2009-05-02 23:03:37 +02:00
|
|
|
/*
|
|
|
|
|
* Copyright (C) 2002 The DOSBox Team
|
|
|
|
|
*
|
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
|
|
|
* (at your option) any later version.
|
|
|
|
|
*
|
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
|
* GNU Library General Public License for more details.
|
|
|
|
|
*
|
|
|
|
|
* You should have received a copy of the GNU General Public License
|
|
|
|
|
* along with this program; if not, write to the Free Software
|
|
|
|
|
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#include "dosbox.h"
|
|
|
|
|
#include "mem.h"
|
|
|
|
|
#include "inout.h"
|
|
|
|
|
#include "int10.h"
|
|
|
|
|
|
|
|
|
|
//TODO Maybe also add PCJR Video Modes could be nice :)
|
|
|
|
|
//TODO include some credits to bochs/plex86 bios i used for info/tables
|
|
|
|
|
|
|
|
|
|
VGAMODES vga_modes[MODE_MAX+1]=
|
|
|
|
|
{//mode vesa class model pg bits sw sh tw th cw ch sstart slength misc pelm crtc actl gdc sequ dac
|
|
|
|
|
{0x00, 0xFFFF, TEXT, CTEXT, 8, 4, 360, 400, 40, 25, 9, 16, 0xB800, 0x0800, 0x67, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x02},
|
|
|
|
|
{0x01, 0xFFFF, TEXT, CTEXT, 8, 4, 360, 400, 40, 25, 9, 16, 0xB800, 0x0800, 0x67, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x02},
|
|
|
|
|
{0x02, 0xFFFF, TEXT, CTEXT, 4, 4, 720, 400, 80, 25, 9, 16, 0xB800, 0x1000, 0x67, 0xFF, 0x01, 0x00, 0x00, 0x01, 0x02},
|
|
|
|
|
{0x03, 0xFFFF, TEXT, CTEXT, 4, 4, 720, 400, 80, 25, 9, 16, 0xB800, 0x1000, 0x67, 0xFF, 0x01, 0x00, 0x00, 0x01, 0x02},
|
|
|
|
|
{0x04, 0xFFFF, GRAPH, CGA, 4, 2, 320, 200, 40, 25, 8, 8, 0xB800, 0x0800, 0x63, 0xFF, 0x02, 0x01, 0x01, 0x02, 0x01},
|
|
|
|
|
{0x05, 0xFFFF, GRAPH, CGA, 1, 2, 320, 200, 40, 25, 8, 8, 0xB800, 0x0800, 0x63, 0xFF, 0x02, 0x01, 0x01, 0x02, 0x01},
|
|
|
|
|
{0x06, 0xFFFF, GRAPH, CGA, 1, 1, 640, 200, 80, 25, 8, 8, 0xB800, 0x1000, 0x63, 0xFF, 0x03, 0x02, 0x02, 0x03, 0x01},
|
|
|
|
|
{0x07, 0xFFFF, TEXT, MTEXT, 4, 4, 720, 400, 80, 25, 9, 16, 0xB000, 0x1000, 0x66, 0xFF, 0x04, 0x03, 0x03, 0x01, 0x00},
|
2009-05-02 23:12:18 +02:00
|
|
|
|
|
|
|
|
{0x0D, 0xFFFF, GRAPH, PLANAR4, 8, 4, 320, 200, 40, 25, 8, 8, 0xA000, 0x2000, 0x63, 0xFF, 0x05, 0x04, 0x04, 0x04, 0x01},
|
|
|
|
|
{0x0E, 0xFFFF, GRAPH, PLANAR4, 4, 4, 640, 200, 80, 25, 8, 8, 0xA000, 0x4000, 0x63, 0xFF, 0x06, 0x04, 0x04, 0x05, 0x01},
|
|
|
|
|
{0x0F, 0xFFFF, GRAPH, PLANAR2, 2, 2, 640, 350, 80, 25, 8, 14, 0xA000, 0x8000, 0xa2, 0xFF, 0x07, 0x05, 0x04, 0x05, 0x00},
|
|
|
|
|
{0x10, 0xFFFF, GRAPH, PLANAR4, 2, 4, 640, 350, 80, 25, 8, 14, 0xA000, 0x8000, 0xa3, 0xFF, 0x07, 0x06, 0x04, 0x05, 0x02},
|
|
|
|
|
{0x11, 0xFFFF, GRAPH, PLANAR1, 1, 1, 640, 480, 80, 30, 8, 16, 0xA000, 0xA000, 0xe3, 0xFF, 0x08, 0x07, 0x04, 0x05, 0x02},
|
|
|
|
|
{0x12, 0xFFFF, GRAPH, PLANAR4, 1, 4, 640, 480, 80, 30, 8, 16, 0xA000, 0xA000, 0xe3, 0xFF, 0x08, 0x06, 0x04, 0x05, 0x02},
|
|
|
|
|
{0x13, 0xFFFF, GRAPH, LINEAR8, 1, 8, 320, 200, 40, 25, 8, 8, 0xA000, 0xFA00, 0x63, 0xFF, 0x09, 0x08, 0x05, 0x06, 0x03}
|
2009-05-02 23:03:37 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* CRTC */
|
|
|
|
|
#define CRTC_MAX_REG 0x18
|
|
|
|
|
#define CRTC_MAX_MODEL 0x09
|
|
|
|
|
static Bit8u crtc_access[CRTC_MAX_REG+1]=
|
|
|
|
|
{ /* 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 */
|
|
|
|
|
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
|
|
|
|
|
};
|
|
|
|
|
static Bit8u crtc_regs[CRTC_MAX_MODEL+1][CRTC_MAX_REG+1]=
|
|
|
|
|
{/* Model 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 */
|
|
|
|
|
/* 00 */ 0x2d,0x27,0x28,0x90,0x2b,0xa0,0xbf,0x1f,0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x14,0x1f,0x96,0xb9,0xa3,0xff,
|
|
|
|
|
/* 01 */ 0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3,0xff,
|
|
|
|
|
/* 02 */ 0x2d,0x27,0x28,0x90,0x2b,0x80,0xbf,0x1f,0x00,0xc1,0x00,0x00,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x14,0x00,0x96,0xb9,0xa2,0xff,
|
|
|
|
|
/* 03 */ 0x5f,0x4f,0x50,0x82,0x54,0x80,0xbf,0x1f,0x00,0xc1,0x00,0x00,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x28,0x00,0x96,0xb9,0xc2,0xff,
|
|
|
|
|
/* 04 */ 0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x28,0x0f,0x96,0xb9,0xa3,0xff,
|
|
|
|
|
/* 05 */ 0x2d,0x27,0x28,0x90,0x2b,0x80,0xbf,0x1f,0x00,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x14,0x00,0x96,0xb9,0xe3,0xff,
|
|
|
|
|
/* 06 */ 0x5f,0x4f,0x50,0x82,0x54,0x80,0xbf,0x1f,0x00,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x28,0x00,0x96,0xb9,0xe3,0xff,
|
|
|
|
|
/* 07 */ 0x5f,0x4f,0x50,0x82,0x54,0x80,0xbf,0x1f,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x83,0x85,0x5d,0x28,0x0f,0x63,0xba,0xe3,0xff,
|
|
|
|
|
/* 08 */ 0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0xea,0x8c,0xdf,0x28,0x00,0xe7,0x04,0xe3,0xff,
|
|
|
|
|
/* 09 */ 0x5f,0x4f,0x50,0x82,0x54,0x80,0xbf,0x1f,0x00,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x28,0x40,0x96,0xb9,0xa3,0xff
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Attribute Controler 0x3c0 */
|
|
|
|
|
#define ACTL_MAX_REG 0x14
|
|
|
|
|
#define ACTL_MAX_MODEL 0x08
|
|
|
|
|
|
|
|
|
|
static Bit8u actl_access[ACTL_MAX_REG+1]=
|
|
|
|
|
{/* 00 01 02 03 04 05 06 07 08 09 0A 0B OC OD OE OF 10 11 12 13 14 */
|
|
|
|
|
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static Bit8u actl_regs[ACTL_MAX_MODEL+1][ACTL_MAX_REG+1]=
|
|
|
|
|
{/* Model 00 01 02 03 04 05 06 07 08 09 0A 0B OC OD OE OF 10 11 12 13 14 */
|
|
|
|
|
/* 00 */ 0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x0c,0x00,0x0f,0x08,0x00,
|
|
|
|
|
/* 01 */ 0x00,0x13,0x15,0x17,0x02,0x04,0x06,0x07,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x01,0x00,0x03,0x00,0x00,
|
|
|
|
|
/* 02 */ 0x00,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x01,0x00,0x01,0x00,0x00,
|
|
|
|
|
/* 03 */ 0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x10,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x0e,0x00,0x0f,0x08,0x00,
|
|
|
|
|
/* 04 */ 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x01,0x00,0x0f,0x00,0x00,
|
|
|
|
|
/* 05 */ 0x00,0x08,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x18,0x00,0x00,0x0b,0x00,0x05,0x00,0x00,
|
|
|
|
|
/* 06 */ 0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00,
|
|
|
|
|
/* 07 */ 0x00,0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,0x01,0x00,0x01,0x00,0x00,
|
|
|
|
|
/* 08 */ 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x41,0x00,0x0f,0x00,0x00
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Sequencer 0x3c4 */
|
|
|
|
|
#define SEQU_MAX_REG 0x04
|
|
|
|
|
#define SEQU_MAX_MODEL 0x06
|
|
|
|
|
|
|
|
|
|
static Bit8u sequ_access[SEQU_MAX_REG+1]=
|
|
|
|
|
{ /* 00 01 02 03 04 */
|
|
|
|
|
0x00,0x00,0x00,0x00,0x00
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static Bit8u sequ_regs[SEQU_MAX_MODEL+1][SEQU_MAX_REG+1]=
|
|
|
|
|
{/* Model 00 01 02 03 04 */
|
|
|
|
|
/* 00 */ 0x03,0x08,0x03,0x00,0x02,
|
|
|
|
|
/* 01 */ 0x03,0x00,0x03,0x00,0x02,
|
|
|
|
|
/* 02 */ 0x03,0x09,0x03,0x00,0x02,
|
|
|
|
|
/* 03 */ 0x03,0x01,0x01,0x00,0x06,
|
|
|
|
|
/* 04 */ 0x03,0x09,0x0f,0x00,0x06,
|
|
|
|
|
/* 05 */ 0x03,0x01,0x0f,0x00,0x06,
|
|
|
|
|
/* 06 */ 0x03,0x01,0x0f,0x00,0x0e
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Graphic ctl 0x3ce */
|
|
|
|
|
#define GRDC_MAX_REG 0x08
|
|
|
|
|
#define GRDC_MAX_MODEL 0x05
|
|
|
|
|
|
|
|
|
|
static Bit8u grdc_access[GRDC_MAX_REG+1]=
|
|
|
|
|
{ /* 00 01 02 03 04 05 06 07 08 */
|
|
|
|
|
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static Bit8u grdc_regs[GRDC_MAX_MODEL+1][GRDC_MAX_REG+1]=
|
|
|
|
|
{/* Model 00 01 02 03 04 05 06 07 08 */
|
|
|
|
|
/* 00 */ 0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x0f,0xff,
|
|
|
|
|
/* 01 */ 0x00,0x00,0x00,0x00,0x00,0x30,0x0f,0x0f,0xff,
|
|
|
|
|
/* 02 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x0d,0x0f,0xff,
|
|
|
|
|
/* 03 */ 0x00,0x00,0x00,0x00,0x00,0x10,0x0a,0x0f,0xff,
|
|
|
|
|
/* 04 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff,
|
|
|
|
|
/* 05 */ 0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f,0xff
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Default Palette */
|
|
|
|
|
#define DAC_MAX_MODEL 3
|
|
|
|
|
|
|
|
|
|
static Bit8u dac_regs[DAC_MAX_MODEL+1]=
|
|
|
|
|
{0x3f,0x3f,0x3f,0xff};
|
|
|
|
|
|
|
|
|
|
/* Mono */
|
|
|
|
|
static Bit8u palette0[63+1][3]=
|
|
|
|
|
{
|
|
|
|
|
0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00,
|
|
|
|
|
0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a,
|
|
|
|
|
0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a,
|
|
|
|
|
0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f,
|
|
|
|
|
0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00,
|
|
|
|
|
0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a,
|
|
|
|
|
0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a,
|
|
|
|
|
0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static Bit8u palette1[63+1][3]=
|
|
|
|
|
{
|
|
|
|
|
0x00,0x00,0x00, 0x00,0x00,0x2a, 0x00,0x2a,0x00, 0x00,0x2a,0x2a, 0x2a,0x00,0x00, 0x2a,0x00,0x2a, 0x2a,0x15,0x00, 0x2a,0x2a,0x2a,
|
|
|
|
|
0x00,0x00,0x00, 0x00,0x00,0x2a, 0x00,0x2a,0x00, 0x00,0x2a,0x2a, 0x2a,0x00,0x00, 0x2a,0x00,0x2a, 0x2a,0x15,0x00, 0x2a,0x2a,0x2a,
|
|
|
|
|
0x15,0x15,0x15, 0x15,0x15,0x3f, 0x15,0x3f,0x15, 0x15,0x3f,0x3f, 0x3f,0x15,0x15, 0x3f,0x15,0x3f, 0x3f,0x3f,0x15, 0x3f,0x3f,0x3f,
|
|
|
|
|
0x15,0x15,0x15, 0x15,0x15,0x3f, 0x15,0x3f,0x15, 0x15,0x3f,0x3f, 0x3f,0x15,0x15, 0x3f,0x15,0x3f, 0x3f,0x3f,0x15, 0x3f,0x3f,0x3f,
|
|
|
|
|
0x00,0x00,0x00, 0x00,0x00,0x2a, 0x00,0x2a,0x00, 0x00,0x2a,0x2a, 0x2a,0x00,0x00, 0x2a,0x00,0x2a, 0x2a,0x15,0x00, 0x2a,0x2a,0x2a,
|
|
|
|
|
0x00,0x00,0x00, 0x00,0x00,0x2a, 0x00,0x2a,0x00, 0x00,0x2a,0x2a, 0x2a,0x00,0x00, 0x2a,0x00,0x2a, 0x2a,0x15,0x00, 0x2a,0x2a,0x2a,
|
|
|
|
|
0x15,0x15,0x15, 0x15,0x15,0x3f, 0x15,0x3f,0x15, 0x15,0x3f,0x3f, 0x3f,0x15,0x15, 0x3f,0x15,0x3f, 0x3f,0x3f,0x15, 0x3f,0x3f,0x3f,
|
|
|
|
|
0x15,0x15,0x15, 0x15,0x15,0x3f, 0x15,0x3f,0x15, 0x15,0x3f,0x3f, 0x3f,0x15,0x15, 0x3f,0x15,0x3f, 0x3f,0x3f,0x15, 0x3f,0x3f,0x3f
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static Bit8u palette2[63+1][3]=
|
|
|
|
|
{
|
|
|
|
|
0x00,0x00,0x00, 0x00,0x00,0x2a, 0x00,0x2a,0x00, 0x00,0x2a,0x2a, 0x2a,0x00,0x00, 0x2a,0x00,0x2a, 0x2a,0x2a,0x00, 0x2a,0x2a,0x2a,
|
|
|
|
|
0x00,0x00,0x15, 0x00,0x00,0x3f, 0x00,0x2a,0x15, 0x00,0x2a,0x3f, 0x2a,0x00,0x15, 0x2a,0x00,0x3f, 0x2a,0x2a,0x15, 0x2a,0x2a,0x3f,
|
|
|
|
|
0x00,0x15,0x00, 0x00,0x15,0x2a, 0x00,0x3f,0x00, 0x00,0x3f,0x2a, 0x2a,0x15,0x00, 0x2a,0x15,0x2a, 0x2a,0x3f,0x00, 0x2a,0x3f,0x2a,
|
|
|
|
|
0x00,0x15,0x15, 0x00,0x15,0x3f, 0x00,0x3f,0x15, 0x00,0x3f,0x3f, 0x2a,0x15,0x15, 0x2a,0x15,0x3f, 0x2a,0x3f,0x15, 0x2a,0x3f,0x3f,
|
|
|
|
|
0x15,0x00,0x00, 0x15,0x00,0x2a, 0x15,0x2a,0x00, 0x15,0x2a,0x2a, 0x3f,0x00,0x00, 0x3f,0x00,0x2a, 0x3f,0x2a,0x00, 0x3f,0x2a,0x2a,
|
|
|
|
|
0x15,0x00,0x15, 0x15,0x00,0x3f, 0x15,0x2a,0x15, 0x15,0x2a,0x3f, 0x3f,0x00,0x15, 0x3f,0x00,0x3f, 0x3f,0x2a,0x15, 0x3f,0x2a,0x3f,
|
|
|
|
|
0x15,0x15,0x00, 0x15,0x15,0x2a, 0x15,0x3f,0x00, 0x15,0x3f,0x2a, 0x3f,0x15,0x00, 0x3f,0x15,0x2a, 0x3f,0x3f,0x00, 0x3f,0x3f,0x2a,
|
|
|
|
|
0x15,0x15,0x15, 0x15,0x15,0x3f, 0x15,0x3f,0x15, 0x15,0x3f,0x3f, 0x3f,0x15,0x15, 0x3f,0x15,0x3f, 0x3f,0x3f,0x15, 0x3f,0x3f,0x3f
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static Bit8u palette3[256][3]=
|
|
|
|
|
{
|
|
|
|
|
0x00,0x00,0x00, 0x00,0x00,0x2a, 0x00,0x2a,0x00, 0x00,0x2a,0x2a, 0x2a,0x00,0x00, 0x2a,0x00,0x2a, 0x2a,0x15,0x00, 0x2a,0x2a,0x2a,
|
|
|
|
|
0x15,0x15,0x15, 0x15,0x15,0x3f, 0x15,0x3f,0x15, 0x15,0x3f,0x3f, 0x3f,0x15,0x15, 0x3f,0x15,0x3f, 0x3f,0x3f,0x15, 0x3f,0x3f,0x3f,
|
|
|
|
|
0x00,0x00,0x00, 0x05,0x05,0x05, 0x08,0x08,0x08, 0x0b,0x0b,0x0b, 0x0e,0x0e,0x0e, 0x11,0x11,0x11, 0x14,0x14,0x14, 0x18,0x18,0x18,
|
|
|
|
|
0x1c,0x1c,0x1c, 0x20,0x20,0x20, 0x24,0x24,0x24, 0x28,0x28,0x28, 0x2d,0x2d,0x2d, 0x32,0x32,0x32, 0x38,0x38,0x38, 0x3f,0x3f,0x3f,
|
|
|
|
|
0x00,0x00,0x3f, 0x10,0x00,0x3f, 0x1f,0x00,0x3f, 0x2f,0x00,0x3f, 0x3f,0x00,0x3f, 0x3f,0x00,0x2f, 0x3f,0x00,0x1f, 0x3f,0x00,0x10,
|
|
|
|
|
0x3f,0x00,0x00, 0x3f,0x10,0x00, 0x3f,0x1f,0x00, 0x3f,0x2f,0x00, 0x3f,0x3f,0x00, 0x2f,0x3f,0x00, 0x1f,0x3f,0x00, 0x10,0x3f,0x00,
|
|
|
|
|
0x00,0x3f,0x00, 0x00,0x3f,0x10, 0x00,0x3f,0x1f, 0x00,0x3f,0x2f, 0x00,0x3f,0x3f, 0x00,0x2f,0x3f, 0x00,0x1f,0x3f, 0x00,0x10,0x3f,
|
|
|
|
|
0x1f,0x1f,0x3f, 0x27,0x1f,0x3f, 0x2f,0x1f,0x3f, 0x37,0x1f,0x3f, 0x3f,0x1f,0x3f, 0x3f,0x1f,0x37, 0x3f,0x1f,0x2f, 0x3f,0x1f,0x27,
|
|
|
|
|
|
|
|
|
|
0x3f,0x1f,0x1f, 0x3f,0x27,0x1f, 0x3f,0x2f,0x1f, 0x3f,0x37,0x1f, 0x3f,0x3f,0x1f, 0x37,0x3f,0x1f, 0x2f,0x3f,0x1f, 0x27,0x3f,0x1f,
|
|
|
|
|
0x1f,0x3f,0x1f, 0x1f,0x3f,0x27, 0x1f,0x3f,0x2f, 0x1f,0x3f,0x37, 0x1f,0x3f,0x3f, 0x1f,0x37,0x3f, 0x1f,0x2f,0x3f, 0x1f,0x27,0x3f,
|
|
|
|
|
0x2d,0x2d,0x3f, 0x31,0x2d,0x3f, 0x36,0x2d,0x3f, 0x3a,0x2d,0x3f, 0x3f,0x2d,0x3f, 0x3f,0x2d,0x3a, 0x3f,0x2d,0x36, 0x3f,0x2d,0x31,
|
|
|
|
|
0x3f,0x2d,0x2d, 0x3f,0x31,0x2d, 0x3f,0x36,0x2d, 0x3f,0x3a,0x2d, 0x3f,0x3f,0x2d, 0x3a,0x3f,0x2d, 0x36,0x3f,0x2d, 0x31,0x3f,0x2d,
|
|
|
|
|
0x2d,0x3f,0x2d, 0x2d,0x3f,0x31, 0x2d,0x3f,0x36, 0x2d,0x3f,0x3a, 0x2d,0x3f,0x3f, 0x2d,0x3a,0x3f, 0x2d,0x36,0x3f, 0x2d,0x31,0x3f,
|
|
|
|
|
0x00,0x00,0x1c, 0x07,0x00,0x1c, 0x0e,0x00,0x1c, 0x15,0x00,0x1c, 0x1c,0x00,0x1c, 0x1c,0x00,0x15, 0x1c,0x00,0x0e, 0x1c,0x00,0x07,
|
|
|
|
|
0x1c,0x00,0x00, 0x1c,0x07,0x00, 0x1c,0x0e,0x00, 0x1c,0x15,0x00, 0x1c,0x1c,0x00, 0x15,0x1c,0x00, 0x0e,0x1c,0x00, 0x07,0x1c,0x00,
|
|
|
|
|
0x00,0x1c,0x00, 0x00,0x1c,0x07, 0x00,0x1c,0x0e, 0x00,0x1c,0x15, 0x00,0x1c,0x1c, 0x00,0x15,0x1c, 0x00,0x0e,0x1c, 0x00,0x07,0x1c,
|
|
|
|
|
|
|
|
|
|
0x0e,0x0e,0x1c, 0x11,0x0e,0x1c, 0x15,0x0e,0x1c, 0x18,0x0e,0x1c, 0x1c,0x0e,0x1c, 0x1c,0x0e,0x18, 0x1c,0x0e,0x15, 0x1c,0x0e,0x11,
|
|
|
|
|
0x1c,0x0e,0x0e, 0x1c,0x11,0x0e, 0x1c,0x15,0x0e, 0x1c,0x18,0x0e, 0x1c,0x1c,0x0e, 0x18,0x1c,0x0e, 0x15,0x1c,0x0e, 0x11,0x1c,0x0e,
|
|
|
|
|
0x0e,0x1c,0x0e, 0x0e,0x1c,0x11, 0x0e,0x1c,0x15, 0x0e,0x1c,0x18, 0x0e,0x1c,0x1c, 0x0e,0x18,0x1c, 0x0e,0x15,0x1c, 0x0e,0x11,0x1c,
|
|
|
|
|
0x14,0x14,0x1c, 0x16,0x14,0x1c, 0x18,0x14,0x1c, 0x1a,0x14,0x1c, 0x1c,0x14,0x1c, 0x1c,0x14,0x1a, 0x1c,0x14,0x18, 0x1c,0x14,0x16,
|
|
|
|
|
0x1c,0x14,0x14, 0x1c,0x16,0x14, 0x1c,0x18,0x14, 0x1c,0x1a,0x14, 0x1c,0x1c,0x14, 0x1a,0x1c,0x14, 0x18,0x1c,0x14, 0x16,0x1c,0x14,
|
|
|
|
|
0x14,0x1c,0x14, 0x14,0x1c,0x16, 0x14,0x1c,0x18, 0x14,0x1c,0x1a, 0x14,0x1c,0x1c, 0x14,0x1a,0x1c, 0x14,0x18,0x1c, 0x14,0x16,0x1c,
|
|
|
|
|
0x00,0x00,0x10, 0x04,0x00,0x10, 0x08,0x00,0x10, 0x0c,0x00,0x10, 0x10,0x00,0x10, 0x10,0x00,0x0c, 0x10,0x00,0x08, 0x10,0x00,0x04,
|
|
|
|
|
0x10,0x00,0x00, 0x10,0x04,0x00, 0x10,0x08,0x00, 0x10,0x0c,0x00, 0x10,0x10,0x00, 0x0c,0x10,0x00, 0x08,0x10,0x00, 0x04,0x10,0x00,
|
|
|
|
|
|
|
|
|
|
0x00,0x10,0x00, 0x00,0x10,0x04, 0x00,0x10,0x08, 0x00,0x10,0x0c, 0x00,0x10,0x10, 0x00,0x0c,0x10, 0x00,0x08,0x10, 0x00,0x04,0x10,
|
|
|
|
|
0x08,0x08,0x10, 0x0a,0x08,0x10, 0x0c,0x08,0x10, 0x0e,0x08,0x10, 0x10,0x08,0x10, 0x10,0x08,0x0e, 0x10,0x08,0x0c, 0x10,0x08,0x0a,
|
|
|
|
|
0x10,0x08,0x08, 0x10,0x0a,0x08, 0x10,0x0c,0x08, 0x10,0x0e,0x08, 0x10,0x10,0x08, 0x0e,0x10,0x08, 0x0c,0x10,0x08, 0x0a,0x10,0x08,
|
|
|
|
|
0x08,0x10,0x08, 0x08,0x10,0x0a, 0x08,0x10,0x0c, 0x08,0x10,0x0e, 0x08,0x10,0x10, 0x08,0x0e,0x10, 0x08,0x0c,0x10, 0x08,0x0a,0x10,
|
|
|
|
|
0x0b,0x0b,0x10, 0x0c,0x0b,0x10, 0x0d,0x0b,0x10, 0x0f,0x0b,0x10, 0x10,0x0b,0x10, 0x10,0x0b,0x0f, 0x10,0x0b,0x0d, 0x10,0x0b,0x0c,
|
|
|
|
|
0x10,0x0b,0x0b, 0x10,0x0c,0x0b, 0x10,0x0d,0x0b, 0x10,0x0f,0x0b, 0x10,0x10,0x0b, 0x0f,0x10,0x0b, 0x0d,0x10,0x0b, 0x0c,0x10,0x0b,
|
|
|
|
|
0x0b,0x10,0x0b, 0x0b,0x10,0x0c, 0x0b,0x10,0x0d, 0x0b,0x10,0x0f, 0x0b,0x10,0x10, 0x0b,0x0f,0x10, 0x0b,0x0d,0x10, 0x0b,0x0c,0x10,
|
|
|
|
|
0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static Bit8u static_functionality[0x10]=
|
|
|
|
|
{
|
|
|
|
|
/* 0 */ 0xff, // All modes supported #1
|
|
|
|
|
/* 1 */ 0xff, // All modes supported #2
|
|
|
|
|
/* 2 */ 0x0f, // All modes supported #3
|
|
|
|
|
/* 3 */ 0x00, 0x00, 0x00, 0x00, // reserved
|
|
|
|
|
/* 7 */ 0x07, // 200, 350, 400 scan lines
|
|
|
|
|
/* 8 */ 0xFF, // FIXME i don't know what this is
|
|
|
|
|
/* 9 */ 0xFF, // FIXME i don't know what this is
|
|
|
|
|
/* a */ 0xe3, // Change to add new functions
|
|
|
|
|
/* b */ 0x0c, // Change to add new functions
|
|
|
|
|
/* c */ 0x00, // reserved
|
|
|
|
|
/* d */ 0x00, // reserved
|
|
|
|
|
/* e */ 0x00, // Change to add new functions
|
|
|
|
|
/* f */ 0x00 // reserved
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static Bit8u FindVideoMode(Bit8u mode) {
|
|
|
|
|
Bit8u line=0xff;
|
|
|
|
|
for(Bit8u i=0;i<=MODE_MAX;i++) {
|
|
|
|
|
if(vga_modes[i].svgamode==mode) {
|
|
|
|
|
line=i;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return line;
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
VGAMODES * GetCurrentMode(void) {
|
|
|
|
|
Bit8u ret=FindVideoMode(real_readb(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE)&127);
|
|
|
|
|
if (ret==0xff) return 0;
|
|
|
|
|
return &vga_modes[ret];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
void INT10_SetVideoMode(Bit8u mode) {
|
|
|
|
|
|
|
|
|
|
bool clearmem=(mode & 128)==0;
|
|
|
|
|
Bit8u *palette;
|
|
|
|
|
Bit16u i,twidth,theight,cheight;
|
|
|
|
|
Bit8u modeset_ctl,video_ctl,vga_switches;
|
|
|
|
|
Bit16u crtc_addr;
|
|
|
|
|
Bit8u line;
|
|
|
|
|
|
|
|
|
|
mode&=mode & 127;
|
|
|
|
|
line=FindVideoMode(mode);
|
|
|
|
|
if (line==0xff) {
|
|
|
|
|
LOG_ERROR("INT10:Trying to set non supported video mode %X",mode);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
twidth=vga_modes[line].twidth;
|
|
|
|
|
theight=vga_modes[line].theight;
|
|
|
|
|
cheight=vga_modes[line].cheight;
|
|
|
|
|
|
|
|
|
|
// Read the bios vga control
|
|
|
|
|
video_ctl=real_readb(BIOSMEM_SEG,BIOSMEM_VIDEO_CTL);
|
|
|
|
|
|
|
|
|
|
// Read the bios vga switches
|
|
|
|
|
vga_switches=real_readb(BIOSMEM_SEG,BIOSMEM_SWITCHES);
|
|
|
|
|
|
|
|
|
|
// Read the bios mode set control
|
|
|
|
|
modeset_ctl=real_readb(BIOSMEM_SEG,BIOSMEM_MODESET_CTL);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
if((modeset_ctl&0x08)==0) {
|
|
|
|
|
// Set the PEL mask
|
|
|
|
|
IO_Write(VGAREG_PEL_MASK,vga_modes[line].pelmask);
|
|
|
|
|
// Set the whole dac always, from 0
|
|
|
|
|
IO_Write(VGAREG_DAC_WRITE_ADDRESS,0x00);
|
|
|
|
|
// From which palette
|
|
|
|
|
switch(vga_modes[line].dacmodel) {
|
|
|
|
|
case 0:
|
|
|
|
|
palette=(Bit8u*)&palette0;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
palette=(Bit8u*)&palette1;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
palette=(Bit8u*)&palette2;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
palette=(Bit8u*)&palette3;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
palette=(Bit8u*)&palette0;/*for gcc*/
|
|
|
|
|
E_Exit("INT10: palette error in setvidmode");
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
// Set the actual palette
|
|
|
|
|
for (i=0;i<256;i++) {
|
|
|
|
|
if (i<=dac_regs[vga_modes[line].dacmodel]) {
|
|
|
|
|
IO_Write(VGAREG_DAC_DATA,palette[(i*3)+0]);
|
|
|
|
|
IO_Write(VGAREG_DAC_DATA,palette[(i*3)+1]);
|
|
|
|
|
IO_Write(VGAREG_DAC_DATA,palette[(i*3)+2]);
|
|
|
|
|
} else {
|
|
|
|
|
IO_Write(VGAREG_DAC_DATA,0);
|
|
|
|
|
IO_Write(VGAREG_DAC_DATA,0);
|
|
|
|
|
IO_Write(VGAREG_DAC_DATA,0);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Reset Attribute ctl into address mode just to be safe */
|
|
|
|
|
|
|
|
|
|
IO_Read(VGAREG_ACTL_RESET);
|
|
|
|
|
// Set Attribute Ctl
|
|
|
|
|
for(i=0;i<=ACTL_MAX_REG;i++) {
|
|
|
|
|
IO_Write(VGAREG_ACTL_ADDRESS,(Bit8u)i);
|
|
|
|
|
IO_Write(VGAREG_ACTL_WRITE_DATA,actl_regs[vga_modes[line].actlmodel][i]);
|
|
|
|
|
}
|
|
|
|
|
// Set Sequencer Ctl
|
|
|
|
|
for(i=0;i<=SEQU_MAX_REG;i++) {
|
|
|
|
|
IO_Write(VGAREG_SEQU_ADDRESS,(Bit8u)i);
|
|
|
|
|
IO_Write(VGAREG_SEQU_DATA,sequ_regs[vga_modes[line].sequmodel][i]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Set Grafx Ctl
|
|
|
|
|
for(i=0;i<=GRDC_MAX_REG;i++) {
|
|
|
|
|
IO_Write(VGAREG_GRDC_ADDRESS,(Bit8u)i);
|
|
|
|
|
IO_Write(VGAREG_GRDC_DATA,grdc_regs[vga_modes[line].grdcmodel][i]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Set CRTC address VGA or MDA
|
|
|
|
|
crtc_addr=vga_modes[line].memmodel==MTEXT?VGAREG_MDA_CRTC_ADDRESS:VGAREG_VGA_CRTC_ADDRESS;
|
|
|
|
|
// Set CRTC regs
|
|
|
|
|
for(i=0;i<=CRTC_MAX_REG;i++) {
|
|
|
|
|
IO_Write(crtc_addr,(Bit8u)i);
|
|
|
|
|
IO_Write(crtc_addr+1,crtc_regs[vga_modes[line].crtcmodel][i]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Set the misc register
|
|
|
|
|
IO_Write(VGAREG_WRITE_MISC_OUTPUT,vga_modes[line].miscreg);
|
|
|
|
|
|
|
|
|
|
// Enable video
|
|
|
|
|
IO_Write(VGAREG_ACTL_ADDRESS,0x20);
|
|
|
|
|
IO_Read(VGAREG_ACTL_RESET);
|
|
|
|
|
Bit32u tel;
|
|
|
|
|
if(clearmem) {
|
|
|
|
|
if(vga_modes[line].type==TEXT) {
|
2009-05-02 23:12:18 +02:00
|
|
|
PhysPt dest=PhysMake(vga_modes[line].sstart,0);
|
2009-05-02 23:03:37 +02:00
|
|
|
for (tel=0;tel<0x4000;tel++) {
|
|
|
|
|
mem_writew(dest,0x0720);
|
|
|
|
|
dest+=2;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
2009-05-02 23:12:18 +02:00
|
|
|
PhysPt dest=PhysMake(0xb800,0);
|
2009-05-02 23:03:37 +02:00
|
|
|
for (tel=0;tel<0x4000;tel++) {
|
|
|
|
|
mem_writew(dest,0x0000);
|
|
|
|
|
dest+=2;
|
|
|
|
|
}
|
2009-05-02 23:12:18 +02:00
|
|
|
dest=PhysMake(0xa000,0);
|
2009-05-02 23:03:37 +02:00
|
|
|
for (tel=0;tel<0x8000;tel++) {
|
|
|
|
|
mem_writew(dest,0x0000);
|
|
|
|
|
dest+=2;
|
|
|
|
|
}
|
|
|
|
|
// FIXME should handle gfx mode
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
// Set the BIOS mem
|
|
|
|
|
real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE,mode|((!clearmem) << 7));
|
|
|
|
|
real_writew(BIOSMEM_SEG,BIOSMEM_NB_COLS,twidth);
|
|
|
|
|
real_writew(BIOSMEM_SEG,BIOSMEM_PAGE_SIZE,vga_modes[line].slength);
|
|
|
|
|
real_writew(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS,crtc_addr);
|
|
|
|
|
real_writeb(BIOSMEM_SEG,BIOSMEM_NB_ROWS,theight-1);
|
|
|
|
|
real_writew(BIOSMEM_SEG,BIOSMEM_CHAR_HEIGHT,cheight);
|
|
|
|
|
real_writeb(BIOSMEM_SEG,BIOSMEM_VIDEO_CTL,(0x60|(clearmem << 7)));
|
|
|
|
|
real_writeb(BIOSMEM_SEG,BIOSMEM_SWITCHES,0xF9);
|
|
|
|
|
real_writeb(BIOSMEM_SEG,BIOSMEM_MODESET_CTL,real_readb(BIOSMEM_SEG,BIOSMEM_MODESET_CTL)&0x7f);
|
|
|
|
|
|
|
|
|
|
// FIXME We nearly have the good tables. to be reworked
|
|
|
|
|
real_writeb(BIOSMEM_SEG,BIOSMEM_DCC_INDEX,0x08); // 8 is VGA should be ok for now
|
|
|
|
|
real_writew(BIOSMEM_SEG,BIOSMEM_VS_POINTER,0x00);
|
|
|
|
|
real_writew(BIOSMEM_SEG,BIOSMEM_VS_POINTER+2,0x00);
|
|
|
|
|
|
|
|
|
|
// FIXME
|
|
|
|
|
real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x00); // Unavailable on vanilla vga, but...
|
|
|
|
|
real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,0x00); // Unavailable on vanilla vga, but...
|
|
|
|
|
|
|
|
|
|
// Set cursor shape
|
|
|
|
|
if(vga_modes[line].type==TEXT) {
|
|
|
|
|
//TODO cursor shape biosfn_set_cursor_shape(0x06,0x07);
|
|
|
|
|
}
|
|
|
|
|
// Set cursor pos for page 0..7
|
|
|
|
|
for(i=0;i<8;i++) INT10_SetCursorPos(0,0,(Bit8u)i);
|
|
|
|
|
// Set active page 0
|
|
|
|
|
INT10_SetActivePage(0);
|
|
|
|
|
/* Set some interrupt vectors */
|
|
|
|
|
RealSetVec(0x43,int10_romarea.font_8_first);
|
|
|
|
|
};
|
