2009-05-02 23:03:37 +02:00
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/*
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2009-05-02 23:53:27 +02:00
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* Copyright (C) 2002-2004 The DOSBox Team
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2009-05-02 23:03:37 +02:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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2009-05-03 00:02:15 +02:00
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* GNU General Public License for more details.
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2009-05-02 23:03:37 +02:00
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include "dosbox.h"
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#include "mem.h"
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#include "inout.h"
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#include "int10.h"
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#define ACTL_MAX_REG 0x14
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void INT10_SetSinglePaletteRegister(Bit8u reg,Bit8u val) {
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if(reg<=ACTL_MAX_REG) {
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IO_Read(VGAREG_ACTL_RESET);
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IO_Write(VGAREG_ACTL_ADDRESS,reg);
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IO_Write(VGAREG_ACTL_WRITE_DATA,val);
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}
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2009-05-02 23:43:00 +02:00
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IO_Write(VGAREG_ACTL_ADDRESS,32); //Enable output and protect palette
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2009-05-02 23:03:37 +02:00
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}
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void INT10_SetOverscanBorderColor(Bit8u val) {
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IO_Read(VGAREG_ACTL_RESET);
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IO_Write(VGAREG_ACTL_ADDRESS,0x11);
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IO_Write(VGAREG_ACTL_WRITE_DATA,val);
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2009-05-02 23:43:00 +02:00
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IO_Write(VGAREG_ACTL_ADDRESS,32); //Enable output and protect palette
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2009-05-02 23:03:37 +02:00
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}
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2009-05-02 23:12:18 +02:00
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void INT10_SetAllPaletteRegisters(PhysPt data) {
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2009-05-02 23:03:37 +02:00
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IO_Read(VGAREG_ACTL_RESET);
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// First the colors
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for(Bit8u i=0;i<0x10;i++) {
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IO_Write(VGAREG_ACTL_ADDRESS,i);
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IO_Write(VGAREG_ACTL_WRITE_DATA,mem_readb(data));
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data++;
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}
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// Then the border
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IO_Write(VGAREG_ACTL_ADDRESS,0x11);
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IO_Write(VGAREG_ACTL_WRITE_DATA,mem_readb(data));
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2009-05-02 23:43:00 +02:00
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IO_Write(VGAREG_ACTL_ADDRESS,32); //Enable output and protect palette
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2009-05-02 23:03:37 +02:00
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}
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void INT10_ToggleBlinkingBit(Bit8u state) {
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Bit8u value;
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state&=0x01;
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IO_Read(VGAREG_ACTL_RESET);
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IO_Write(VGAREG_ACTL_ADDRESS,0x10);
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value=IO_Read(VGAREG_ACTL_READ_DATA);
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value&=0xf7;
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value|=state<<3;
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IO_Read(VGAREG_ACTL_RESET);
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IO_Write(VGAREG_ACTL_ADDRESS,0x10);
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IO_Write(VGAREG_ACTL_WRITE_DATA,value);
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2009-05-02 23:43:00 +02:00
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IO_Write(VGAREG_ACTL_ADDRESS,32); //Enable output and protect palette
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2009-05-02 23:03:37 +02:00
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}
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void INT10_GetSinglePaletteRegister(Bit8u reg,Bit8u * val) {
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if(reg<=ACTL_MAX_REG) {
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IO_Read(VGAREG_ACTL_RESET);
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2009-05-02 23:43:00 +02:00
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IO_Write(VGAREG_ACTL_ADDRESS,reg+32);
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2009-05-02 23:03:37 +02:00
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*val=IO_Read(VGAREG_ACTL_READ_DATA);
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}
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}
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void INT10_GetOverscanBorderColor(Bit8u * val) {
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IO_Read(VGAREG_ACTL_RESET);
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2009-05-02 23:43:00 +02:00
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IO_Write(VGAREG_ACTL_ADDRESS,0x11+32);
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2009-05-02 23:03:37 +02:00
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*val=IO_Read(VGAREG_ACTL_READ_DATA);
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}
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2009-05-02 23:12:18 +02:00
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void INT10_GetAllPaletteRegisters(PhysPt data) {
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2009-05-02 23:03:37 +02:00
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IO_Read(VGAREG_ACTL_RESET);
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// First the colors
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for(Bit8u i=0;i<0x10;i++) {
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IO_Write(VGAREG_ACTL_ADDRESS,i);
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mem_writeb(data,IO_Read(VGAREG_ACTL_READ_DATA));
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data++;
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}
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// Then the border
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2009-05-02 23:43:00 +02:00
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IO_Write(VGAREG_ACTL_ADDRESS,0x11+32);
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2009-05-02 23:03:37 +02:00
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mem_writeb(data,IO_Read(VGAREG_ACTL_READ_DATA));
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}
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void INT10_SetSingleDacRegister(Bit8u index,Bit8u red,Bit8u green,Bit8u blue) {
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IO_Write(VGAREG_DAC_WRITE_ADDRESS,(Bit8u)index);
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IO_Write(VGAREG_DAC_DATA,red);
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IO_Write(VGAREG_DAC_DATA,green);
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IO_Write(VGAREG_DAC_DATA,blue);
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}
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void INT10_GetSingleDacRegister(Bit8u index,Bit8u * red,Bit8u * green,Bit8u * blue) {
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IO_Write(VGAREG_DAC_READ_ADDRESS,index);
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*red=IO_Read(VGAREG_DAC_DATA);
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*green=IO_Read(VGAREG_DAC_DATA);
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*blue=IO_Read(VGAREG_DAC_DATA);
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}
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2009-05-02 23:12:18 +02:00
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void INT10_SetDACBlock(Bit16u index,Bit16u count,PhysPt data) {
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2009-05-02 23:03:37 +02:00
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IO_Write(VGAREG_DAC_WRITE_ADDRESS,(Bit8u)index);
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for (;count>0;count--) {
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IO_Write(VGAREG_DAC_DATA,mem_readb(data++));
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IO_Write(VGAREG_DAC_DATA,mem_readb(data++));
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IO_Write(VGAREG_DAC_DATA,mem_readb(data++));
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}
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}
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2009-05-02 23:12:18 +02:00
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void INT10_GetDACBlock(Bit16u index,Bit16u count,PhysPt data) {
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2009-05-02 23:03:37 +02:00
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IO_Write(VGAREG_DAC_WRITE_ADDRESS,(Bit8u)index);
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for (;count>0;count--) {
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mem_writeb(data++,IO_Read(VGAREG_DAC_DATA));
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mem_writeb(data++,IO_Read(VGAREG_DAC_DATA));
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mem_writeb(data++,IO_Read(VGAREG_DAC_DATA));
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}
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2009-05-02 23:43:00 +02:00
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}
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void INT10_SelectDACPage(Bit8u function,Bit8u mode) {
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IO_Read(VGAREG_ACTL_RESET);
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IO_Write(VGAREG_ACTL_ADDRESS,0x10);
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Bit8u old10=IO_Read(VGAREG_ACTL_READ_DATA);
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if (!function) { //Select paging mode
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if (mode) old10|=0x80;
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else old10&=0x7f;
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IO_Write(VGAREG_ACTL_ADDRESS,0x10);
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IO_Write(VGAREG_ACTL_WRITE_DATA,old10);
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} else { //Select page
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if (!(old10 & 0x80)) mode<<=2;
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mode&=0xf;
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IO_Write(VGAREG_ACTL_ADDRESS,0x14);
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IO_Write(VGAREG_ACTL_WRITE_DATA,mode);
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}
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IO_Write(VGAREG_ACTL_ADDRESS,32); //Enable output and protect palette
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}
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void INT10_SetPelMask(Bit8u mask) {
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IO_Write(VGAREG_PEL_MASK,mask);
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}
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void INT10_GetPelMask(Bit8u & mask) {
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mask=IO_Read(VGAREG_PEL_MASK);
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}
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void INT10_SetBackgroundBorder(Bit8u val) {
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2009-05-02 23:53:27 +02:00
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Bitu temp=real_readb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL);
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temp=(temp & 0xe0) | (val & 0x1f);
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real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,temp);
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IO_Write(0x3d9,temp);
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2009-05-02 23:43:00 +02:00
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}
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void INT10_SetColorSelect(Bit8u val) {
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2009-05-02 23:53:27 +02:00
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Bitu temp=real_readb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL);
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temp=(temp & 0xdf) | ((val & 1) ? 0x20 : 0x0);
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real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,temp);
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IO_Write(0x3d9,temp);
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2009-05-02 23:43:00 +02:00
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}
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