2010-11-05 05:55:33 +01:00
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/*
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2011-06-22 06:18:55 +02:00
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* Copyright (C) 2002-2011 The DOSBox Team
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2010-11-05 05:55:33 +01:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef DOSBOX_CPU_H
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#define DOSBOX_CPU_H
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#ifndef DOSBOX_DOSBOX_H
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#include "dosbox.h"
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#endif
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#ifndef DOSBOX_REGS_H
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#include "regs.h"
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#endif
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#ifndef DOSBOX_MEM_H
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#include "mem.h"
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#endif
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#define CPU_AUTODETERMINE_NONE 0x00
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#define CPU_AUTODETERMINE_CORE 0x01
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#define CPU_AUTODETERMINE_CYCLES 0x02
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#define CPU_AUTODETERMINE_SHIFT 0x02
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#define CPU_AUTODETERMINE_MASK 0x03
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#define CPU_CYCLES_LOWER_LIMIT 100
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#define CPU_ARCHTYPE_MIXED 0xff
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#define CPU_ARCHTYPE_386SLOW 0x30
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#define CPU_ARCHTYPE_386FAST 0x35
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#define CPU_ARCHTYPE_486OLDSLOW 0x40
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#define CPU_ARCHTYPE_486NEWSLOW 0x45
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#define CPU_ARCHTYPE_PENTIUMSLOW 0x50
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/* CPU Cycle Timing */
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extern Bit32s CPU_Cycles;
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extern Bit32s CPU_CycleLeft;
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extern Bit32s CPU_CycleMax;
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extern Bit32s CPU_OldCycleMax;
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extern Bit32s CPU_CyclePercUsed;
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extern Bit32s CPU_CycleLimit;
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extern Bit64s CPU_IODelayRemoved;
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extern bool CPU_CycleAutoAdjust;
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extern bool CPU_SkipCycleAutoAdjust;
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extern Bitu CPU_AutoDetermineMode;
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extern Bitu CPU_ArchitectureType;
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extern Bitu CPU_PrefetchQueueSize;
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/* Some common Defines */
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/* A CPU Handler */
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typedef Bits (CPU_Decoder)(void);
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extern CPU_Decoder * cpudecoder;
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Bits CPU_Core_Normal_Run(void);
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Bits CPU_Core_Normal_Trap_Run(void);
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Bits CPU_Core_Simple_Run(void);
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Bits CPU_Core_Full_Run(void);
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Bits CPU_Core_Dyn_X86_Run(void);
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Bits CPU_Core_Dyn_X86_Trap_Run(void);
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Bits CPU_Core_Dynrec_Run(void);
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Bits CPU_Core_Dynrec_Trap_Run(void);
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Bits CPU_Core_Prefetch_Run(void);
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Bits CPU_Core_Prefetch_Trap_Run(void);
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void CPU_Enable_SkipAutoAdjust(void);
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void CPU_Disable_SkipAutoAdjust(void);
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void CPU_Reset_AutoAdjust(void);
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//CPU Stuff
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extern Bit16u parity_lookup[256];
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bool CPU_LLDT(Bitu selector);
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bool CPU_LTR(Bitu selector);
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void CPU_LIDT(Bitu limit,Bitu base);
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void CPU_LGDT(Bitu limit,Bitu base);
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Bitu CPU_STR(void);
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Bitu CPU_SLDT(void);
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Bitu CPU_SIDT_base(void);
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Bitu CPU_SIDT_limit(void);
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Bitu CPU_SGDT_base(void);
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Bitu CPU_SGDT_limit(void);
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void CPU_ARPL(Bitu & dest_sel,Bitu src_sel);
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void CPU_LAR(Bitu selector,Bitu & ar);
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void CPU_LSL(Bitu selector,Bitu & limit);
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void CPU_SET_CRX(Bitu cr,Bitu value);
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bool CPU_WRITE_CRX(Bitu cr,Bitu value);
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Bitu CPU_GET_CRX(Bitu cr);
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bool CPU_READ_CRX(Bitu cr,Bit32u & retvalue);
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bool CPU_WRITE_DRX(Bitu dr,Bitu value);
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bool CPU_READ_DRX(Bitu dr,Bit32u & retvalue);
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bool CPU_WRITE_TRX(Bitu dr,Bitu value);
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bool CPU_READ_TRX(Bitu dr,Bit32u & retvalue);
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Bitu CPU_SMSW(void);
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bool CPU_LMSW(Bitu word);
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void CPU_VERR(Bitu selector);
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void CPU_VERW(Bitu selector);
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void CPU_JMP(bool use32,Bitu selector,Bitu offset,Bitu oldeip);
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void CPU_CALL(bool use32,Bitu selector,Bitu offset,Bitu oldeip);
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void CPU_RET(bool use32,Bitu bytes,Bitu oldeip);
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void CPU_IRET(bool use32,Bitu oldeip);
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void CPU_HLT(Bitu oldeip);
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bool CPU_POPF(Bitu use32);
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bool CPU_PUSHF(Bitu use32);
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bool CPU_CLI(void);
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bool CPU_STI(void);
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bool CPU_IO_Exception(Bitu port,Bitu size);
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void CPU_RunException(void);
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void CPU_ENTER(bool use32,Bitu bytes,Bitu level);
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#define CPU_INT_SOFTWARE 0x1
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#define CPU_INT_EXCEPTION 0x2
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#define CPU_INT_HAS_ERROR 0x4
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#define CPU_INT_NOIOPLCHECK 0x8
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void CPU_Interrupt(Bitu num,Bitu type,Bitu oldeip);
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static INLINE void CPU_HW_Interrupt(Bitu num) {
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CPU_Interrupt(num,0,reg_eip);
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}
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static INLINE void CPU_SW_Interrupt(Bitu num,Bitu oldeip) {
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CPU_Interrupt(num,CPU_INT_SOFTWARE,oldeip);
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}
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static INLINE void CPU_SW_Interrupt_NoIOPLCheck(Bitu num,Bitu oldeip) {
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CPU_Interrupt(num,CPU_INT_SOFTWARE|CPU_INT_NOIOPLCHECK,oldeip);
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}
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bool CPU_PrepareException(Bitu which,Bitu error);
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void CPU_Exception(Bitu which,Bitu error=0);
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bool CPU_SetSegGeneral(SegNames seg,Bitu value);
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bool CPU_PopSeg(SegNames seg,bool use32);
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bool CPU_CPUID(void);
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Bitu CPU_Pop16(void);
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Bitu CPU_Pop32(void);
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void CPU_Push16(Bitu value);
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void CPU_Push32(Bitu value);
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void CPU_SetFlags(Bitu word,Bitu mask);
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#define EXCEPTION_UD 6
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#define EXCEPTION_TS 10
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#define EXCEPTION_NP 11
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#define EXCEPTION_SS 12
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#define EXCEPTION_GP 13
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#define EXCEPTION_PF 14
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#define CR0_PROTECTION 0x00000001
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#define CR0_MONITORPROCESSOR 0x00000002
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#define CR0_FPUEMULATION 0x00000004
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#define CR0_TASKSWITCH 0x00000008
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#define CR0_FPUPRESENT 0x00000010
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#define CR0_PAGING 0x80000000
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// *********************************************************************
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// Descriptor
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// *********************************************************************
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#define DESC_INVALID 0x00
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#define DESC_286_TSS_A 0x01
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#define DESC_LDT 0x02
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#define DESC_286_TSS_B 0x03
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#define DESC_286_CALL_GATE 0x04
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#define DESC_TASK_GATE 0x05
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#define DESC_286_INT_GATE 0x06
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#define DESC_286_TRAP_GATE 0x07
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#define DESC_386_TSS_A 0x09
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#define DESC_386_TSS_B 0x0b
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#define DESC_386_CALL_GATE 0x0c
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#define DESC_386_INT_GATE 0x0e
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#define DESC_386_TRAP_GATE 0x0f
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/* EU/ED Expand UP/DOWN RO/RW Read Only/Read Write NA/A Accessed */
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#define DESC_DATA_EU_RO_NA 0x10
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#define DESC_DATA_EU_RO_A 0x11
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#define DESC_DATA_EU_RW_NA 0x12
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#define DESC_DATA_EU_RW_A 0x13
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#define DESC_DATA_ED_RO_NA 0x14
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#define DESC_DATA_ED_RO_A 0x15
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#define DESC_DATA_ED_RW_NA 0x16
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#define DESC_DATA_ED_RW_A 0x17
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/* N/R Readable NC/C Confirming A/NA Accessed */
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#define DESC_CODE_N_NC_A 0x18
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#define DESC_CODE_N_NC_NA 0x19
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#define DESC_CODE_R_NC_A 0x1a
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#define DESC_CODE_R_NC_NA 0x1b
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#define DESC_CODE_N_C_A 0x1c
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#define DESC_CODE_N_C_NA 0x1d
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#define DESC_CODE_R_C_A 0x1e
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#define DESC_CODE_R_C_NA 0x1f
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#ifdef _MSC_VER
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#pragma pack (1)
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#endif
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struct S_Descriptor {
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#ifdef WORDS_BIGENDIAN
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Bit32u base_0_15 :16;
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Bit32u limit_0_15 :16;
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Bit32u base_24_31 :8;
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Bit32u g :1;
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Bit32u big :1;
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Bit32u r :1;
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Bit32u avl :1;
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Bit32u limit_16_19 :4;
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Bit32u p :1;
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Bit32u dpl :2;
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Bit32u type :5;
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Bit32u base_16_23 :8;
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#else
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Bit32u limit_0_15 :16;
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Bit32u base_0_15 :16;
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Bit32u base_16_23 :8;
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Bit32u type :5;
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Bit32u dpl :2;
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Bit32u p :1;
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Bit32u limit_16_19 :4;
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Bit32u avl :1;
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Bit32u r :1;
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Bit32u big :1;
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Bit32u g :1;
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Bit32u base_24_31 :8;
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#endif
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}GCC_ATTRIBUTE(packed);
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struct G_Descriptor {
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#ifdef WORDS_BIGENDIAN
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Bit32u selector: 16;
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Bit32u offset_0_15 :16;
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Bit32u offset_16_31 :16;
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Bit32u p :1;
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Bit32u dpl :2;
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Bit32u type :5;
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Bit32u reserved :3;
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Bit32u paramcount :5;
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#else
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Bit32u offset_0_15 :16;
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Bit32u selector :16;
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Bit32u paramcount :5;
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Bit32u reserved :3;
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Bit32u type :5;
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Bit32u dpl :2;
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Bit32u p :1;
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Bit32u offset_16_31 :16;
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#endif
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} GCC_ATTRIBUTE(packed);
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struct TSS_16 {
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Bit16u back; /* Back link to other task */
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Bit16u sp0; /* The CK stack pointer */
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Bit16u ss0; /* The CK stack selector */
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Bit16u sp1; /* The parent KL stack pointer */
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Bit16u ss1; /* The parent KL stack selector */
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Bit16u sp2; /* Unused */
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Bit16u ss2; /* Unused */
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Bit16u ip; /* The instruction pointer */
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Bit16u flags; /* The flags */
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Bit16u ax, cx, dx, bx; /* The general purpose registers */
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Bit16u sp, bp, si, di; /* The special purpose registers */
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Bit16u es; /* The extra selector */
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Bit16u cs; /* The code selector */
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Bit16u ss; /* The application stack selector */
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Bit16u ds; /* The data selector */
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Bit16u ldt; /* The local descriptor table */
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} GCC_ATTRIBUTE(packed);
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struct TSS_32 {
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Bit32u back; /* Back link to other task */
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Bit32u esp0; /* The CK stack pointer */
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Bit32u ss0; /* The CK stack selector */
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Bit32u esp1; /* The parent KL stack pointer */
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Bit32u ss1; /* The parent KL stack selector */
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Bit32u esp2; /* Unused */
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Bit32u ss2; /* Unused */
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Bit32u cr3; /* The page directory pointer */
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Bit32u eip; /* The instruction pointer */
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Bit32u eflags; /* The flags */
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Bit32u eax, ecx, edx, ebx; /* The general purpose registers */
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Bit32u esp, ebp, esi, edi; /* The special purpose registers */
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Bit32u es; /* The extra selector */
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Bit32u cs; /* The code selector */
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Bit32u ss; /* The application stack selector */
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Bit32u ds; /* The data selector */
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Bit32u fs; /* And another extra selector */
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Bit32u gs; /* ... and another one */
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Bit32u ldt; /* The local descriptor table */
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} GCC_ATTRIBUTE(packed);
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#ifdef _MSC_VER
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#pragma pack()
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#endif
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class Descriptor
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{
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public:
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Descriptor() { saved.fill[0]=saved.fill[1]=0; }
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void Load(PhysPt address);
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void Save(PhysPt address);
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PhysPt GetBase (void) {
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return (saved.seg.base_24_31<<24) | (saved.seg.base_16_23<<16) | saved.seg.base_0_15;
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}
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Bitu GetLimit (void) {
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Bitu limit = (saved.seg.limit_16_19<<16) | saved.seg.limit_0_15;
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if (saved.seg.g) return (limit<<12) | 0xFFF;
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return limit;
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}
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Bitu GetOffset(void) {
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return (saved.gate.offset_16_31 << 16) | saved.gate.offset_0_15;
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}
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Bitu GetSelector(void) {
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return saved.gate.selector;
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}
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Bitu Type(void) {
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return saved.seg.type;
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}
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Bitu Conforming(void) {
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return saved.seg.type & 8;
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}
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Bitu DPL(void) {
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return saved.seg.dpl;
|
|
|
|
}
|
|
|
|
Bitu Big(void) {
|
|
|
|
return saved.seg.big;
|
|
|
|
}
|
|
|
|
public:
|
|
|
|
union {
|
|
|
|
S_Descriptor seg;
|
|
|
|
G_Descriptor gate;
|
|
|
|
Bit32u fill[2];
|
|
|
|
} saved;
|
|
|
|
};
|
|
|
|
|
|
|
|
class DescriptorTable {
|
|
|
|
public:
|
|
|
|
PhysPt GetBase (void) { return table_base; }
|
|
|
|
Bitu GetLimit (void) { return table_limit; }
|
|
|
|
void SetBase (PhysPt _base) { table_base = _base; }
|
|
|
|
void SetLimit (Bitu _limit) { table_limit= _limit; }
|
|
|
|
|
|
|
|
bool GetDescriptor (Bitu selector, Descriptor& desc) {
|
|
|
|
selector&=~7;
|
|
|
|
if (selector>=table_limit) return false;
|
|
|
|
desc.Load(table_base+(selector));
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
protected:
|
|
|
|
PhysPt table_base;
|
|
|
|
Bitu table_limit;
|
|
|
|
};
|
|
|
|
|
|
|
|
class GDTDescriptorTable : public DescriptorTable {
|
|
|
|
public:
|
|
|
|
bool GetDescriptor(Bitu selector, Descriptor& desc) {
|
|
|
|
Bitu address=selector & ~7;
|
|
|
|
if (selector & 4) {
|
|
|
|
if (address>=ldt_limit) return false;
|
|
|
|
desc.Load(ldt_base+address);
|
|
|
|
return true;
|
|
|
|
} else {
|
|
|
|
if (address>=table_limit) return false;
|
|
|
|
desc.Load(table_base+address);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
bool SetDescriptor(Bitu selector, Descriptor& desc) {
|
|
|
|
Bitu address=selector & ~7;
|
|
|
|
if (selector & 4) {
|
|
|
|
if (address>=ldt_limit) return false;
|
|
|
|
desc.Save(ldt_base+address);
|
|
|
|
return true;
|
|
|
|
} else {
|
|
|
|
if (address>=table_limit) return false;
|
|
|
|
desc.Save(table_base+address);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
Bitu SLDT(void) {
|
|
|
|
return ldt_value;
|
|
|
|
}
|
|
|
|
bool LLDT(Bitu value) {
|
|
|
|
if ((value&0xfffc)==0) {
|
|
|
|
ldt_value=0;
|
|
|
|
ldt_base=0;
|
|
|
|
ldt_limit=0;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
Descriptor desc;
|
|
|
|
if (!GetDescriptor(value,desc)) return !CPU_PrepareException(EXCEPTION_GP,value);
|
|
|
|
if (desc.Type()!=DESC_LDT) return !CPU_PrepareException(EXCEPTION_GP,value);
|
|
|
|
if (!desc.saved.seg.p) return !CPU_PrepareException(EXCEPTION_NP,value);
|
|
|
|
ldt_base=desc.GetBase();
|
|
|
|
ldt_limit=desc.GetLimit();
|
|
|
|
ldt_value=value;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
private:
|
|
|
|
PhysPt ldt_base;
|
|
|
|
Bitu ldt_limit;
|
|
|
|
Bitu ldt_value;
|
|
|
|
};
|
|
|
|
|
|
|
|
class TSS_Descriptor : public Descriptor {
|
|
|
|
public:
|
|
|
|
Bitu IsBusy(void) {
|
|
|
|
return saved.seg.type & 2;
|
|
|
|
}
|
|
|
|
Bitu Is386(void) {
|
|
|
|
return saved.seg.type & 8;
|
|
|
|
}
|
|
|
|
void SetBusy(bool busy) {
|
|
|
|
if (busy) saved.seg.type|=2;
|
|
|
|
else saved.seg.type&=~2;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
struct CPUBlock {
|
|
|
|
Bitu cpl; /* Current Privilege */
|
|
|
|
Bitu mpl;
|
|
|
|
Bitu cr0;
|
|
|
|
bool pmode; /* Is Protected mode enabled */
|
|
|
|
GDTDescriptorTable gdt;
|
|
|
|
DescriptorTable idt;
|
|
|
|
struct {
|
|
|
|
Bitu mask,notmask;
|
|
|
|
bool big;
|
|
|
|
} stack;
|
|
|
|
struct {
|
|
|
|
bool big;
|
|
|
|
} code;
|
|
|
|
struct {
|
|
|
|
Bitu cs,eip;
|
|
|
|
CPU_Decoder * old_decoder;
|
|
|
|
} hlt;
|
|
|
|
struct {
|
|
|
|
Bitu which,error;
|
|
|
|
} exception;
|
|
|
|
Bits direction;
|
|
|
|
bool trap_skip;
|
|
|
|
Bit32u drx[8];
|
|
|
|
Bit32u trx[8];
|
|
|
|
};
|
|
|
|
|
|
|
|
extern CPUBlock cpu;
|
|
|
|
|
|
|
|
static INLINE void CPU_SetFlagsd(Bitu word) {
|
|
|
|
Bitu mask=cpu.cpl ? FMASK_NORMAL : FMASK_ALL;
|
|
|
|
CPU_SetFlags(word,mask);
|
|
|
|
}
|
|
|
|
|
|
|
|
static INLINE void CPU_SetFlagsw(Bitu word) {
|
|
|
|
Bitu mask=(cpu.cpl ? FMASK_NORMAL : FMASK_ALL) & 0xffff;
|
|
|
|
CPU_SetFlags(word,mask);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#endif
|