From 9e0f047d1b153dca914a81589f6ec43fd9bc8455 Mon Sep 17 00:00:00 2001 From: dborth Date: Tue, 19 May 2009 08:05:51 +0000 Subject: [PATCH] sync to dosbox svn --- src/cpu/core_dynrec/risc_armv4le-common.h | 18 +- src/cpu/core_dynrec/risc_armv4le-o3.h | 495 +++++++----- src/cpu/core_dynrec/risc_armv4le-s3.h | 462 ++++++----- src/cpu/core_dynrec/risc_armv4le-thumb-iw.h | 805 +++++++++++-------- src/cpu/core_dynrec/risc_armv4le-thumb-niw.h | 791 ++++++++++-------- src/cpu/core_dynrec/risc_armv4le-thumb.h | 801 ++++++++++-------- src/debug/debug_win32.cpp | 6 +- 7 files changed, 1927 insertions(+), 1451 deletions(-) diff --git a/src/cpu/core_dynrec/risc_armv4le-common.h b/src/cpu/core_dynrec/risc_armv4le-common.h index e0efa6a..fea54bc 100644 --- a/src/cpu/core_dynrec/risc_armv4le-common.h +++ b/src/cpu/core_dynrec/risc_armv4le-common.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2002-2008 The DOSBox Team + * Copyright (C) 2002-2009 The DOSBox Team * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,7 +16,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $Id: risc_armv4le-common.h,v 1.2 2008/09/19 16:48:02 c2woody Exp $ */ +/* $Id: risc_armv4le-common.h,v 1.3 2009/05/16 21:52:47 c2woody Exp $ */ /* ARMv4 (little endian) backend by M-HT (common data/functions) */ @@ -89,8 +89,19 @@ typedef Bit8u HostReg; static void cache_block_closing(Bit8u* block_start,Bitu block_size) { +#if (__ARM_EABI__) + //flush cache - eabi + register unsigned long _beg __asm ("a1") = (unsigned long)(block_start); // block start + register unsigned long _end __asm ("a2") = (unsigned long)(block_start+block_size); // block end + register unsigned long _flg __asm ("a3") = 0; + register unsigned long _par __asm ("r7") = 0xf0002; // sys_cacheflush + __asm __volatile ("swi 0x0" + : // no outputs + : "r" (_beg), "r" (_end), "r" (_flg), "r" (_par) + ); +#else // GP2X BEGIN - //flush cache + //flush cache - old abi register unsigned long _beg __asm ("a1") = (unsigned long)(block_start); // block start register unsigned long _end __asm ("a2") = (unsigned long)(block_start+block_size); // block end register unsigned long _flg __asm ("a3") = 0; @@ -99,4 +110,5 @@ static void cache_block_closing(Bit8u* block_start,Bitu block_size) { : "r" (_beg), "r" (_end), "r" (_flg) ); // GP2X END +#endif } diff --git a/src/cpu/core_dynrec/risc_armv4le-o3.h b/src/cpu/core_dynrec/risc_armv4le-o3.h index 8c0c37c..288a74a 100644 --- a/src/cpu/core_dynrec/risc_armv4le-o3.h +++ b/src/cpu/core_dynrec/risc_armv4le-o3.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2002-2008 The DOSBox Team + * Copyright (C) 2002-2009 The DOSBox Team * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,7 +16,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $Id: risc_armv4le-o3.h,v 1.3 2008/09/19 16:48:02 c2woody Exp $ */ +/* $Id: risc_armv4le-o3.h,v 1.4 2009/05/16 21:52:47 c2woody Exp $ */ /* ARMv4 (little endian) backend by M-HT (size-tweaked arm version) */ @@ -58,13 +58,102 @@ #define FC_SEGS_ADDR HOST_v8 #endif + // helper macro #define ROTATE_SCALE(x) ( (x)?(32 - x):(0) ) + +// instruction encodings + +// move +// mov dst, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define MOV_IMM(dst, imm, rimm) (0xe3a00000 + ((dst) << 12) + (imm) + ((rimm) << 7) ) +// mov dst, src, lsl #imm +#define MOV_REG_LSL_IMM(dst, src, imm) (0xe1a00000 + ((dst) << 12) + (src) + ((imm) << 7) ) +// movs dst, src, lsl #imm +#define MOVS_REG_LSL_IMM(dst, src, imm) (0xe1b00000 + ((dst) << 12) + (src) + ((imm) << 7) ) +// mov dst, src, lsr #imm +#define MOV_REG_LSR_IMM(dst, src, imm) (0xe1a00020 + ((dst) << 12) + (src) + ((imm) << 7) ) +// mov dst, src, asr #imm +#define MOV_REG_ASR_IMM(dst, src, imm) (0xe1a00040 + ((dst) << 12) + (src) + ((imm) << 7) ) +// mov dst, src, lsl rreg +#define MOV_REG_LSL_REG(dst, src, rreg) (0xe1a00010 + ((dst) << 12) + (src) + ((rreg) << 8) ) +// mov dst, src, lsr rreg +#define MOV_REG_LSR_REG(dst, src, rreg) (0xe1a00030 + ((dst) << 12) + (src) + ((rreg) << 8) ) +// mov dst, src, asr rreg +#define MOV_REG_ASR_REG(dst, src, rreg) (0xe1a00050 + ((dst) << 12) + (src) + ((rreg) << 8) ) +// mov dst, src, ror rreg +#define MOV_REG_ROR_REG(dst, src, rreg) (0xe1a00070 + ((dst) << 12) + (src) + ((rreg) << 8) ) +// mvn dst, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define MVN_IMM(dst, imm, rimm) (0xe3e00000 + ((dst) << 12) + (imm) + ((rimm) << 7) ) + +// arithmetic +// add dst, src, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define ADD_IMM(dst, src, imm, rimm) (0xe2800000 + ((dst) << 12) + ((src) << 16) + (imm) + ((rimm) << 7) ) +// add dst, src1, src2, lsl #imm +#define ADD_REG_LSL_IMM(dst, src1, src2, imm) (0xe0800000 + ((dst) << 12) + ((src1) << 16) + (src2) + ((imm) << 7) ) +// sub dst, src, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define SUB_IMM(dst, src, imm, rimm) (0xe2400000 + ((dst) << 12) + ((src) << 16) + (imm) + ((rimm) << 7) ) +// sub dst, src1, src2, lsl #imm +#define SUB_REG_LSL_IMM(dst, src1, src2, imm) (0xe0400000 + ((dst) << 12) + ((src1) << 16) + (src2) + ((imm) << 7) ) +// rsb dst, src, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define RSB_IMM(dst, src, imm, rimm) (0xe2600000 + ((dst) << 12) + ((src) << 16) + (imm) + ((rimm) << 7) ) +// cmp src, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define CMP_IMM(src, imm, rimm) (0xe3500000 + ((src) << 16) + (imm) + ((rimm) << 7) ) +// nop +#define NOP MOV_REG_LSL_IMM(HOST_r0, HOST_r0, 0) + +// logical +// tst src, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define TST_IMM(src, imm, rimm) (0xe3100000 + ((src) << 16) + (imm) + ((rimm) << 7) ) +// and dst, src, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define AND_IMM(dst, src, imm, rimm) (0xe2000000 + ((dst) << 12) + ((src) << 16) + (imm) + ((rimm) << 7) ) +// and dst, src1, src2, lsl #imm +#define AND_REG_LSL_IMM(dst, src1, src2, imm) (0xe0000000 + ((dst) << 12) + ((src1) << 16) + (src2) + ((imm) << 7) ) +// orr dst, src, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define ORR_IMM(dst, src, imm, rimm) (0xe3800000 + ((dst) << 12) + ((src) << 16) + (imm) + ((rimm) << 7) ) +// orr dst, src1, src2, lsl #imm +#define ORR_REG_LSL_IMM(dst, src1, src2, imm) (0xe1800000 + ((dst) << 12) + ((src1) << 16) + (src2) + ((imm) << 7) ) +// orr dst, src1, src2, lsr #imm +#define ORR_REG_LSR_IMM(dst, src1, src2, imm) (0xe1800020 + ((dst) << 12) + ((src1) << 16) + (src2) + ((imm) << 7) ) +// eor dst, src1, src2, lsl #imm +#define EOR_REG_LSL_IMM(dst, src1, src2, imm) (0xe0200000 + ((dst) << 12) + ((src1) << 16) + (src2) + ((imm) << 7) ) +// bic dst, src, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define BIC_IMM(dst, src, imm, rimm) (0xe3c00000 + ((dst) << 12) + ((src) << 16) + (imm) + ((rimm) << 7) ) + +// load +// ldr reg, [addr, #imm] @ 0 <= imm < 4096 +#define LDR_IMM(reg, addr, imm) (0xe5900000 + ((reg) << 12) + ((addr) << 16) + (imm) ) +// ldrh reg, [addr, #imm] @ 0 <= imm < 256 +#define LDRH_IMM(reg, addr, imm) (0xe1d000b0 + ((reg) << 12) + ((addr) << 16) + (((imm) & 0xf0) << 4) + ((imm) & 0x0f) ) +// ldrb reg, [addr, #imm] @ 0 <= imm < 4096 +#define LDRB_IMM(reg, addr, imm) (0xe5d00000 + ((reg) << 12) + ((addr) << 16) + (imm) ) + +// store +// str reg, [addr, #imm] @ 0 <= imm < 4096 +#define STR_IMM(reg, addr, imm) (0xe5800000 + ((reg) << 12) + ((addr) << 16) + (imm) ) +// strh reg, [addr, #imm] @ 0 <= imm < 256 +#define STRH_IMM(reg, addr, imm) (0xe1c000b0 + ((reg) << 12) + ((addr) << 16) + (((imm) & 0xf0) << 4) + ((imm) & 0x0f) ) +// strb reg, [addr, #imm] @ 0 <= imm < 4096 +#define STRB_IMM(reg, addr, imm) (0xe5c00000 + ((reg) << 12) + ((addr) << 16) + (imm) ) + +// branch +// beq pc+imm @ 0 <= imm < 32M & imm mod 4 = 0 +#define BEQ_FWD(imm) (0x0a000000 + ((imm) >> 2) ) +// bne pc+imm @ 0 <= imm < 32M & imm mod 4 = 0 +#define BNE_FWD(imm) (0x1a000000 + ((imm) >> 2) ) +// bgt pc+imm @ 0 <= imm < 32M & imm mod 4 = 0 +#define BGT_FWD(imm) (0xca000000 + ((imm) >> 2) ) +// b pc+imm @ 0 <= imm < 32M & imm mod 4 = 0 +#define B_FWD(imm) (0xea000000 + ((imm) >> 2) ) +// bx reg +#define BX(reg) (0xe12fff10 + (reg) ) + + // move a full register from reg_src to reg_dst static void gen_mov_regs(HostReg reg_dst,HostReg reg_src) { if(reg_src == reg_dst) return; - cache_addd(0xe1a00000 + (reg_dst << 12) + reg_src); // mov reg_dst, reg_src + cache_addd( MOV_REG_LSL_IMM(reg_dst, reg_src, 0) ); // mov reg_dst, reg_src } // helper function @@ -114,9 +203,9 @@ static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) { Bits first, method, scale; Bit32u imm2, dist; if (imm == 0) { - cache_addd(0xe3a00000 + (dest_reg << 12)); // mov dest_reg, #0 + cache_addd( MOV_IMM(dest_reg, 0, 0) ); // mov dest_reg, #0 } else if (imm == 0xffffffff) { - cache_addd(0xe3e00000 + (dest_reg << 12)); // mvn dest_reg, #0 + cache_addd( MVN_IMM(dest_reg, 0, 0) ); // mvn dest_reg, #0 } else { method = get_method_imm_gen_len(imm, 1, NULL); @@ -130,10 +219,10 @@ static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) { scale+=2; } if (first) { - cache_addd(0xe2400000 + (dest_reg << 12) + (HOST_pc << 16) + (ROTATE_SCALE(scale) << 7) + (dist & 0xff)); // sub dest_reg, pc, #((dist & 0xff) << scale) + cache_addd( SUB_IMM(dest_reg, HOST_pc, dist & 0xff, ROTATE_SCALE(scale)) ); // sub dest_reg, pc, #((dist & 0xff) << scale) first = 0; } else { - cache_addd(0xe2400000 + (dest_reg << 12) + (dest_reg << 16) + (ROTATE_SCALE(scale) << 7) + (dist & 0xff)); // sub dest_reg, dest_reg, #((dist & 0xff) << scale) + cache_addd( SUB_IMM(dest_reg, dest_reg, dist & 0xff, ROTATE_SCALE(scale)) ); // sub dest_reg, dest_reg, #((dist & 0xff) << scale) } dist>>=8; scale+=8; @@ -141,7 +230,7 @@ static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) { } else if (method == 1) { dist = imm - ((Bit32u)cache.pos+8); if (dist == 0) { - cache_addd(0xe1a00000 + (dest_reg << 12) + HOST_pc); // mov dest_reg, pc + cache_addd( MOV_REG_LSL_IMM(dest_reg, HOST_pc, 0) ); // mov dest_reg, pc } else { while (dist) { while ((dist & 3) == 0) { @@ -149,10 +238,10 @@ static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) { scale+=2; } if (first) { - cache_addd(0xe2800000 + (dest_reg << 12) + (HOST_pc << 16) + (ROTATE_SCALE(scale) << 7) + (dist & 0xff)); // add dest_reg, pc, #((dist & 0xff) << scale) + cache_addd( ADD_IMM(dest_reg, HOST_pc, dist & 0xff, ROTATE_SCALE(scale)) ); // add dest_reg, pc, #((dist & 0xff) << scale) first = 0; } else { - cache_addd(0xe2800000 + (dest_reg << 12) + (dest_reg << 16) + (ROTATE_SCALE(scale) << 7) + (dist & 0xff)); // add dest_reg, dest_reg, #((dist & 0xff) << scale) + cache_addd( ADD_IMM(dest_reg, dest_reg, dist & 0xff, ROTATE_SCALE(scale)) ); // add dest_reg, dest_reg, #((dist & 0xff) << scale) } dist>>=8; scale+=8; @@ -165,10 +254,10 @@ static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) { scale+=2; } if (first) { - cache_addd(0xe3a00000 + (dest_reg << 12) + (ROTATE_SCALE(scale) << 7) + (imm & 0xff)); // mov dest_reg, #((imm & 0xff) << scale) + cache_addd( MOV_IMM(dest_reg, imm & 0xff, ROTATE_SCALE(scale)) ); // mov dest_reg, #((imm & 0xff) << scale) first = 0; } else { - cache_addd(0xe3800000 + (dest_reg << 12) + (dest_reg << 16) + (ROTATE_SCALE(scale) << 7) + (imm & 0xff)); // orr dest_reg, dest_reg, #((imm & 0xff) << scale) + cache_addd( ORR_IMM(dest_reg, dest_reg, imm & 0xff, ROTATE_SCALE(scale)) ); // orr dest_reg, dest_reg, #((imm & 0xff) << scale) } imm>>=8; scale+=8; @@ -181,10 +270,10 @@ static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) { scale+=2; } if (first) { - cache_addd(0xe3e00000 + (dest_reg << 12) + (ROTATE_SCALE(scale) << 7) + (imm2 & 0xff)); // mvn dest_reg, #((imm2 & 0xff) << scale) + cache_addd( MVN_IMM(dest_reg, imm2 & 0xff, ROTATE_SCALE(scale)) ); // mvn dest_reg, #((imm2 & 0xff) << scale) first = 0; } else { - cache_addd(0xe3c00000 + (dest_reg << 12) + (dest_reg << 16) + (ROTATE_SCALE(scale) << 7) + (imm2 & 0xff)); // bic dest_reg, dest_reg, #((imm2 & 0xff) << scale) + cache_addd( BIC_IMM(dest_reg, dest_reg, imm2 & 0xff, ROTATE_SCALE(scale)) ); // bic dest_reg, dest_reg, #((imm2 & 0xff) << scale) } imm2>>=8; scale+=8; @@ -199,26 +288,26 @@ static void gen_mov_word_to_reg_helper(HostReg dest_reg,void* data,bool dword,Ho if (dword) { if ((Bit32u)data & 3) { if ( ((Bit32u)data & 3) == 2 ) { - cache_addd(0xe1d000b0 + (dest_reg << 12) + (data_reg << 16)); // ldrh dest_reg, [data_reg] - cache_addd(0xe1d000b2 + (temp2 << 12) + (data_reg << 16)); // ldrh temp2, [data_reg, #2] - cache_addd(0xe1800800 + (dest_reg << 12) + (dest_reg << 16) + (temp2)); // orr dest_reg, dest_reg, temp2, lsl #16 + cache_addd( LDRH_IMM(dest_reg, data_reg, 0) ); // ldrh dest_reg, [data_reg] + cache_addd( LDRH_IMM(temp2, data_reg, 2) ); // ldrh temp2, [data_reg, #2] + cache_addd( ORR_REG_LSL_IMM(dest_reg, dest_reg, temp2, 16) ); // orr dest_reg, dest_reg, temp2, lsl #16 } else { - cache_addd(0xe5d00000 + (dest_reg << 12) + (data_reg << 16)); // ldrb dest_reg, [data_reg] - cache_addd(0xe1d000b1 + (temp2 << 12) + (data_reg << 16)); // ldrh temp2, [data_reg, #1] - cache_addd(0xe1800400 + (dest_reg << 12) + (dest_reg << 16) + (temp2)); // orr dest_reg, dest_reg, temp2, lsl #8 - cache_addd(0xe5d00003 + (temp2 << 12) + (data_reg << 16)); // ldrb temp2, [data_reg, #3] - cache_addd(0xe1800c00 + (dest_reg << 12) + (dest_reg << 16) + (temp2)); // orr dest_reg, dest_reg, temp2, lsl #24 + cache_addd( LDRB_IMM(dest_reg, data_reg, 0) ); // ldrb dest_reg, [data_reg] + cache_addd( LDRH_IMM(temp2, data_reg, 1) ); // ldrh temp2, [data_reg, #1] + cache_addd( ORR_REG_LSL_IMM(dest_reg, dest_reg, temp2, 8) ); // orr dest_reg, dest_reg, temp2, lsl #8 + cache_addd( LDRB_IMM(temp2, data_reg, 3) ); // ldrb temp2, [data_reg, #3] + cache_addd( ORR_REG_LSL_IMM(dest_reg, dest_reg, temp2, 24) ); // orr dest_reg, dest_reg, temp2, lsl #24 } } else { - cache_addd(0xe5900000 + (dest_reg << 12) + (data_reg << 16)); // ldr dest_reg, [data_reg] + cache_addd( LDR_IMM(dest_reg, data_reg, 0) ); // ldr dest_reg, [data_reg] } } else { if ((Bit32u)data & 1) { - cache_addd(0xe5d00000 + (dest_reg << 12) + (data_reg << 16)); // ldrb dest_reg, [data_reg] - cache_addd(0xe5d00001 + (temp2 << 12) + (data_reg << 16)); // ldrb temp2, [data_reg, #1] - cache_addd(0xe1800400 + (dest_reg << 12) + (dest_reg << 16) + (temp2)); // orr dest_reg, dest_reg, temp2, lsl #8 + cache_addd( LDRB_IMM(dest_reg, data_reg, 0) ); // ldrb dest_reg, [data_reg] + cache_addd( LDRB_IMM(temp2, data_reg, 1) ); // ldrb temp2, [data_reg, #1] + cache_addd( ORR_REG_LSL_IMM(dest_reg, dest_reg, temp2, 8) ); // orr dest_reg, dest_reg, temp2, lsl #8 } else { - cache_addd(0xe1d000b0 + (dest_reg << 12) + (data_reg << 16)); // ldrh dest_reg, [data_reg] + cache_addd( LDRH_IMM(dest_reg, data_reg, 0) ); // ldrh dest_reg, [data_reg] } } } @@ -236,7 +325,7 @@ static void gen_mov_word_to_reg_imm(HostReg dest_reg,Bit16u imm) { Bits first, scale; Bit32u imm2; if (imm == 0) { - cache_addd(0xe3a00000 + (dest_reg << 12)); // mov dest_reg, #0 + cache_addd( MOV_IMM(dest_reg, 0, 0) ); // mov dest_reg, #0 } else { scale = 0; first = 1; @@ -247,10 +336,10 @@ static void gen_mov_word_to_reg_imm(HostReg dest_reg,Bit16u imm) { scale+=2; } if (first) { - cache_addd(0xe3a00000 + (dest_reg << 12) + (ROTATE_SCALE(scale) << 7) + (imm2 & 0xff)); // mov dest_reg, #((imm2 & 0xff) << scale) + cache_addd( MOV_IMM(dest_reg, imm2 & 0xff, ROTATE_SCALE(scale)) ); // mov dest_reg, #((imm2 & 0xff) << scale) first = 0; } else { - cache_addd(0xe3800000 + (dest_reg << 12) + (dest_reg << 16) + (ROTATE_SCALE(scale) << 7) + (imm2 & 0xff)); // orr dest_reg, dest_reg, #((imm2 & 0xff) << scale) + cache_addd( ORR_IMM(dest_reg, dest_reg, imm2 & 0xff, ROTATE_SCALE(scale)) ); // orr dest_reg, dest_reg, #((imm2 & 0xff) << scale) } imm2>>=8; scale+=8; @@ -264,26 +353,26 @@ static void gen_mov_word_from_reg_helper(HostReg src_reg,void* dest,bool dword, if (dword) { if ((Bit32u)dest & 3) { if ( ((Bit32u)dest & 3) == 2 ) { - cache_addd(0xe1c000b0 + (src_reg << 12) + (data_reg << 16)); // strh src_reg, [data_reg] - cache_addd(0xe1a00820 + (temp2 << 12) + (src_reg)); // mov temp2, src_reg, lsr #16 - cache_addd(0xe1c000b2 + (temp2 << 12) + (data_reg << 16)); // strh temp2, [data_reg, #2] + cache_addd( STRH_IMM(src_reg, data_reg, 0) ); // strh src_reg, [data_reg] + cache_addd( MOV_REG_LSR_IMM(temp2, src_reg, 16) ); // mov temp2, src_reg, lsr #16 + cache_addd( STRH_IMM(temp2, data_reg, 2) ); // strh temp2, [data_reg, #2] } else { - cache_addd(0xe5c00000 + (src_reg << 12) + (data_reg << 16)); // strb src_reg, [data_reg] - cache_addd(0xe1a00420 + (temp2 << 12) + (src_reg)); // mov temp2, src_reg, lsr #8 - cache_addd(0xe1c000b1 + (temp2 << 12) + (data_reg << 16)); // strh temp2, [data_reg, #1] - cache_addd(0xe1a00820 + (temp2 << 12) + (temp2)); // mov temp2, temp2, lsr #16 - cache_addd(0xe5c00003 + (temp2 << 12) + (data_reg << 16)); // strb temp2, [data_reg, #3] + cache_addd( STRB_IMM(src_reg, data_reg, 0) ); // strb src_reg, [data_reg] + cache_addd( MOV_REG_LSR_IMM(temp2, src_reg, 8) ); // mov temp2, src_reg, lsr #8 + cache_addd( STRH_IMM(temp2, data_reg, 1) ); // strh temp2, [data_reg, #1] + cache_addd( MOV_REG_LSR_IMM(temp2, temp2, 16) ); // mov temp2, temp2, lsr #16 + cache_addd( STRB_IMM(temp2, data_reg, 3) ); // strb temp2, [data_reg, #3] } } else { - cache_addd(0xe5800000 + (src_reg << 12) + (data_reg << 16)); // str src_reg, [data_reg] + cache_addd( STR_IMM(src_reg, data_reg, 0) ); // str src_reg, [data_reg] } } else { if ((Bit32u)dest & 1) { - cache_addd(0xe5c00000 + (src_reg << 12) + (data_reg << 16)); // strb src_reg, [data_reg] - cache_addd(0xe1a00420 + (temp2 << 12) + (src_reg)); // mov temp2, src_reg, lsr #8 - cache_addd(0xe5c00001 + (temp2 << 12) + (data_reg << 16)); // strb temp2, [data_reg, #1] + cache_addd( STRB_IMM(src_reg, data_reg, 0) ); // strb src_reg, [data_reg] + cache_addd( MOV_REG_LSR_IMM(temp2, src_reg, 8) ); // mov temp2, src_reg, lsr #8 + cache_addd( STRB_IMM(temp2, data_reg, 1) ); // strb temp2, [data_reg, #1] } else { - cache_addd(0xe1c000b0 + (src_reg << 12) + (data_reg << 16)); // strh src_reg, [data_reg] + cache_addd( STRH_IMM(src_reg, data_reg, 0) ); // strh src_reg, [data_reg] } } } @@ -300,7 +389,7 @@ static void gen_mov_word_from_reg(HostReg src_reg,void* dest,bool dword) { // registers might not be directly byte-accessible on some architectures static void gen_mov_byte_to_reg_low(HostReg dest_reg,void* data) { gen_mov_dword_to_reg_imm(temp1, (Bit32u)data); - cache_addd(0xe5d00000 + (dest_reg << 12) + (temp1 << 16)); // ldrb dest_reg, [temp1] + cache_addd( LDRB_IMM(dest_reg, temp1, 0) ); // ldrb dest_reg, [temp1] } // move an 8bit value from memory into dest_reg @@ -316,7 +405,7 @@ static void INLINE gen_mov_byte_to_reg_low_canuseword(HostReg dest_reg,void* dat // this function does not use FC_OP1/FC_OP2 as dest_reg as these // registers might not be directly byte-accessible on some architectures static void gen_mov_byte_to_reg_low_imm(HostReg dest_reg,Bit8u imm) { - cache_addd(0xe3a00000 + (dest_reg << 12) + (imm)); // mov dest_reg, #(imm) + cache_addd( MOV_IMM(dest_reg, imm, 0) ); // mov dest_reg, #(imm) } // move an 8bit constant value into dest_reg @@ -330,7 +419,7 @@ static void INLINE gen_mov_byte_to_reg_low_imm_canuseword(HostReg dest_reg,Bit8u // move the lowest 8bit of a register into memory static void gen_mov_byte_from_reg_low(HostReg src_reg,void* dest) { gen_mov_dword_to_reg_imm(temp1, (Bit32u)dest); - cache_addd(0xe5c00000 + (src_reg << 12) + (temp1 << 16)); // strb src_reg, [temp1] + cache_addd( STRB_IMM(src_reg, temp1, 0) ); // strb src_reg, [temp1] } @@ -339,10 +428,10 @@ static void gen_mov_byte_from_reg_low(HostReg src_reg,void* dest) { // the register is zero-extended (sign==false) or sign-extended (sign==true) static void gen_extend_byte(bool sign,HostReg reg) { if (sign) { - cache_addd(0xe1a00c00 + (reg << 12) + (reg)); // mov reg, reg, lsl #24 - cache_addd(0xe1a00c40 + (reg << 12) + (reg)); // mov reg, reg, asr #24 + cache_addd( MOV_REG_LSL_IMM(reg, reg, 24) ); // mov reg, reg, lsl #24 + cache_addd( MOV_REG_ASR_IMM(reg, reg, 24) ); // mov reg, reg, asr #24 } else { - cache_addd(0xe20000ff + (reg << 12) + (reg << 16)); // and reg, reg, #0xff + cache_addd( AND_IMM(reg, reg, 0xff, 0) ); // and reg, reg, #0xff } } @@ -350,18 +439,18 @@ static void gen_extend_byte(bool sign,HostReg reg) { // the register is zero-extended (sign==false) or sign-extended (sign==true) static void gen_extend_word(bool sign,HostReg reg) { if (sign) { - cache_addd(0xe1a00800 + (reg << 12) + (reg)); // mov reg, reg, lsl #16 - cache_addd(0xe1a00840 + (reg << 12) + (reg)); // mov reg, reg, asr #16 + cache_addd( MOV_REG_LSL_IMM(reg, reg, 16) ); // mov reg, reg, lsl #16 + cache_addd( MOV_REG_ASR_IMM(reg, reg, 16) ); // mov reg, reg, asr #16 } else { - cache_addd(0xe1a00800 + (reg << 12) + (reg)); // mov reg, reg, lsl #16 - cache_addd(0xe1a00820 + (reg << 12) + (reg)); // mov reg, reg, lsr #16 + cache_addd( MOV_REG_LSL_IMM(reg, reg, 16) ); // mov reg, reg, lsl #16 + cache_addd( MOV_REG_LSR_IMM(reg, reg, 16) ); // mov reg, reg, lsr #16 } } // add a 32bit value from memory to a full register static void gen_add(HostReg reg,void* op) { gen_mov_word_to_reg(temp3, op, 1); - cache_addd(0xe0800000 + (reg << 12) + (reg << 16) + (temp3)); // add reg, reg, temp3 + cache_addd( ADD_REG_LSL_IMM(reg, reg, temp3, 0) ); // add reg, reg, temp3 } // add a 32bit constant value to a full register @@ -369,9 +458,9 @@ static void gen_add_imm(HostReg reg,Bit32u imm) { Bits method1, method2, num1, num2, scale, sub; if(!imm) return; if (imm == 1) { - cache_addd(0xe2800001 + (reg << 12) + (reg << 16)); // add reg, reg, #1 + cache_addd( ADD_IMM(reg, reg, 1, 0) ); // add reg, reg, #1 } else if (imm == 0xffffffff) { - cache_addd(0xe2400001 + (reg << 12) + (reg << 16)); // sub reg, reg, #1 + cache_addd( SUB_IMM(reg, reg, 1, 0) ); // sub reg, reg, #1 } else { method1 = get_method_imm_gen_len(imm, 1, &num1); method2 = get_method_imm_gen_len(-((Bit32s)imm), 1, &num2); @@ -384,9 +473,9 @@ static void gen_add_imm(HostReg reg,Bit32u imm) { if (method1 != 2) { gen_mov_dword_to_reg_imm(temp3, imm); if (sub) { - cache_addd(0xe0400000 + (reg << 12) + (reg << 16) + (temp3)); // sub reg, reg, temp3 + cache_addd( SUB_REG_LSL_IMM(reg, reg, temp3, 0) ); // sub reg, reg, temp3 } else { - cache_addd(0xe0800000 + (reg << 12) + (reg << 16) + (temp3)); // add reg, reg, temp3 + cache_addd( ADD_REG_LSL_IMM(reg, reg, temp3, 0) ); // add reg, reg, temp3 } } else { scale = 0; @@ -396,9 +485,9 @@ static void gen_add_imm(HostReg reg,Bit32u imm) { scale+=2; } if (sub) { - cache_addd(0xe2400000 + (reg << 12) + (reg << 16) + (ROTATE_SCALE(scale) << 7) + (imm & 0xff)); // sub reg, reg, #((imm & 0xff) << scale) + cache_addd( SUB_IMM(reg, reg, imm & 0xff, ROTATE_SCALE(scale)) ); // sub reg, reg, #((imm & 0xff) << scale) } else { - cache_addd(0xe2800000 + (reg << 12) + (reg << 16) + (ROTATE_SCALE(scale) << 7) + (imm & 0xff)); // add reg, reg, #((imm & 0xff) << scale) + cache_addd( ADD_IMM(reg, reg, imm & 0xff, ROTATE_SCALE(scale)) ); // add reg, reg, #((imm & 0xff) << scale) } imm>>=8; scale+=8; @@ -414,12 +503,12 @@ static void gen_and_imm(HostReg reg,Bit32u imm) { imm2 = ~imm; if(!imm2) return; if (!imm) { - cache_addd(0xe3a00000 + (reg << 12)); // mov reg, #0 + cache_addd( MOV_IMM(reg, 0, 0) ); // mov reg, #0 } else { method = get_method_imm_gen_len(imm, 0, NULL); if (method != 3) { gen_mov_dword_to_reg_imm(temp3, imm); - cache_addd(0xe0000000 + (reg << 12) + (reg << 16) + (temp3)); // and reg, reg, temp3 + cache_addd( AND_REG_LSL_IMM(reg, reg, temp3, 0) ); // and reg, reg, temp3 } else { scale = 0; while (imm2) { @@ -427,7 +516,7 @@ static void gen_and_imm(HostReg reg,Bit32u imm) { imm2>>=2; scale+=2; } - cache_addd(0xe3c00000 + (reg << 12) + (reg << 16) + (ROTATE_SCALE(scale) << 7) + (imm2 & 0xff)); // bic reg, reg, #((imm2 & 0xff) << scale) + cache_addd( BIC_IMM(reg, reg, imm2 & 0xff, ROTATE_SCALE(scale)) ); // bic reg, reg, #((imm2 & 0xff) << scale) imm2>>=8; scale+=8; } @@ -453,9 +542,9 @@ static void gen_add_direct_byte(void* dest,Bit8s imm) { gen_mov_dword_to_reg_imm(temp1, (Bit32u)dest); gen_mov_word_to_reg_helper(temp3, dest, 1, temp1); if (imm >= 0) { - cache_addd(0xe2800000 + (temp3 << 12) + (temp3 << 16) + ((Bit32s)imm)); // add temp3, temp3, #(imm) + cache_addd( ADD_IMM(temp3, temp3, (Bit32s)imm, 0) ); // add temp3, temp3, #(imm) } else { - cache_addd(0xe2400000 + (temp3 << 12) + (temp3 << 16) + (-((Bit32s)imm))); // sub temp3, temp3, #(-imm) + cache_addd( SUB_IMM(temp3, temp3, -((Bit32s)imm), 0) ); // sub temp3, temp3, #(-imm) } gen_mov_word_from_reg_helper(temp3, dest, 1, temp1); } @@ -475,7 +564,7 @@ static void gen_add_direct_word(void* dest,Bit32u imm,bool dword) { } else { gen_mov_word_to_reg_imm(temp2, (Bit16u)imm); } - cache_addd(0xe0800000 + (temp3 << 12) + (temp3 << 16) + (temp2)); // add temp3, temp3, temp2 + cache_addd( ADD_REG_LSL_IMM(temp3, temp3, temp2, 0) ); // add temp3, temp3, temp2 gen_mov_word_from_reg_helper(temp3, dest, dword, temp1); } @@ -485,9 +574,9 @@ static void gen_sub_direct_byte(void* dest,Bit8s imm) { gen_mov_dword_to_reg_imm(temp1, (Bit32u)dest); gen_mov_word_to_reg_helper(temp3, dest, 1, temp1); if (imm >= 0) { - cache_addd(0xe2400000 + (temp3 << 12) + (temp3 << 16) + ((Bit32s)imm)); // sub temp3, temp3, #(imm) + cache_addd( SUB_IMM(temp3, temp3, (Bit32s)imm, 0) ); // sub temp3, temp3, #(imm) } else { - cache_addd(0xe2800000 + (temp3 << 12) + (temp3 << 16) + (-((Bit32s)imm))); // add temp3, temp3, #(-imm) + cache_addd( ADD_IMM(temp3, temp3, -((Bit32s)imm), 0) ); // add temp3, temp3, #(-imm) } gen_mov_word_from_reg_helper(temp3, dest, 1, temp1); } @@ -507,7 +596,7 @@ static void gen_sub_direct_word(void* dest,Bit32u imm,bool dword) { } else { gen_mov_word_to_reg_imm(temp2, (Bit16u)imm); } - cache_addd(0xe0400000 + (temp3 << 12) + (temp3 << 16) + (temp2)); // sub temp3, temp3, temp2 + cache_addd( SUB_REG_LSL_IMM(temp3, temp3, temp2, 0) ); // sub temp3, temp3, temp2 gen_mov_word_from_reg_helper(temp3, dest, dword, temp1); } @@ -515,7 +604,7 @@ static void gen_sub_direct_word(void* dest,Bit32u imm,bool dword) { // scale_reg is scaled by scale (scale_reg*(2^scale)) and // added to dest_reg, then the immediate value is added static INLINE void gen_lea(HostReg dest_reg,HostReg scale_reg,Bitu scale,Bits imm) { - cache_addd(0xe0800000 + (dest_reg << 12) + (dest_reg << 16) + (scale_reg) + (scale << 7)); // add dest_reg, dest_reg, scale_reg, lsl #(scale) + cache_addd( ADD_REG_LSL_IMM(dest_reg, dest_reg, scale_reg, scale) ); // add dest_reg, dest_reg, scale_reg, lsl #(scale) gen_add_imm(dest_reg, imm); } @@ -524,18 +613,18 @@ static INLINE void gen_lea(HostReg dest_reg,HostReg scale_reg,Bitu scale,Bits im // then the immediate value is added static INLINE void gen_lea(HostReg dest_reg,Bitu scale,Bits imm) { if (scale) { - cache_addd(0xe1a00000 + (dest_reg << 12) + (dest_reg) + (scale << 7)); // mov dest_reg, dest_reg, lsl #(scale) + cache_addd( MOV_REG_LSL_IMM(dest_reg, dest_reg, scale) ); // mov dest_reg, dest_reg, lsl #(scale) } gen_add_imm(dest_reg, imm); } // generate a call to a parameterless function static void INLINE gen_call_function_raw(void * func) { - cache_addd(0xe5900004 + (temp1 << 12) + (HOST_pc << 16)); // ldr temp1, [pc, #4] - cache_addd(0xe2800004 + (HOST_lr << 12) + (HOST_pc << 16)); // add lr, pc, #4 - cache_addd(0xe12fff10 + (temp1)); // bx temp1 + cache_addd( LDR_IMM(temp1, HOST_pc, 4) ); // ldr temp1, [pc, #4] + cache_addd( ADD_IMM(HOST_lr, HOST_pc, 4, 0) ); // add lr, pc, #4 + cache_addd( BX(temp1) ); // bx temp1 cache_addd((Bit32u)func); // .int func - cache_addd(0xe1a00000 + (FC_RETOP << 12) + HOST_a1); // mov FC_RETOP, a1 + cache_addd( MOV_REG_LSL_IMM(FC_RETOP, HOST_a1, 0) ); // mov FC_RETOP, a1 } // generate a call to a function with paramcount parameters @@ -596,9 +685,9 @@ static void gen_jmp_ptr(void * ptr,Bits imm=0) { scale+=2; } if (sub) { - cache_addd(0xe2400000 + (temp3 << 12) + (temp3 << 16) + (ROTATE_SCALE(scale) << 7) + (imm2 & 0xff)); // sub temp3, temp3, #((imm2 & 0xff) << scale) + cache_addd( SUB_IMM(temp3, temp3, imm2 & 0xff, ROTATE_SCALE(scale)) ); // sub temp3, temp3, #((imm2 & 0xff) << scale) } else { - cache_addd(0xe2800000 + (temp3 << 12) + (temp3 << 16) + (ROTATE_SCALE(scale) << 7) + (imm2 & 0xff)); // add temp3, temp3, #((imm2 & 0xff) << scale) + cache_addd( ADD_IMM(temp3, temp3, imm2 & 0xff, ROTATE_SCALE(scale)) ); // add temp3, temp3, #((imm2 & 0xff) << scale) } imm2>>=8; scale+=8; @@ -608,31 +697,31 @@ static void gen_jmp_ptr(void * ptr,Bits imm=0) { #if (1) // (*ptr) should be word aligned if ((imm & 0x03) == 0) { - cache_addd(0xe5900000 + (temp1 << 12) + (temp3 << 16)); // ldr temp1, [temp3] + cache_addd( LDR_IMM(temp1, temp3, 0) ); // ldr temp1, [temp3] } else #endif { - cache_addd(0xe5d00000 + (temp1 << 12) + (temp3 << 16)); // ldrb temp1, [temp3] - cache_addd(0xe5d00001 + (temp2 << 12) + (temp3 << 16)); // ldrb temp2, [temp3, #1] - cache_addd(0xe1800400 + (temp1 << 12) + (temp1 << 16) + (temp2)); // orr temp1, temp1, temp2, lsl #8 - cache_addd(0xe5d00002 + (temp2 << 12) + (temp3 << 16)); // ldrb temp2, [temp3, #2] - cache_addd(0xe1800800 + (temp1 << 12) + (temp1 << 16) + (temp2)); // orr temp1, temp1, temp2, lsl #16 - cache_addd(0xe5d00003 + (temp2 << 12) + (temp3 << 16)); // ldrb temp2, [temp3, #3] - cache_addd(0xe1800c00 + (temp1 << 12) + (temp1 << 16) + (temp2)); // orr temp1, temp1, temp2, lsl #24 + cache_addd( LDRB_IMM(temp1, temp3, 0) ); // ldrb temp1, [temp3] + cache_addd( LDRB_IMM(temp2, temp3, 1) ); // ldrb temp2, [temp3, #1] + cache_addd( ORR_REG_LSL_IMM(temp1, temp1, temp2, 8) ); // orr temp1, temp1, temp2, lsl #8 + cache_addd( LDRB_IMM(temp2, temp3, 2) ); // ldrb temp2, [temp3, #2] + cache_addd( ORR_REG_LSL_IMM(temp1, temp1, temp2, 16) ); // orr temp1, temp1, temp2, lsl #16 + cache_addd( LDRB_IMM(temp2, temp3, 3) ); // ldrb temp2, [temp3, #3] + cache_addd( ORR_REG_LSL_IMM(temp1, temp1, temp2, 24) ); // orr temp1, temp1, temp2, lsl #24 } - cache_addd(0xe12fff10 + (temp1)); // bx temp1 + cache_addd( BX(temp1) ); // bx temp1 } // short conditional jump (+-127 bytes) if register is zero // the destination is set by gen_fill_branch() later static Bit32u gen_create_branch_on_zero(HostReg reg,bool dword) { if (dword) { - cache_addd(0xe3500000 + (reg << 16)); // cmp reg, #0 + cache_addd( CMP_IMM(reg, 0, 0) ); // cmp reg, #0 } else { - cache_addd(0xe1b00800 + (temp1 << 12) + (reg)); // movs temp1, reg, lsl #16 + cache_addd( MOVS_REG_LSL_IMM(temp1, reg, 16) ); // movs temp1, reg, lsl #16 } - cache_addd(0x0a000000); // beq j + cache_addd( BEQ_FWD(0) ); // beq j return ((Bit32u)cache.pos-4); } @@ -640,11 +729,11 @@ static Bit32u gen_create_branch_on_zero(HostReg reg,bool dword) { // the destination is set by gen_fill_branch() later static Bit32u gen_create_branch_on_nonzero(HostReg reg,bool dword) { if (dword) { - cache_addd(0xe3500000 + (reg << 16)); // cmp reg, #0 + cache_addd( CMP_IMM(reg, 0, 0) ); // cmp reg, #0 } else { - cache_addd(0xe1b00800 + (temp1 << 12) + (reg)); // movs temp1, reg, lsl #16 + cache_addd( MOVS_REG_LSL_IMM(temp1, reg, 16) ); // movs temp1, reg, lsl #16 } - cache_addd(0x1a000000); // bne j + cache_addd( BNE_FWD(0) ); // bne j return ((Bit32u)cache.pos-4); } @@ -663,13 +752,13 @@ static void INLINE gen_fill_branch(DRC_PTR_SIZE_IM data) { // for isdword==false the lowest 8bit of the register are tested static Bit32u gen_create_branch_long_nonzero(HostReg reg,bool isdword) { if (isdword) { - cache_addd(0xe3500000 + (reg << 16)); // cmp reg, #0 + cache_addd( CMP_IMM(reg, 0, 0) ); // cmp reg, #0 } else { - cache_addd(0xe31000ff + (reg << 16)); // tst reg, #0xff + cache_addd( TST_IMM(reg, 0xff, 0) ); // tst reg, #0xff } - cache_addd(0x0a000002); // beq nobranch - cache_addd(0xe5900000 + (temp1 << 12) + (HOST_pc << 16)); // ldr temp1, [pc, #0] - cache_addd(0xe12fff10 + (temp1)); // bx temp1 + cache_addd( BEQ_FWD(8) ); // beq nobranch (pc +8) + cache_addd( LDR_IMM(temp1, HOST_pc, 0) ); // ldr temp1, [pc, #0] + cache_addd( BX(temp1) ); // bx temp1 cache_addd(0); // fill j // nobranch: return ((Bit32u)cache.pos-4); @@ -677,10 +766,10 @@ static Bit32u gen_create_branch_long_nonzero(HostReg reg,bool isdword) { // compare 32bit-register against zero and jump if value less/equal than zero static Bit32u gen_create_branch_long_leqzero(HostReg reg) { - cache_addd(0xe3500000 + (reg << 16)); // cmp reg, #0 - cache_addd(0xca000002); // bgt nobranch - cache_addd(0xe5900000 + (temp1 << 12) + (HOST_pc << 16)); // ldr temp1, [pc, #0] - cache_addd(0xe12fff10 + (temp1)); // bx temp1 + cache_addd( CMP_IMM(reg, 0, 0) ); // cmp reg, #0 + cache_addd( BGT_FWD(8) ); // bgt nobranch (pc+8) + cache_addd( LDR_IMM(temp1, HOST_pc, 0) ); // ldr temp1, [pc, #0] + cache_addd( BX(temp1) ); // bx temp1 cache_addd(0); // fill j // nobranch: return ((Bit32u)cache.pos-4); @@ -697,23 +786,26 @@ static void gen_run_code(void) { cache_addd(0xe92d0df0); // stmfd sp!, {v1-v5,v7,v8} // adr: 8 - cache_addd(0xe5900000 + (FC_SEGS_ADDR << 12) + (HOST_pc << 16) + (64 - (8 + 8))); // ldr FC_SEGS_ADDR, [pc, #(&Segs)] + cache_addd( LDR_IMM(FC_SEGS_ADDR, HOST_pc, 64 - (8 + 8)) ); // ldr FC_SEGS_ADDR, [pc, #(&Segs)] // adr: 12 - cache_addd(0xe5900000 + (FC_REGS_ADDR << 12) + (HOST_pc << 16) + (68 - (12 + 8))); // ldr FC_REGS_ADDR, [pc, #(&cpu_regs)] - cache_addd(0xe28fe004); // add lr, pc, #4 + cache_addd( LDR_IMM(FC_REGS_ADDR, HOST_pc, 68 - (12 + 8)) ); // ldr FC_REGS_ADDR, [pc, #(&cpu_regs)] + + cache_addd( ADD_IMM(HOST_lr, HOST_pc, 4, 0) ); // add lr, pc, #4 cache_addd(0xe92d4000); // stmfd sp!, {lr} - cache_addd(0xe12fff10); // bx r0 + cache_addd( BX(HOST_r0) ); // bx r0 + cache_addd(0xe8bd0df0); // ldmfd sp!, {v1-v5,v7,v8} cache_addd(0xe8bd4000); // ldmfd sp!, {lr} - cache_addd(0xe12fff1e); // bx lr + cache_addd( BX(HOST_lr) ); // bx lr + // fill up to 64 bytes - cache_addd(0xe1a00000); // nop - cache_addd(0xe1a00000); // nop - cache_addd(0xe1a00000); // nop - cache_addd(0xe1a00000); // nop - cache_addd(0xe1a00000); // nop - cache_addd(0xe1a00000); // nop + cache_addd( NOP ); // nop + cache_addd( NOP ); // nop + cache_addd( NOP ); // nop + cache_addd( NOP ); // nop + cache_addd( NOP ); // nop + cache_addd( NOP ); // nop // adr: 64 cache_addd((Bit32u)&Segs); // address of "Segs" @@ -723,9 +815,9 @@ static void gen_run_code(void) { // return from a function static void gen_return_function(void) { - cache_addd(0xe1a00000 + (HOST_a1 << 12) + FC_RETOP); // mov a1, FC_RETOP + cache_addd( MOV_REG_LSL_IMM(HOST_a1, FC_RETOP, 0) ); // mov a1, FC_RETOP cache_addd(0xe8bd4000); // ldmfd sp!, {lr} - cache_addd(0xe12fff1e); // bx lr + cache_addd( BX(HOST_lr) ); // bx lr } #ifdef DRC_FLAGS_INVALIDATION @@ -739,32 +831,32 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { case t_ADDb: case t_ADDw: case t_ADDd: - *(Bit32u*)pos=0xe0800000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (HOST_a2); // add FC_RETOP, a1, a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=ADD_REG_LSL_IMM(FC_RETOP, HOST_a1, HOST_a2, 0); // add FC_RETOP, a1, a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_ORb: case t_ORw: case t_ORd: - *(Bit32u*)pos=0xe1800000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (HOST_a2); // orr FC_RETOP, a1, a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=ORR_REG_LSL_IMM(FC_RETOP, HOST_a1, HOST_a2, 0); // orr FC_RETOP, a1, a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_ANDb: case t_ANDw: case t_ANDd: - *(Bit32u*)pos=0xe0000000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (HOST_a2); // and FC_RETOP, a1, a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=AND_REG_LSL_IMM(FC_RETOP, HOST_a1, HOST_a2, 0); // and FC_RETOP, a1, a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_SUBb: case t_SUBw: case t_SUBd: - *(Bit32u*)pos=0xe0400000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (HOST_a2); // sub FC_RETOP, a1, a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=SUB_REG_LSL_IMM(FC_RETOP, HOST_a1, HOST_a2, 0); // sub FC_RETOP, a1, a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_XORb: case t_XORw: case t_XORd: - *(Bit32u*)pos=0xe0200000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (HOST_a2); // eor FC_RETOP, a1, a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=EOR_REG_LSL_IMM(FC_RETOP, HOST_a1, HOST_a2, 0); // eor FC_RETOP, a1, a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_CMPb: case t_CMPw: @@ -772,106 +864,106 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { case t_TESTb: case t_TESTw: case t_TESTd: - *(Bit32u*)pos=0xea000000 + (3); // b (pc+3*4) + *(Bit32u*)pos=B_FWD(12); // b (pc+3*4) break; case t_INCb: case t_INCw: case t_INCd: - *(Bit32u*)pos=0xe2800000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (1); // add FC_RETOP, a1, #1 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=ADD_IMM(FC_RETOP, HOST_a1, 1, 0); // add FC_RETOP, a1, #1 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_DECb: case t_DECw: case t_DECd: - *(Bit32u*)pos=0xe2400000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (1); // sub FC_RETOP, a1, #1 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=SUB_IMM(FC_RETOP, HOST_a1, 1, 0); // sub FC_RETOP, a1, #1 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_SHLb: case t_SHLw: case t_SHLd: - *(Bit32u*)pos=0xe1a00010 + (FC_RETOP << 12) + (HOST_a1) + (HOST_a2 << 8); // mov FC_RETOP, a1, lsl a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=MOV_REG_LSL_REG(FC_RETOP, HOST_a1, HOST_a2); // mov FC_RETOP, a1, lsl a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_SHRb: - *(Bit32u*)pos=0xe2000000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (0xff); // and FC_RETOP, a1, #0xff - *(Bit32u*)(pos+4)=0xe1a00030 + (FC_RETOP << 12) + (FC_RETOP) + (HOST_a2 << 8); // mov FC_RETOP, FC_RETOP, lsr a2 - *(Bit32u*)(pos+8)=0xe1a00000; // nop - *(Bit32u*)(pos+12)=0xe1a00000; // nop - *(Bit32u*)(pos+16)=0xe1a00000; // nop + *(Bit32u*)pos=AND_IMM(FC_RETOP, HOST_a1, 0xff, 0); // and FC_RETOP, a1, #0xff + *(Bit32u*)(pos+4)=MOV_REG_LSR_REG(FC_RETOP, FC_RETOP, HOST_a2); // mov FC_RETOP, FC_RETOP, lsr a2 + *(Bit32u*)(pos+8)=NOP; // nop + *(Bit32u*)(pos+12)=NOP; // nop + *(Bit32u*)(pos+16)=NOP; // nop break; case t_SHRw: - *(Bit32u*)pos=0xe1a00000 + (FC_RETOP << 12) + (HOST_a1) + (16 << 7); // mov FC_RETOP, a1, lsl #16 - *(Bit32u*)(pos+4)=0xe1a00020 + (FC_RETOP << 12) + (FC_RETOP) + (16 << 7); // mov FC_RETOP, FC_RETOP, lsr #16 - *(Bit32u*)(pos+8)=0xe1a00030 + (FC_RETOP << 12) + (FC_RETOP) + (HOST_a2 << 8); // mov FC_RETOP, FC_RETOP, lsr a2 - *(Bit32u*)(pos+12)=0xe1a00000; // nop - *(Bit32u*)(pos+16)=0xe1a00000; // nop + *(Bit32u*)pos=MOV_REG_LSL_IMM(FC_RETOP, HOST_a1, 16); // mov FC_RETOP, a1, lsl #16 + *(Bit32u*)(pos+4)=MOV_REG_LSR_IMM(FC_RETOP, FC_RETOP, 16); // mov FC_RETOP, FC_RETOP, lsr #16 + *(Bit32u*)(pos+8)=MOV_REG_LSR_REG(FC_RETOP, FC_RETOP, HOST_a2); // mov FC_RETOP, FC_RETOP, lsr a2 + *(Bit32u*)(pos+12)=NOP; // nop + *(Bit32u*)(pos+16)=NOP; // nop break; case t_SHRd: - *(Bit32u*)pos=0xe1a00030 + (FC_RETOP << 12) + (HOST_a1) + (HOST_a2 << 8); // mov FC_RETOP, a1, lsr a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=MOV_REG_LSR_REG(FC_RETOP, HOST_a1, HOST_a2); // mov FC_RETOP, a1, lsr a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_SARb: - *(Bit32u*)pos=0xe1a00000 + (FC_RETOP << 12) + (HOST_a1) + (24 << 7); // mov FC_RETOP, a1, lsl #24 - *(Bit32u*)(pos+4)=0xe1a00040 + (FC_RETOP << 12) + (FC_RETOP) + (24 << 7); // mov FC_RETOP, FC_RETOP, asr #24 - *(Bit32u*)(pos+8)=0xe1a00050 + (FC_RETOP << 12) + (FC_RETOP) + (HOST_a2 << 8); // mov FC_RETOP, FC_RETOP, asr a2 - *(Bit32u*)(pos+12)=0xe1a00000; // nop - *(Bit32u*)(pos+16)=0xe1a00000; // nop + *(Bit32u*)pos=MOV_REG_LSL_IMM(FC_RETOP, HOST_a1, 24); // mov FC_RETOP, a1, lsl #24 + *(Bit32u*)(pos+4)=MOV_REG_ASR_IMM(FC_RETOP, FC_RETOP, 24); // mov FC_RETOP, FC_RETOP, asr #24 + *(Bit32u*)(pos+8)=MOV_REG_ASR_REG(FC_RETOP, FC_RETOP, HOST_a2); // mov FC_RETOP, FC_RETOP, asr a2 + *(Bit32u*)(pos+12)=NOP; // nop + *(Bit32u*)(pos+16)=NOP; // nop break; case t_SARw: - *(Bit32u*)pos=0xe1a00000 + (FC_RETOP << 12) + (HOST_a1) + (16 << 7); // mov FC_RETOP, a1, lsl #16 - *(Bit32u*)(pos+4)=0xe1a00040 + (FC_RETOP << 12) + (FC_RETOP) + (16 << 7); // mov FC_RETOP, FC_RETOP, asr #16 - *(Bit32u*)(pos+8)=0xe1a00050 + (FC_RETOP << 12) + (FC_RETOP) + (HOST_a2 << 8); // mov FC_RETOP, FC_RETOP, asr a2 - *(Bit32u*)(pos+12)=0xe1a00000; // nop - *(Bit32u*)(pos+16)=0xe1a00000; // nop + *(Bit32u*)pos=MOV_REG_LSL_IMM(FC_RETOP, HOST_a1, 16); // mov FC_RETOP, a1, lsl #16 + *(Bit32u*)(pos+4)=MOV_REG_ASR_IMM(FC_RETOP, FC_RETOP, 16); // mov FC_RETOP, FC_RETOP, asr #16 + *(Bit32u*)(pos+8)=MOV_REG_ASR_REG(FC_RETOP, FC_RETOP, HOST_a2); // mov FC_RETOP, FC_RETOP, asr a2 + *(Bit32u*)(pos+12)=NOP; // nop + *(Bit32u*)(pos+16)=NOP; // nop break; case t_SARd: - *(Bit32u*)pos=0xe1a00050 + (FC_RETOP << 12) + (HOST_a1) + (HOST_a2 << 8); // mov FC_RETOP, a1, asr a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=MOV_REG_ASR_REG(FC_RETOP, HOST_a1, HOST_a2); // mov FC_RETOP, a1, asr a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_RORb: - *(Bit32u*)pos=0xe1a00000 + (FC_RETOP << 12) + (HOST_a1) + (24 << 7); // mov FC_RETOP, a1, lsl #24 - *(Bit32u*)(pos+4)=0xe1800020 + (FC_RETOP << 12) + (FC_RETOP << 16) + (FC_RETOP) + (8 << 7); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #8 - *(Bit32u*)(pos+8)=0xe1800020 + (FC_RETOP << 12) + (FC_RETOP << 16) + (FC_RETOP) + (16 << 7); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #16 - *(Bit32u*)(pos+12)=0xe1a00070 + (FC_RETOP << 12) + (FC_RETOP) + (HOST_a2 << 8); // mov FC_RETOP, FC_RETOP, ror a2 - *(Bit32u*)(pos+16)=0xe1a00000; // nop + *(Bit32u*)pos=MOV_REG_LSL_IMM(FC_RETOP, HOST_a1, 24); // mov FC_RETOP, a1, lsl #24 + *(Bit32u*)(pos+4)=ORR_REG_LSR_IMM(FC_RETOP, FC_RETOP, FC_RETOP, 8); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #8 + *(Bit32u*)(pos+8)=ORR_REG_LSR_IMM(FC_RETOP, FC_RETOP, FC_RETOP, 16); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #16 + *(Bit32u*)(pos+12)=MOV_REG_ROR_REG(FC_RETOP, FC_RETOP, HOST_a2); // mov FC_RETOP, FC_RETOP, ror a2 + *(Bit32u*)(pos+16)=NOP; // nop break; case t_RORw: - *(Bit32u*)pos=0xe1a00000 + (FC_RETOP << 12) + (HOST_a1) + (16 << 7); // mov FC_RETOP, a1, lsl #16 - *(Bit32u*)(pos+4)=0xe1800020 + (FC_RETOP << 12) + (FC_RETOP << 16) + (FC_RETOP) + (16 << 7); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #16 - *(Bit32u*)(pos+8)=0xe1a00070 + (FC_RETOP << 12) + (FC_RETOP) + (HOST_a2 << 8); // mov FC_RETOP, FC_RETOP, ror a2 - *(Bit32u*)(pos+12)=0xe1a00000; // nop - *(Bit32u*)(pos+16)=0xe1a00000; // nop + *(Bit32u*)pos=MOV_REG_LSL_IMM(FC_RETOP, HOST_a1, 16); // mov FC_RETOP, a1, lsl #16 + *(Bit32u*)(pos+4)=ORR_REG_LSR_IMM(FC_RETOP, FC_RETOP, FC_RETOP, 16); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #16 + *(Bit32u*)(pos+8)=MOV_REG_ROR_REG(FC_RETOP, FC_RETOP, HOST_a2); // mov FC_RETOP, FC_RETOP, ror a2 + *(Bit32u*)(pos+12)=NOP; // nop + *(Bit32u*)(pos+16)=NOP; // nop break; case t_RORd: - *(Bit32u*)pos=0xe1a00070 + (FC_RETOP << 12) + (HOST_a1) + (HOST_a2 << 8); // mov FC_RETOP, a1, ror a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=MOV_REG_ROR_REG(FC_RETOP, HOST_a1, HOST_a2); // mov FC_RETOP, a1, ror a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_ROLb: - *(Bit32u*)pos=0xe1a00000 + (FC_RETOP << 12) + (HOST_a1) + (24 << 7); // mov FC_RETOP, a1, lsl #24 - *(Bit32u*)(pos+4)=0xe2600000 + (HOST_a2 << 12) + (HOST_a2 << 16) + (32); // rsb a2, a2, #32 - *(Bit32u*)(pos+8)=0xe1800020 + (FC_RETOP << 12) + (FC_RETOP << 16) + (FC_RETOP) + (8 << 7); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #8 - *(Bit32u*)(pos+12)=0xe1800020 + (FC_RETOP << 12) + (FC_RETOP << 16) + (FC_RETOP) + (16 << 7); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #16 - *(Bit32u*)(pos+16)=0xe1a00070 + (FC_RETOP << 12) + (FC_RETOP) + (HOST_a2 << 8); // mov FC_RETOP, FC_RETOP, ror a2 + *(Bit32u*)pos=MOV_REG_LSL_IMM(FC_RETOP, HOST_a1, 24); // mov FC_RETOP, a1, lsl #24 + *(Bit32u*)(pos+4)=RSB_IMM(HOST_a2, HOST_a2, 32, 0); // rsb a2, a2, #32 + *(Bit32u*)(pos+8)=ORR_REG_LSR_IMM(FC_RETOP, FC_RETOP, FC_RETOP, 8); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #8 + *(Bit32u*)(pos+12)=ORR_REG_LSR_IMM(FC_RETOP, FC_RETOP, FC_RETOP, 16); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #16 + *(Bit32u*)(pos+16)=MOV_REG_ROR_REG(FC_RETOP, FC_RETOP, HOST_a2); // mov FC_RETOP, FC_RETOP, ror a2 break; case t_ROLw: - *(Bit32u*)pos=0xe1a00000 + (FC_RETOP << 12) + (HOST_a1) + (16 << 7); // mov FC_RETOP, a1, lsl #16 - *(Bit32u*)(pos+4)=0xe2600000 + (HOST_a2 << 12) + (HOST_a2 << 16) + (32); // rsb a2, a2, #32 - *(Bit32u*)(pos+8)=0xe1800020 + (FC_RETOP << 12) + (FC_RETOP << 16) + (FC_RETOP) + (16 << 7); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #16 - *(Bit32u*)(pos+12)=0xe1a00070 + (FC_RETOP << 12) + (FC_RETOP) + (HOST_a2 << 8); // mov FC_RETOP, FC_RETOP, ror a2 - *(Bit32u*)(pos+16)=0xe1a00000; // nop + *(Bit32u*)pos=MOV_REG_LSL_IMM(FC_RETOP, HOST_a1, 16); // mov FC_RETOP, a1, lsl #16 + *(Bit32u*)(pos+4)=RSB_IMM(HOST_a2, HOST_a2, 32, 0); // rsb a2, a2, #32 + *(Bit32u*)(pos+8)=ORR_REG_LSR_IMM(FC_RETOP, FC_RETOP, FC_RETOP, 16); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #16 + *(Bit32u*)(pos+12)=MOV_REG_ROR_REG(FC_RETOP, FC_RETOP, HOST_a2); // mov FC_RETOP, FC_RETOP, ror a2 + *(Bit32u*)(pos+16)=NOP; // nop break; case t_ROLd: - *(Bit32u*)pos=0xe2600000 + (HOST_a2 << 12) + (HOST_a2 << 16) + (32); // rsb a2, a2, #32 - *(Bit32u*)(pos+4)=0xe1a00070 + (FC_RETOP << 12) + (HOST_a1) + (HOST_a2 << 8); // mov FC_RETOP, a1, ror a2 - *(Bit32u*)(pos+8)=0xe1a00000; // nop - *(Bit32u*)(pos+12)=0xe1a00000; // nop - *(Bit32u*)(pos+16)=0xe1a00000; // nop + *(Bit32u*)pos=RSB_IMM(HOST_a2, HOST_a2, 32, 0); // rsb a2, a2, #32 + *(Bit32u*)(pos+4)=MOV_REG_ROR_REG(FC_RETOP, HOST_a1, HOST_a2); // mov FC_RETOP, a1, ror a2 + *(Bit32u*)(pos+8)=NOP; // nop + *(Bit32u*)(pos+12)=NOP; // nop + *(Bit32u*)(pos+16)=NOP; // nop break; case t_NEGb: case t_NEGw: case t_NEGd: - *(Bit32u*)pos=0xe2600000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (0); // rsb FC_RETOP, a1, #0 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=RSB_IMM(FC_RETOP, HOST_a1, 0, 0); // rsb FC_RETOP, a1, #0 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; default: *(Bit32u*)(pos+12)=(Bit32u)fct_ptr; // simple_func @@ -886,24 +978,23 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { static void cache_block_before_close(void) { } - #ifdef DRC_USE_SEGS_ADDR // mov 16bit value from Segs[index] into dest_reg using FC_SEGS_ADDR (index modulo 2 must be zero) // 16bit moves may destroy the upper 16bit of the destination register static void gen_mov_seg16_to_reg(HostReg dest_reg,Bitu index) { - cache_addd(0xe1d000b0 + (dest_reg << 12) + (FC_SEGS_ADDR << 16) + ((index & 0xf0) << 4) + (index & 0x0f)); // ldrh dest_reg, [FC_SEGS_ADDR, #index] + cache_addd( LDRH_IMM(dest_reg, FC_SEGS_ADDR, index) ); // ldrh dest_reg, [FC_SEGS_ADDR, #index] } // mov 32bit value from Segs[index] into dest_reg using FC_SEGS_ADDR (index modulo 4 must be zero) static void gen_mov_seg32_to_reg(HostReg dest_reg,Bitu index) { - cache_addd(0xe5900000 + (dest_reg << 12) + (FC_SEGS_ADDR << 16) + (index)); // ldr dest_reg, [FC_SEGS_ADDR, #index] + cache_addd( LDR_IMM(dest_reg, FC_SEGS_ADDR, index) ); // ldr dest_reg, [FC_SEGS_ADDR, #index] } // add a 32bit value from Segs[index] to a full register using FC_SEGS_ADDR (index modulo 4 must be zero) static void gen_add_seg32_to_reg(HostReg reg,Bitu index) { - cache_addd(0xe5900000 + (temp1 << 12) + (FC_SEGS_ADDR << 16) + (index)); // ldr temp1, [FC_SEGS_ADDR, #index] - cache_addd(0xe0800000 + (reg << 12) + (reg << 16) + (temp1)); // add reg, reg, temp1 + cache_addd( LDR_IMM(temp1, FC_SEGS_ADDR, index) ); // ldr temp1, [FC_SEGS_ADDR, #index] + cache_addd( ADD_REG_LSL_IMM(reg, reg, temp1, 0) ); // add reg, reg, temp1 } #endif @@ -913,21 +1004,21 @@ static void gen_add_seg32_to_reg(HostReg reg,Bitu index) { // mov 16bit value from cpu_regs[index] into dest_reg using FC_REGS_ADDR (index modulo 2 must be zero) // 16bit moves may destroy the upper 16bit of the destination register static void gen_mov_regval16_to_reg(HostReg dest_reg,Bitu index) { - cache_addd(0xe1d000b0 + (dest_reg << 12) + (FC_REGS_ADDR << 16) + ((index & 0xf0) << 4) + (index & 0x0f)); // ldrh dest_reg, [FC_REGS_ADDR, #index] + cache_addd( LDRH_IMM(dest_reg, FC_REGS_ADDR, index) ); // ldrh dest_reg, [FC_REGS_ADDR, #index] } // mov 32bit value from cpu_regs[index] into dest_reg using FC_REGS_ADDR (index modulo 4 must be zero) static void gen_mov_regval32_to_reg(HostReg dest_reg,Bitu index) { - cache_addd(0xe5900000 + (dest_reg << 12) + (FC_REGS_ADDR << 16) + (index)); // ldr dest_reg, [FC_REGS_ADDR, #index] + cache_addd( LDR_IMM(dest_reg, FC_REGS_ADDR, index) ); // ldr dest_reg, [FC_REGS_ADDR, #index] } // move a 32bit (dword==true) or 16bit (dword==false) value from cpu_regs[index] into dest_reg using FC_REGS_ADDR (if dword==true index modulo 4 must be zero) (if dword==false index modulo 2 must be zero) // 16bit moves may destroy the upper 16bit of the destination register static void gen_mov_regword_to_reg(HostReg dest_reg,Bitu index,bool dword) { if (dword) { - cache_addd(0xe5900000 + (dest_reg << 12) + (FC_REGS_ADDR << 16) + (index)); // ldr dest_reg, [FC_REGS_ADDR, #index] + cache_addd( LDR_IMM(dest_reg, FC_REGS_ADDR, index) ); // ldr dest_reg, [FC_REGS_ADDR, #index] } else { - cache_addd(0xe1d000b0 + (dest_reg << 12) + (FC_REGS_ADDR << 16) + ((index & 0xf0) << 4) + (index & 0x0f)); // ldrh dest_reg, [FC_REGS_ADDR, #index] + cache_addd( LDRH_IMM(dest_reg, FC_REGS_ADDR, index) ); // ldrh dest_reg, [FC_REGS_ADDR, #index] } } @@ -936,7 +1027,7 @@ static void gen_mov_regword_to_reg(HostReg dest_reg,Bitu index,bool dword) { // this function does not use FC_OP1/FC_OP2 as dest_reg as these // registers might not be directly byte-accessible on some architectures static void gen_mov_regbyte_to_reg_low(HostReg dest_reg,Bitu index) { - cache_addd(0xe5d00000 + (dest_reg << 12) + (FC_REGS_ADDR << 16) + (index)); // ldrb dest_reg, [FC_REGS_ADDR, #index] + cache_addd( LDRB_IMM(dest_reg, FC_REGS_ADDR, index) ); // ldrb dest_reg, [FC_REGS_ADDR, #index] } // move an 8bit value from cpu_regs[index] into dest_reg using FC_REGS_ADDR @@ -944,39 +1035,39 @@ static void gen_mov_regbyte_to_reg_low(HostReg dest_reg,Bitu index) { // this function can use FC_OP1/FC_OP2 as dest_reg which are // not directly byte-accessible on some architectures static void INLINE gen_mov_regbyte_to_reg_low_canuseword(HostReg dest_reg,Bitu index) { - cache_addd(0xe5d00000 + (dest_reg << 12) + (FC_REGS_ADDR << 16) + (index)); // ldrb dest_reg, [FC_REGS_ADDR, #index] + cache_addd( LDRB_IMM(dest_reg, FC_REGS_ADDR, index) ); // ldrb dest_reg, [FC_REGS_ADDR, #index] } // add a 32bit value from cpu_regs[index] to a full register using FC_REGS_ADDR (index modulo 4 must be zero) static void gen_add_regval32_to_reg(HostReg reg,Bitu index) { - cache_addd(0xe5900000 + (temp2 << 12) + (FC_REGS_ADDR << 16) + (index)); // ldr temp2, [FC_REGS_ADDR, #index] - cache_addd(0xe0800000 + (reg << 12) + (reg << 16) + (temp2)); // add reg, reg, temp2 + cache_addd( LDR_IMM(temp2, FC_REGS_ADDR, index) ); // ldr temp2, [FC_REGS_ADDR, #index] + cache_addd( ADD_REG_LSL_IMM(reg, reg, temp2, 0) ); // add reg, reg, temp2 } // move 16bit of register into cpu_regs[index] using FC_REGS_ADDR (index modulo 2 must be zero) static void gen_mov_regval16_from_reg(HostReg src_reg,Bitu index) { - cache_addd(0xe1c000b0 + (src_reg << 12) + (FC_REGS_ADDR << 16) + ((index & 0xf0) << 4) + (index & 0x0f)); // strh src_reg, [FC_REGS_ADDR, #index] + cache_addd( STRH_IMM(src_reg, FC_REGS_ADDR, index) ); // strh src_reg, [FC_REGS_ADDR, #index] } // move 32bit of register into cpu_regs[index] using FC_REGS_ADDR (index modulo 4 must be zero) static void gen_mov_regval32_from_reg(HostReg src_reg,Bitu index) { - cache_addd(0xe5800000 + (src_reg << 12) + (FC_REGS_ADDR << 16) + (index)); // str src_reg, [FC_REGS_ADDR, #index] + cache_addd( STR_IMM(src_reg, FC_REGS_ADDR, index) ); // str src_reg, [FC_REGS_ADDR, #index] } // move 32bit (dword==true) or 16bit (dword==false) of a register into cpu_regs[index] using FC_REGS_ADDR (if dword==true index modulo 4 must be zero) (if dword==false index modulo 2 must be zero) static void gen_mov_regword_from_reg(HostReg src_reg,Bitu index,bool dword) { if (dword) { - cache_addd(0xe5800000 + (src_reg << 12) + (FC_REGS_ADDR << 16) + (index)); // str src_reg, [FC_REGS_ADDR, #index] + cache_addd( STR_IMM(src_reg, FC_REGS_ADDR, index) ); // str src_reg, [FC_REGS_ADDR, #index] } else { - cache_addd(0xe1c000b0 + (src_reg << 12) + (FC_REGS_ADDR << 16) + ((index & 0xf0) << 4) + (index & 0x0f)); // strh src_reg, [FC_REGS_ADDR, #index] + cache_addd( STRH_IMM(src_reg, FC_REGS_ADDR, index) ); // strh src_reg, [FC_REGS_ADDR, #index] } } // move the lowest 8bit of a register into cpu_regs[index] using FC_REGS_ADDR static void gen_mov_regbyte_from_reg_low(HostReg src_reg,Bitu index) { - cache_addd(0xe5c00000 + (src_reg << 12) + (FC_REGS_ADDR << 16) + (index)); // strb src_reg, [FC_REGS_ADDR, #index] + cache_addd( STRB_IMM(src_reg, FC_REGS_ADDR, index) ); // strb src_reg, [FC_REGS_ADDR, #index] } #endif diff --git a/src/cpu/core_dynrec/risc_armv4le-s3.h b/src/cpu/core_dynrec/risc_armv4le-s3.h index 42f6a01..9c39de4 100644 --- a/src/cpu/core_dynrec/risc_armv4le-s3.h +++ b/src/cpu/core_dynrec/risc_armv4le-s3.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2002-2008 The DOSBox Team + * Copyright (C) 2002-2009 The DOSBox Team * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,7 +16,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $Id: risc_armv4le-s3.h,v 1.3 2008/09/19 16:48:02 c2woody Exp $ */ +/* $Id: risc_armv4le-s3.h,v 1.4 2009/05/16 21:52:47 c2woody Exp $ */ /* ARMv4 (little endian) backend by M-HT (speed-tweaked arm version) */ @@ -58,20 +58,109 @@ #define FC_SEGS_ADDR HOST_v8 #endif + // helper macro #define ROTATE_SCALE(x) ( (x)?(32 - x):(0) ) + +// instruction encodings + +// move +// mov dst, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define MOV_IMM(dst, imm, rimm) (0xe3a00000 + ((dst) << 12) + (imm) + ((rimm) << 7) ) +// mov dst, src, lsl #imm +#define MOV_REG_LSL_IMM(dst, src, imm) (0xe1a00000 + ((dst) << 12) + (src) + ((imm) << 7) ) +// movs dst, src, lsl #imm +#define MOVS_REG_LSL_IMM(dst, src, imm) (0xe1b00000 + ((dst) << 12) + (src) + ((imm) << 7) ) +// mov dst, src, lsr #imm +#define MOV_REG_LSR_IMM(dst, src, imm) (0xe1a00020 + ((dst) << 12) + (src) + ((imm) << 7) ) +// mov dst, src, asr #imm +#define MOV_REG_ASR_IMM(dst, src, imm) (0xe1a00040 + ((dst) << 12) + (src) + ((imm) << 7) ) +// mov dst, src, lsl rreg +#define MOV_REG_LSL_REG(dst, src, rreg) (0xe1a00010 + ((dst) << 12) + (src) + ((rreg) << 8) ) +// mov dst, src, lsr rreg +#define MOV_REG_LSR_REG(dst, src, rreg) (0xe1a00030 + ((dst) << 12) + (src) + ((rreg) << 8) ) +// mov dst, src, asr rreg +#define MOV_REG_ASR_REG(dst, src, rreg) (0xe1a00050 + ((dst) << 12) + (src) + ((rreg) << 8) ) +// mov dst, src, ror rreg +#define MOV_REG_ROR_REG(dst, src, rreg) (0xe1a00070 + ((dst) << 12) + (src) + ((rreg) << 8) ) +// mvn dst, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define MVN_IMM(dst, imm, rimm) (0xe3e00000 + ((dst) << 12) + (imm) + ((rimm) << 7) ) + +// arithmetic +// add dst, src, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define ADD_IMM(dst, src, imm, rimm) (0xe2800000 + ((dst) << 12) + ((src) << 16) + (imm) + ((rimm) << 7) ) +// add dst, src1, src2, lsl #imm +#define ADD_REG_LSL_IMM(dst, src1, src2, imm) (0xe0800000 + ((dst) << 12) + ((src1) << 16) + (src2) + ((imm) << 7) ) +// sub dst, src, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define SUB_IMM(dst, src, imm, rimm) (0xe2400000 + ((dst) << 12) + ((src) << 16) + (imm) + ((rimm) << 7) ) +// sub dst, src1, src2, lsl #imm +#define SUB_REG_LSL_IMM(dst, src1, src2, imm) (0xe0400000 + ((dst) << 12) + ((src1) << 16) + (src2) + ((imm) << 7) ) +// rsb dst, src, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define RSB_IMM(dst, src, imm, rimm) (0xe2600000 + ((dst) << 12) + ((src) << 16) + (imm) + ((rimm) << 7) ) +// cmp src, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define CMP_IMM(src, imm, rimm) (0xe3500000 + ((src) << 16) + (imm) + ((rimm) << 7) ) +// nop +#define NOP MOV_REG_LSL_IMM(HOST_r0, HOST_r0, 0) + +// logical +// tst src, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define TST_IMM(src, imm, rimm) (0xe3100000 + ((src) << 16) + (imm) + ((rimm) << 7) ) +// and dst, src, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define AND_IMM(dst, src, imm, rimm) (0xe2000000 + ((dst) << 12) + ((src) << 16) + (imm) + ((rimm) << 7) ) +// and dst, src1, src2, lsl #imm +#define AND_REG_LSL_IMM(dst, src1, src2, imm) (0xe0000000 + ((dst) << 12) + ((src1) << 16) + (src2) + ((imm) << 7) ) +// orr dst, src, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define ORR_IMM(dst, src, imm, rimm) (0xe3800000 + ((dst) << 12) + ((src) << 16) + (imm) + ((rimm) << 7) ) +// orr dst, src1, src2, lsl #imm +#define ORR_REG_LSL_IMM(dst, src1, src2, imm) (0xe1800000 + ((dst) << 12) + ((src1) << 16) + (src2) + ((imm) << 7) ) +// orr dst, src1, src2, lsr #imm +#define ORR_REG_LSR_IMM(dst, src1, src2, imm) (0xe1800020 + ((dst) << 12) + ((src1) << 16) + (src2) + ((imm) << 7) ) +// eor dst, src1, src2, lsl #imm +#define EOR_REG_LSL_IMM(dst, src1, src2, imm) (0xe0200000 + ((dst) << 12) + ((src1) << 16) + (src2) + ((imm) << 7) ) +// bic dst, src, #(imm ror rimm) @ 0 <= imm <= 255 & rimm mod 2 = 0 +#define BIC_IMM(dst, src, imm, rimm) (0xe3c00000 + ((dst) << 12) + ((src) << 16) + (imm) + ((rimm) << 7) ) + +// load +// ldr reg, [addr, #imm] @ 0 <= imm < 4096 +#define LDR_IMM(reg, addr, imm) (0xe5900000 + ((reg) << 12) + ((addr) << 16) + (imm) ) +// ldrh reg, [addr, #imm] @ 0 <= imm < 256 +#define LDRH_IMM(reg, addr, imm) (0xe1d000b0 + ((reg) << 12) + ((addr) << 16) + (((imm) & 0xf0) << 4) + ((imm) & 0x0f) ) +// ldrb reg, [addr, #imm] @ 0 <= imm < 4096 +#define LDRB_IMM(reg, addr, imm) (0xe5d00000 + ((reg) << 12) + ((addr) << 16) + (imm) ) + +// store +// str reg, [addr, #imm] @ 0 <= imm < 4096 +#define STR_IMM(reg, addr, imm) (0xe5800000 + ((reg) << 12) + ((addr) << 16) + (imm) ) +// strh reg, [addr, #imm] @ 0 <= imm < 256 +#define STRH_IMM(reg, addr, imm) (0xe1c000b0 + ((reg) << 12) + ((addr) << 16) + (((imm) & 0xf0) << 4) + ((imm) & 0x0f) ) +// strb reg, [addr, #imm] @ 0 <= imm < 4096 +#define STRB_IMM(reg, addr, imm) (0xe5c00000 + ((reg) << 12) + ((addr) << 16) + (imm) ) + +// branch +// beq pc+imm @ 0 <= imm < 32M & imm mod 4 = 0 +#define BEQ_FWD(imm) (0x0a000000 + ((imm) >> 2) ) +// bne pc+imm @ 0 <= imm < 32M & imm mod 4 = 0 +#define BNE_FWD(imm) (0x1a000000 + ((imm) >> 2) ) +// bgt pc+imm @ 0 <= imm < 32M & imm mod 4 = 0 +#define BGT_FWD(imm) (0xca000000 + ((imm) >> 2) ) +// b pc+imm @ 0 <= imm < 32M & imm mod 4 = 0 +#define B_FWD(imm) (0xea000000 + ((imm) >> 2) ) +// bx reg +#define BX(reg) (0xe12fff10 + (reg) ) + + // move a full register from reg_src to reg_dst static void gen_mov_regs(HostReg reg_dst,HostReg reg_src) { if(reg_src == reg_dst) return; - cache_addd(0xe1a00000 + (reg_dst << 12) + reg_src); // mov reg_dst, reg_src + cache_addd( MOV_REG_LSL_IMM(reg_dst, reg_src, 0) ); // mov reg_dst, reg_src } // move a 32bit constant value into dest_reg static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) { Bits first, scale; if (imm == 0) { - cache_addd(0xe3a00000 + (dest_reg << 12)); // mov dest_reg, #0 + cache_addd( MOV_IMM(dest_reg, 0, 0) ); // mov dest_reg, #0 } else { scale = 0; first = 1; @@ -81,10 +170,10 @@ static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) { scale+=2; } if (first) { - cache_addd(0xe3a00000 + (dest_reg << 12) + (ROTATE_SCALE(scale) << 7) + (imm & 0xff)); // mov dest_reg, #((imm & 0xff) << scale) + cache_addd( MOV_IMM(dest_reg, imm & 0xff, ROTATE_SCALE(scale)) ); // mov dest_reg, #((imm & 0xff) << scale) first = 0; } else { - cache_addd(0xe3800000 + (dest_reg << 12) + (dest_reg << 16) + (ROTATE_SCALE(scale) << 7) + (imm & 0xff)); // orr dest_reg, dest_reg, #((imm & 0xff) << scale) + cache_addd( ORR_IMM(dest_reg, dest_reg, imm & 0xff, ROTATE_SCALE(scale)) ); // orr dest_reg, dest_reg, #((imm & 0xff) << scale) } imm>>=8; scale+=8; @@ -98,26 +187,26 @@ static void gen_mov_word_to_reg_helper(HostReg dest_reg,void* data,bool dword,Ho if (dword) { if ((Bit32u)data & 3) { if ( ((Bit32u)data & 3) == 2 ) { - cache_addd(0xe1d000b0 + (dest_reg << 12) + (data_reg << 16)); // ldrh dest_reg, [data_reg] - cache_addd(0xe1d000b2 + (temp2 << 12) + (data_reg << 16)); // ldrh temp2, [data_reg, #2] - cache_addd(0xe1800800 + (dest_reg << 12) + (dest_reg << 16) + (temp2)); // orr dest_reg, dest_reg, temp2, lsl #16 + cache_addd( LDRH_IMM(dest_reg, data_reg, 0) ); // ldrh dest_reg, [data_reg] + cache_addd( LDRH_IMM(temp2, data_reg, 2) ); // ldrh temp2, [data_reg, #2] + cache_addd( ORR_REG_LSL_IMM(dest_reg, dest_reg, temp2, 16) ); // orr dest_reg, dest_reg, temp2, lsl #16 } else { - cache_addd(0xe5d00000 + (dest_reg << 12) + (data_reg << 16)); // ldrb dest_reg, [data_reg] - cache_addd(0xe1d000b1 + (temp2 << 12) + (data_reg << 16)); // ldrh temp2, [data_reg, #1] - cache_addd(0xe1800400 + (dest_reg << 12) + (dest_reg << 16) + (temp2)); // orr dest_reg, dest_reg, temp2, lsl #8 - cache_addd(0xe5d00003 + (temp2 << 12) + (data_reg << 16)); // ldrb temp2, [data_reg, #3] - cache_addd(0xe1800c00 + (dest_reg << 12) + (dest_reg << 16) + (temp2)); // orr dest_reg, dest_reg, temp2, lsl #24 + cache_addd( LDRB_IMM(dest_reg, data_reg, 0) ); // ldrb dest_reg, [data_reg] + cache_addd( LDRH_IMM(temp2, data_reg, 1) ); // ldrh temp2, [data_reg, #1] + cache_addd( ORR_REG_LSL_IMM(dest_reg, dest_reg, temp2, 8) ); // orr dest_reg, dest_reg, temp2, lsl #8 + cache_addd( LDRB_IMM(temp2, data_reg, 3) ); // ldrb temp2, [data_reg, #3] + cache_addd( ORR_REG_LSL_IMM(dest_reg, dest_reg, temp2, 24) ); // orr dest_reg, dest_reg, temp2, lsl #24 } } else { - cache_addd(0xe5900000 + (dest_reg << 12) + (data_reg << 16)); // ldr dest_reg, [data_reg] + cache_addd( LDR_IMM(dest_reg, data_reg, 0) ); // ldr dest_reg, [data_reg] } } else { if ((Bit32u)data & 1) { - cache_addd(0xe5d00000 + (dest_reg << 12) + (data_reg << 16)); // ldrb dest_reg, [data_reg] - cache_addd(0xe5d00001 + (temp2 << 12) + (data_reg << 16)); // ldrb temp2, [data_reg, #1] - cache_addd(0xe1800400 + (dest_reg << 12) + (dest_reg << 16) + (temp2)); // orr dest_reg, dest_reg, temp2, lsl #8 + cache_addd( LDRB_IMM(dest_reg, data_reg, 0) ); // ldrb dest_reg, [data_reg] + cache_addd( LDRB_IMM(temp2, data_reg, 1) ); // ldrb temp2, [data_reg, #1] + cache_addd( ORR_REG_LSL_IMM(dest_reg, dest_reg, temp2, 8) ); // orr dest_reg, dest_reg, temp2, lsl #8 } else { - cache_addd(0xe1d000b0 + (dest_reg << 12) + (data_reg << 16)); // ldrh dest_reg, [data_reg] + cache_addd( LDRH_IMM(dest_reg, data_reg, 0) ); // ldrh dest_reg, [data_reg] } } } @@ -141,26 +230,26 @@ static void gen_mov_word_from_reg_helper(HostReg src_reg,void* dest,bool dword, if (dword) { if ((Bit32u)dest & 3) { if ( ((Bit32u)dest & 3) == 2 ) { - cache_addd(0xe1c000b0 + (src_reg << 12) + (data_reg << 16)); // strh src_reg, [data_reg] - cache_addd(0xe1a00820 + (temp2 << 12) + (src_reg)); // mov temp2, src_reg, lsr #16 - cache_addd(0xe1c000b2 + (temp2 << 12) + (data_reg << 16)); // strh temp2, [data_reg, #2] + cache_addd( STRH_IMM(src_reg, data_reg, 0) ); // strh src_reg, [data_reg] + cache_addd( MOV_REG_LSR_IMM(temp2, src_reg, 16) ); // mov temp2, src_reg, lsr #16 + cache_addd( STRH_IMM(temp2, data_reg, 2) ); // strh temp2, [data_reg, #2] } else { - cache_addd(0xe5c00000 + (src_reg << 12) + (data_reg << 16)); // strb src_reg, [data_reg] - cache_addd(0xe1a00420 + (temp2 << 12) + (src_reg)); // mov temp2, src_reg, lsr #8 - cache_addd(0xe1c000b1 + (temp2 << 12) + (data_reg << 16)); // strh temp2, [data_reg, #1] - cache_addd(0xe1a00820 + (temp2 << 12) + (temp2)); // mov temp2, temp2, lsr #16 - cache_addd(0xe5c00003 + (temp2 << 12) + (data_reg << 16)); // strb temp2, [data_reg, #3] + cache_addd( STRB_IMM(src_reg, data_reg, 0) ); // strb src_reg, [data_reg] + cache_addd( MOV_REG_LSR_IMM(temp2, src_reg, 8) ); // mov temp2, src_reg, lsr #8 + cache_addd( STRH_IMM(temp2, data_reg, 1) ); // strh temp2, [data_reg, #1] + cache_addd( MOV_REG_LSR_IMM(temp2, temp2, 16) ); // mov temp2, temp2, lsr #16 + cache_addd( STRB_IMM(temp2, data_reg, 3) ); // strb temp2, [data_reg, #3] } } else { - cache_addd(0xe5800000 + (src_reg << 12) + (data_reg << 16)); // str src_reg, [data_reg] + cache_addd( STR_IMM(src_reg, data_reg, 0) ); // str src_reg, [data_reg] } } else { if ((Bit32u)dest & 1) { - cache_addd(0xe5c00000 + (src_reg << 12) + (data_reg << 16)); // strb src_reg, [data_reg] - cache_addd(0xe1a00420 + (temp2 << 12) + (src_reg)); // mov temp2, src_reg, lsr #8 - cache_addd(0xe5c00001 + (temp2 << 12) + (data_reg << 16)); // strb temp2, [data_reg, #1] + cache_addd( STRB_IMM(src_reg, data_reg, 0) ); // strb src_reg, [data_reg] + cache_addd( MOV_REG_LSR_IMM(temp2, src_reg, 8) ); // mov temp2, src_reg, lsr #8 + cache_addd( STRB_IMM(temp2, data_reg, 1) ); // strb temp2, [data_reg, #1] } else { - cache_addd(0xe1c000b0 + (src_reg << 12) + (data_reg << 16)); // strh src_reg, [data_reg] + cache_addd( STRH_IMM(src_reg, data_reg, 0) ); // strh src_reg, [data_reg] } } } @@ -177,7 +266,7 @@ static void gen_mov_word_from_reg(HostReg src_reg,void* dest,bool dword) { // registers might not be directly byte-accessible on some architectures static void gen_mov_byte_to_reg_low(HostReg dest_reg,void* data) { gen_mov_dword_to_reg_imm(temp1, (Bit32u)data); - cache_addd(0xe5d00000 + (dest_reg << 12) + (temp1 << 16)); // ldrb dest_reg, [temp1] + cache_addd( LDRB_IMM(dest_reg, temp1, 0) ); // ldrb dest_reg, [temp1] } // move an 8bit value from memory into dest_reg @@ -193,7 +282,7 @@ static void INLINE gen_mov_byte_to_reg_low_canuseword(HostReg dest_reg,void* dat // this function does not use FC_OP1/FC_OP2 as dest_reg as these // registers might not be directly byte-accessible on some architectures static void gen_mov_byte_to_reg_low_imm(HostReg dest_reg,Bit8u imm) { - cache_addd(0xe3a00000 + (dest_reg << 12) + (imm)); // mov dest_reg, #(imm) + cache_addd( MOV_IMM(dest_reg, imm, 0) ); // mov dest_reg, #(imm) } // move an 8bit constant value into dest_reg @@ -207,7 +296,7 @@ static void INLINE gen_mov_byte_to_reg_low_imm_canuseword(HostReg dest_reg,Bit8u // move the lowest 8bit of a register into memory static void gen_mov_byte_from_reg_low(HostReg src_reg,void* dest) { gen_mov_dword_to_reg_imm(temp1, (Bit32u)dest); - cache_addd(0xe5c00000 + (src_reg << 12) + (temp1 << 16)); // strb src_reg, [temp1] + cache_addd( STRB_IMM(src_reg, temp1, 0) ); // strb src_reg, [temp1] } @@ -216,10 +305,10 @@ static void gen_mov_byte_from_reg_low(HostReg src_reg,void* dest) { // the register is zero-extended (sign==false) or sign-extended (sign==true) static void gen_extend_byte(bool sign,HostReg reg) { if (sign) { - cache_addd(0xe1a00c00 + (reg << 12) + (reg)); // mov reg, reg, lsl #24 - cache_addd(0xe1a00c40 + (reg << 12) + (reg)); // mov reg, reg, asr #24 + cache_addd( MOV_REG_LSL_IMM(reg, reg, 24) ); // mov reg, reg, lsl #24 + cache_addd( MOV_REG_ASR_IMM(reg, reg, 24) ); // mov reg, reg, asr #24 } else { - cache_addd(0xe20000ff + (reg << 12) + (reg << 16)); // and reg, reg, #0xff + cache_addd( AND_IMM(reg, reg, 0xff, 0) ); // and reg, reg, #0xff } } @@ -227,18 +316,18 @@ static void gen_extend_byte(bool sign,HostReg reg) { // the register is zero-extended (sign==false) or sign-extended (sign==true) static void gen_extend_word(bool sign,HostReg reg) { if (sign) { - cache_addd(0xe1a00800 + (reg << 12) + (reg)); // mov reg, reg, lsl #16 - cache_addd(0xe1a00840 + (reg << 12) + (reg)); // mov reg, reg, asr #16 + cache_addd( MOV_REG_LSL_IMM(reg, reg, 16) ); // mov reg, reg, lsl #16 + cache_addd( MOV_REG_ASR_IMM(reg, reg, 16) ); // mov reg, reg, asr #16 } else { - cache_addd(0xe1a00800 + (reg << 12) + (reg)); // mov reg, reg, lsl #16 - cache_addd(0xe1a00820 + (reg << 12) + (reg)); // mov reg, reg, lsr #16 + cache_addd( MOV_REG_LSL_IMM(reg, reg, 16) ); // mov reg, reg, lsl #16 + cache_addd( MOV_REG_LSR_IMM(reg, reg, 16) ); // mov reg, reg, lsr #16 } } // add a 32bit value from memory to a full register static void gen_add(HostReg reg,void* op) { gen_mov_word_to_reg(temp3, op, 1); - cache_addd(0xe0800000 + (reg << 12) + (reg << 16) + (temp3)); // add reg, reg, temp3 + cache_addd( ADD_REG_LSL_IMM(reg, reg, temp3, 0) ); // add reg, reg, temp3 } // add a 32bit constant value to a full register @@ -246,7 +335,7 @@ static void gen_add_imm(HostReg reg,Bit32u imm) { Bits scale; if(!imm) return; if (imm == 0xffffffff) { - cache_addd(0xe2400001 + (reg << 12) + (reg << 16)); // sub reg, reg, #1 + cache_addd( SUB_IMM(reg, reg, 1, 0) ); // sub reg, reg, #1 } else { scale = 0; while (imm) { @@ -254,7 +343,7 @@ static void gen_add_imm(HostReg reg,Bit32u imm) { imm>>=2; scale+=2; } - cache_addd(0xe2800000 + (reg << 12) + (reg << 16) + (ROTATE_SCALE(scale) << 7) + (imm & 0xff)); // add reg, reg, #((imm & 0xff) << scale) + cache_addd( ADD_IMM(reg, reg, imm & 0xff, ROTATE_SCALE(scale)) ); // add reg, reg, #((imm & 0xff) << scale) imm>>=8; scale+=8; } @@ -268,7 +357,7 @@ static void gen_and_imm(HostReg reg,Bit32u imm) { imm2 = ~imm; if(!imm2) return; if (!imm) { - cache_addd(0xe3a00000 + (reg << 12)); // mov reg, #0 + cache_addd( MOV_IMM(reg, 0, 0) ); // mov reg, #0 } else { scale = 0; while (imm2) { @@ -276,7 +365,7 @@ static void gen_and_imm(HostReg reg,Bit32u imm) { imm2>>=2; scale+=2; } - cache_addd(0xe3c00000 + (reg << 12) + (reg << 16) + (ROTATE_SCALE(scale) << 7) + (imm2 & 0xff)); // bic reg, reg, #((imm2 & 0xff) << scale) + cache_addd( BIC_IMM(reg, reg, imm2 & 0xff, ROTATE_SCALE(scale)) ); // bic reg, reg, #((imm2 & 0xff) << scale) imm2>>=8; scale+=8; } @@ -301,9 +390,9 @@ static void gen_add_direct_byte(void* dest,Bit8s imm) { gen_mov_dword_to_reg_imm(temp1, (Bit32u)dest); gen_mov_word_to_reg_helper(temp3, dest, 1, temp1); if (imm >= 0) { - cache_addd(0xe2800000 + (temp3 << 12) + (temp3 << 16) + ((Bit32s)imm)); // add temp3, temp3, #(imm) + cache_addd( ADD_IMM(temp3, temp3, (Bit32s)imm, 0) ); // add temp3, temp3, #(imm) } else { - cache_addd(0xe2400000 + (temp3 << 12) + (temp3 << 16) + (-((Bit32s)imm))); // sub temp3, temp3, #(-imm) + cache_addd( SUB_IMM(temp3, temp3, -((Bit32s)imm), 0) ); // sub temp3, temp3, #(-imm) } gen_mov_word_from_reg_helper(temp3, dest, 1, temp1); } @@ -323,7 +412,7 @@ static void gen_add_direct_word(void* dest,Bit32u imm,bool dword) { } else { gen_mov_word_to_reg_imm(temp2, (Bit16u)imm); } - cache_addd(0xe0800000 + (temp3 << 12) + (temp3 << 16) + (temp2)); // add temp3, temp3, temp2 + cache_addd( ADD_REG_LSL_IMM(temp3, temp3, temp2, 0) ); // add temp3, temp3, temp2 gen_mov_word_from_reg_helper(temp3, dest, dword, temp1); } @@ -333,9 +422,9 @@ static void gen_sub_direct_byte(void* dest,Bit8s imm) { gen_mov_dword_to_reg_imm(temp1, (Bit32u)dest); gen_mov_word_to_reg_helper(temp3, dest, 1, temp1); if (imm >= 0) { - cache_addd(0xe2400000 + (temp3 << 12) + (temp3 << 16) + ((Bit32s)imm)); // sub temp3, temp3, #(imm) + cache_addd( SUB_IMM(temp3, temp3, (Bit32s)imm, 0) ); // sub temp3, temp3, #(imm) } else { - cache_addd(0xe2800000 + (temp3 << 12) + (temp3 << 16) + (-((Bit32s)imm))); // add temp3, temp3, #(-imm) + cache_addd( ADD_IMM(temp3, temp3, -((Bit32s)imm), 0) ); // add temp3, temp3, #(-imm) } gen_mov_word_from_reg_helper(temp3, dest, 1, temp1); } @@ -355,7 +444,7 @@ static void gen_sub_direct_word(void* dest,Bit32u imm,bool dword) { } else { gen_mov_word_to_reg_imm(temp2, (Bit16u)imm); } - cache_addd(0xe0400000 + (temp3 << 12) + (temp3 << 16) + (temp2)); // sub temp3, temp3, temp2 + cache_addd( SUB_REG_LSL_IMM(temp3, temp3, temp2, 0) ); // sub temp3, temp3, temp2 gen_mov_word_from_reg_helper(temp3, dest, dword, temp1); } @@ -363,7 +452,7 @@ static void gen_sub_direct_word(void* dest,Bit32u imm,bool dword) { // scale_reg is scaled by scale (scale_reg*(2^scale)) and // added to dest_reg, then the immediate value is added static INLINE void gen_lea(HostReg dest_reg,HostReg scale_reg,Bitu scale,Bits imm) { - cache_addd(0xe0800000 + (dest_reg << 12) + (dest_reg << 16) + (scale_reg) + (scale << 7)); // add dest_reg, dest_reg, scale_reg, lsl #(scale) + cache_addd( ADD_REG_LSL_IMM(dest_reg, dest_reg, scale_reg, scale) ); // add dest_reg, dest_reg, scale_reg, lsl #(scale) gen_add_imm(dest_reg, imm); } @@ -372,18 +461,18 @@ static INLINE void gen_lea(HostReg dest_reg,HostReg scale_reg,Bitu scale,Bits im // then the immediate value is added static INLINE void gen_lea(HostReg dest_reg,Bitu scale,Bits imm) { if (scale) { - cache_addd(0xe1a00000 + (dest_reg << 12) + (dest_reg) + (scale << 7)); // mov dest_reg, dest_reg, lsl #(scale) + cache_addd( MOV_REG_LSL_IMM(dest_reg, dest_reg, scale) ); // mov dest_reg, dest_reg, lsl #(scale) } gen_add_imm(dest_reg, imm); } // generate a call to a parameterless function static void INLINE gen_call_function_raw(void * func) { - cache_addd(0xe5900004 + (temp1 << 12) + (HOST_pc << 16)); // ldr temp1, [pc, #4] - cache_addd(0xe2800004 + (HOST_lr << 12) + (HOST_pc << 16)); // add lr, pc, #4 - cache_addd(0xe12fff10 + (temp1)); // bx temp1 + cache_addd( LDR_IMM(temp1, HOST_pc, 4) ); // ldr temp1, [pc, #4] + cache_addd( ADD_IMM(HOST_lr, HOST_pc, 4, 0) ); // add lr, pc, #4 + cache_addd( BX(temp1) ); // bx temp1 cache_addd((Bit32u)func); // .int func - cache_addd(0xe1a00000 + (FC_RETOP << 12) + HOST_a1); // mov FC_RETOP, a1 + cache_addd( MOV_REG_LSL_IMM(FC_RETOP, HOST_a1, 0) ); // mov FC_RETOP, a1 } // generate a call to a function with paramcount parameters @@ -435,7 +524,7 @@ static void gen_jmp_ptr(void * ptr,Bits imm=0) { imm2>>=2; scale+=2; } - cache_addd(0xe2800000 + (temp3 << 12) + (temp3 << 16) + (ROTATE_SCALE(scale) << 7) + (imm2 & 0xff)); // add temp3, temp3, #((imm2 & 0xff) << scale) + cache_addd( ADD_IMM(temp3, temp3, imm2 & 0xff, ROTATE_SCALE(scale)) ); // add temp3, temp3, #((imm2 & 0xff) << scale) imm2>>=8; scale+=8; } @@ -444,31 +533,31 @@ static void gen_jmp_ptr(void * ptr,Bits imm=0) { #if (1) // (*ptr) should be word aligned if ((imm & 0x03) == 0) { - cache_addd(0xe5900000 + (temp1 << 12) + (temp3 << 16)); // ldr temp1, [temp3] + cache_addd( LDR_IMM(temp1, temp3, 0) ); // ldr temp1, [temp3] } else #endif { - cache_addd(0xe5d00000 + (temp1 << 12) + (temp3 << 16)); // ldrb temp1, [temp3] - cache_addd(0xe5d00001 + (temp2 << 12) + (temp3 << 16)); // ldrb temp2, [temp3, #1] - cache_addd(0xe1800400 + (temp1 << 12) + (temp1 << 16) + (temp2)); // orr temp1, temp1, temp2, lsl #8 - cache_addd(0xe5d00002 + (temp2 << 12) + (temp3 << 16)); // ldrb temp2, [temp3, #2] - cache_addd(0xe1800800 + (temp1 << 12) + (temp1 << 16) + (temp2)); // orr temp1, temp1, temp2, lsl #16 - cache_addd(0xe5d00003 + (temp2 << 12) + (temp3 << 16)); // ldrb temp2, [temp3, #3] - cache_addd(0xe1800c00 + (temp1 << 12) + (temp1 << 16) + (temp2)); // orr temp1, temp1, temp2, lsl #24 + cache_addd( LDRB_IMM(temp1, temp3, 0) ); // ldrb temp1, [temp3] + cache_addd( LDRB_IMM(temp2, temp3, 1) ); // ldrb temp2, [temp3, #1] + cache_addd( ORR_REG_LSL_IMM(temp1, temp1, temp2, 8) ); // orr temp1, temp1, temp2, lsl #8 + cache_addd( LDRB_IMM(temp2, temp3, 2) ); // ldrb temp2, [temp3, #2] + cache_addd( ORR_REG_LSL_IMM(temp1, temp1, temp2, 16) ); // orr temp1, temp1, temp2, lsl #16 + cache_addd( LDRB_IMM(temp2, temp3, 3) ); // ldrb temp2, [temp3, #3] + cache_addd( ORR_REG_LSL_IMM(temp1, temp1, temp2, 24) ); // orr temp1, temp1, temp2, lsl #24 } - cache_addd(0xe12fff10 + (temp1)); // bx temp1 + cache_addd( BX(temp1) ); // bx temp1 } // short conditional jump (+-127 bytes) if register is zero // the destination is set by gen_fill_branch() later static Bit32u gen_create_branch_on_zero(HostReg reg,bool dword) { if (dword) { - cache_addd(0xe3500000 + (reg << 16)); // cmp reg, #0 + cache_addd( CMP_IMM(reg, 0, 0) ); // cmp reg, #0 } else { - cache_addd(0xe1b00800 + (temp1 << 12) + (reg)); // movs temp1, reg, lsl #16 + cache_addd( MOVS_REG_LSL_IMM(temp1, reg, 16) ); // movs temp1, reg, lsl #16 } - cache_addd(0x0a000000); // beq j + cache_addd( BEQ_FWD(0) ); // beq j return ((Bit32u)cache.pos-4); } @@ -476,11 +565,11 @@ static Bit32u gen_create_branch_on_zero(HostReg reg,bool dword) { // the destination is set by gen_fill_branch() later static Bit32u gen_create_branch_on_nonzero(HostReg reg,bool dword) { if (dword) { - cache_addd(0xe3500000 + (reg << 16)); // cmp reg, #0 + cache_addd( CMP_IMM(reg, 0, 0) ); // cmp reg, #0 } else { - cache_addd(0xe1b00800 + (temp1 << 12) + (reg)); // movs temp1, reg, lsl #16 + cache_addd( MOVS_REG_LSL_IMM(temp1, reg, 16) ); // movs temp1, reg, lsl #16 } - cache_addd(0x1a000000); // bne j + cache_addd( BNE_FWD(0) ); // bne j return ((Bit32u)cache.pos-4); } @@ -499,13 +588,13 @@ static void INLINE gen_fill_branch(DRC_PTR_SIZE_IM data) { // for isdword==false the lowest 8bit of the register are tested static Bit32u gen_create_branch_long_nonzero(HostReg reg,bool isdword) { if (isdword) { - cache_addd(0xe3500000 + (reg << 16)); // cmp reg, #0 + cache_addd( CMP_IMM(reg, 0, 0) ); // cmp reg, #0 } else { - cache_addd(0xe31000ff + (reg << 16)); // tst reg, #0xff + cache_addd( TST_IMM(reg, 0xff, 0) ); // tst reg, #0xff } - cache_addd(0x0a000002); // beq nobranch - cache_addd(0xe5900000 + (temp1 << 12) + (HOST_pc << 16)); // ldr temp1, [pc, #0] - cache_addd(0xe12fff10 + (temp1)); // bx temp1 + cache_addd( BEQ_FWD(8) ); // beq nobranch (pc +8) + cache_addd( LDR_IMM(temp1, HOST_pc, 0) ); // ldr temp1, [pc, #0] + cache_addd( BX(temp1) ); // bx temp1 cache_addd(0); // fill j // nobranch: return ((Bit32u)cache.pos-4); @@ -513,10 +602,10 @@ static Bit32u gen_create_branch_long_nonzero(HostReg reg,bool isdword) { // compare 32bit-register against zero and jump if value less/equal than zero static Bit32u gen_create_branch_long_leqzero(HostReg reg) { - cache_addd(0xe3500000 + (reg << 16)); // cmp reg, #0 - cache_addd(0xca000002); // bgt nobranch - cache_addd(0xe5900000 + (temp1 << 12) + (HOST_pc << 16)); // ldr temp1, [pc, #0] - cache_addd(0xe12fff10 + (temp1)); // bx temp1 + cache_addd( CMP_IMM(reg, 0, 0) ); // cmp reg, #0 + cache_addd( BGT_FWD(8) ); // bgt nobranch (pc+8) + cache_addd( LDR_IMM(temp1, HOST_pc, 0) ); // ldr temp1, [pc, #0] + cache_addd( BX(temp1) ); // bx temp1 cache_addd(0); // fill j // nobranch: return ((Bit32u)cache.pos-4); @@ -533,22 +622,26 @@ static void gen_run_code(void) { cache_addd(0xe92d0df0); // stmfd sp!, {v1-v5,v7,v8} // adr: 8 - cache_addd(0xe5900000 + (FC_SEGS_ADDR << 12) + (HOST_pc << 16) + (64 - (8 + 8))); // ldr FC_SEGS_ADDR, [pc, #(&Segs)] + cache_addd( LDR_IMM(FC_SEGS_ADDR, HOST_pc, 64 - (8 + 8)) ); // ldr FC_SEGS_ADDR, [pc, #(&Segs)] // adr: 12 - cache_addd(0xe5900000 + (FC_REGS_ADDR << 12) + (HOST_pc << 16) + (68 - (12 + 8))); // ldr FC_REGS_ADDR, [pc, #(&cpu_regs)] - cache_addd(0xe28fe004); // add lr, pc, #4 + cache_addd( LDR_IMM(FC_REGS_ADDR, HOST_pc, 68 - (12 + 8)) ); // ldr FC_REGS_ADDR, [pc, #(&cpu_regs)] + + cache_addd( ADD_IMM(HOST_lr, HOST_pc, 4, 0) ); // add lr, pc, #4 cache_addd(0xe92d4000); // stmfd sp!, {lr} - cache_addd(0xe12fff10); // bx r0 + cache_addd( BX(HOST_r0) ); // bx r0 + cache_addd(0xe8bd0df0); // ldmfd sp!, {v1-v5,v7,v8} + cache_addd(0xe8bd4000); // ldmfd sp!, {lr} - cache_addd(0xe12fff1e); // bx lr + cache_addd( BX(HOST_lr) ); // bx lr + // fill up to 64 bytes - cache_addd(0xe1a00000); // nop - cache_addd(0xe1a00000); // nop - cache_addd(0xe1a00000); // nop - cache_addd(0xe1a00000); // nop - cache_addd(0xe1a00000); // nop - cache_addd(0xe1a00000); // nop + cache_addd( NOP ); // nop + cache_addd( NOP ); // nop + cache_addd( NOP ); // nop + cache_addd( NOP ); // nop + cache_addd( NOP ); // nop + cache_addd( NOP ); // nop // adr: 64 cache_addd((Bit32u)&Segs); // address of "Segs" @@ -558,9 +651,9 @@ static void gen_run_code(void) { // return from a function static void gen_return_function(void) { - cache_addd(0xe1a00000 + (HOST_a1 << 12) + FC_RETOP); // mov a1, FC_RETOP + cache_addd( MOV_REG_LSL_IMM(HOST_a1, FC_RETOP, 0) ); // mov a1, FC_RETOP cache_addd(0xe8bd4000); // ldmfd sp!, {lr} - cache_addd(0xe12fff1e); // bx lr + cache_addd( BX(HOST_lr) ); // bx lr } #ifdef DRC_FLAGS_INVALIDATION @@ -574,32 +667,32 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { case t_ADDb: case t_ADDw: case t_ADDd: - *(Bit32u*)pos=0xe0800000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (HOST_a2); // add FC_RETOP, a1, a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=ADD_REG_LSL_IMM(FC_RETOP, HOST_a1, HOST_a2, 0); // add FC_RETOP, a1, a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_ORb: case t_ORw: case t_ORd: - *(Bit32u*)pos=0xe1800000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (HOST_a2); // orr FC_RETOP, a1, a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=ORR_REG_LSL_IMM(FC_RETOP, HOST_a1, HOST_a2, 0); // orr FC_RETOP, a1, a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_ANDb: case t_ANDw: case t_ANDd: - *(Bit32u*)pos=0xe0000000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (HOST_a2); // and FC_RETOP, a1, a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=AND_REG_LSL_IMM(FC_RETOP, HOST_a1, HOST_a2, 0); // and FC_RETOP, a1, a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_SUBb: case t_SUBw: case t_SUBd: - *(Bit32u*)pos=0xe0400000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (HOST_a2); // sub FC_RETOP, a1, a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=SUB_REG_LSL_IMM(FC_RETOP, HOST_a1, HOST_a2, 0); // sub FC_RETOP, a1, a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_XORb: case t_XORw: case t_XORd: - *(Bit32u*)pos=0xe0200000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (HOST_a2); // eor FC_RETOP, a1, a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=EOR_REG_LSL_IMM(FC_RETOP, HOST_a1, HOST_a2, 0); // eor FC_RETOP, a1, a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_CMPb: case t_CMPw: @@ -607,106 +700,106 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { case t_TESTb: case t_TESTw: case t_TESTd: - *(Bit32u*)pos=0xea000000 + (3); // b (pc+3*4) + *(Bit32u*)pos=B_FWD(12); // b (pc+3*4) break; case t_INCb: case t_INCw: case t_INCd: - *(Bit32u*)pos=0xe2800000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (1); // add FC_RETOP, a1, #1 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=ADD_IMM(FC_RETOP, HOST_a1, 1, 0); // add FC_RETOP, a1, #1 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_DECb: case t_DECw: case t_DECd: - *(Bit32u*)pos=0xe2400000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (1); // sub FC_RETOP, a1, #1 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=SUB_IMM(FC_RETOP, HOST_a1, 1, 0); // sub FC_RETOP, a1, #1 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_SHLb: case t_SHLw: case t_SHLd: - *(Bit32u*)pos=0xe1a00010 + (FC_RETOP << 12) + (HOST_a1) + (HOST_a2 << 8); // mov FC_RETOP, a1, lsl a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=MOV_REG_LSL_REG(FC_RETOP, HOST_a1, HOST_a2); // mov FC_RETOP, a1, lsl a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_SHRb: - *(Bit32u*)pos=0xe2000000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (0xff); // and FC_RETOP, a1, #0xff - *(Bit32u*)(pos+4)=0xe1a00030 + (FC_RETOP << 12) + (FC_RETOP) + (HOST_a2 << 8); // mov FC_RETOP, FC_RETOP, lsr a2 - *(Bit32u*)(pos+8)=0xe1a00000; // nop - *(Bit32u*)(pos+12)=0xe1a00000; // nop - *(Bit32u*)(pos+16)=0xe1a00000; // nop + *(Bit32u*)pos=AND_IMM(FC_RETOP, HOST_a1, 0xff, 0); // and FC_RETOP, a1, #0xff + *(Bit32u*)(pos+4)=MOV_REG_LSR_REG(FC_RETOP, FC_RETOP, HOST_a2); // mov FC_RETOP, FC_RETOP, lsr a2 + *(Bit32u*)(pos+8)=NOP; // nop + *(Bit32u*)(pos+12)=NOP; // nop + *(Bit32u*)(pos+16)=NOP; // nop break; case t_SHRw: - *(Bit32u*)pos=0xe1a00000 + (FC_RETOP << 12) + (HOST_a1) + (16 << 7); // mov FC_RETOP, a1, lsl #16 - *(Bit32u*)(pos+4)=0xe1a00020 + (FC_RETOP << 12) + (FC_RETOP) + (16 << 7); // mov FC_RETOP, FC_RETOP, lsr #16 - *(Bit32u*)(pos+8)=0xe1a00030 + (FC_RETOP << 12) + (FC_RETOP) + (HOST_a2 << 8); // mov FC_RETOP, FC_RETOP, lsr a2 - *(Bit32u*)(pos+12)=0xe1a00000; // nop - *(Bit32u*)(pos+16)=0xe1a00000; // nop + *(Bit32u*)pos=MOV_REG_LSL_IMM(FC_RETOP, HOST_a1, 16); // mov FC_RETOP, a1, lsl #16 + *(Bit32u*)(pos+4)=MOV_REG_LSR_IMM(FC_RETOP, FC_RETOP, 16); // mov FC_RETOP, FC_RETOP, lsr #16 + *(Bit32u*)(pos+8)=MOV_REG_LSR_REG(FC_RETOP, FC_RETOP, HOST_a2); // mov FC_RETOP, FC_RETOP, lsr a2 + *(Bit32u*)(pos+12)=NOP; // nop + *(Bit32u*)(pos+16)=NOP; // nop break; case t_SHRd: - *(Bit32u*)pos=0xe1a00030 + (FC_RETOP << 12) + (HOST_a1) + (HOST_a2 << 8); // mov FC_RETOP, a1, lsr a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=MOV_REG_LSR_REG(FC_RETOP, HOST_a1, HOST_a2); // mov FC_RETOP, a1, lsr a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_SARb: - *(Bit32u*)pos=0xe1a00000 + (FC_RETOP << 12) + (HOST_a1) + (24 << 7); // mov FC_RETOP, a1, lsl #24 - *(Bit32u*)(pos+4)=0xe1a00040 + (FC_RETOP << 12) + (FC_RETOP) + (24 << 7); // mov FC_RETOP, FC_RETOP, asr #24 - *(Bit32u*)(pos+8)=0xe1a00050 + (FC_RETOP << 12) + (FC_RETOP) + (HOST_a2 << 8); // mov FC_RETOP, FC_RETOP, asr a2 - *(Bit32u*)(pos+12)=0xe1a00000; // nop - *(Bit32u*)(pos+16)=0xe1a00000; // nop + *(Bit32u*)pos=MOV_REG_LSL_IMM(FC_RETOP, HOST_a1, 24); // mov FC_RETOP, a1, lsl #24 + *(Bit32u*)(pos+4)=MOV_REG_ASR_IMM(FC_RETOP, FC_RETOP, 24); // mov FC_RETOP, FC_RETOP, asr #24 + *(Bit32u*)(pos+8)=MOV_REG_ASR_REG(FC_RETOP, FC_RETOP, HOST_a2); // mov FC_RETOP, FC_RETOP, asr a2 + *(Bit32u*)(pos+12)=NOP; // nop + *(Bit32u*)(pos+16)=NOP; // nop break; case t_SARw: - *(Bit32u*)pos=0xe1a00000 + (FC_RETOP << 12) + (HOST_a1) + (16 << 7); // mov FC_RETOP, a1, lsl #16 - *(Bit32u*)(pos+4)=0xe1a00040 + (FC_RETOP << 12) + (FC_RETOP) + (16 << 7); // mov FC_RETOP, FC_RETOP, asr #16 - *(Bit32u*)(pos+8)=0xe1a00050 + (FC_RETOP << 12) + (FC_RETOP) + (HOST_a2 << 8); // mov FC_RETOP, FC_RETOP, asr a2 - *(Bit32u*)(pos+12)=0xe1a00000; // nop - *(Bit32u*)(pos+16)=0xe1a00000; // nop + *(Bit32u*)pos=MOV_REG_LSL_IMM(FC_RETOP, HOST_a1, 16); // mov FC_RETOP, a1, lsl #16 + *(Bit32u*)(pos+4)=MOV_REG_ASR_IMM(FC_RETOP, FC_RETOP, 16); // mov FC_RETOP, FC_RETOP, asr #16 + *(Bit32u*)(pos+8)=MOV_REG_ASR_REG(FC_RETOP, FC_RETOP, HOST_a2); // mov FC_RETOP, FC_RETOP, asr a2 + *(Bit32u*)(pos+12)=NOP; // nop + *(Bit32u*)(pos+16)=NOP; // nop break; case t_SARd: - *(Bit32u*)pos=0xe1a00050 + (FC_RETOP << 12) + (HOST_a1) + (HOST_a2 << 8); // mov FC_RETOP, a1, asr a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=MOV_REG_ASR_REG(FC_RETOP, HOST_a1, HOST_a2); // mov FC_RETOP, a1, asr a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_RORb: - *(Bit32u*)pos=0xe1a00000 + (FC_RETOP << 12) + (HOST_a1) + (24 << 7); // mov FC_RETOP, a1, lsl #24 - *(Bit32u*)(pos+4)=0xe1800020 + (FC_RETOP << 12) + (FC_RETOP << 16) + (FC_RETOP) + (8 << 7); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #8 - *(Bit32u*)(pos+8)=0xe1800020 + (FC_RETOP << 12) + (FC_RETOP << 16) + (FC_RETOP) + (16 << 7); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #16 - *(Bit32u*)(pos+12)=0xe1a00070 + (FC_RETOP << 12) + (FC_RETOP) + (HOST_a2 << 8); // mov FC_RETOP, FC_RETOP, ror a2 - *(Bit32u*)(pos+16)=0xe1a00000; // nop + *(Bit32u*)pos=MOV_REG_LSL_IMM(FC_RETOP, HOST_a1, 24); // mov FC_RETOP, a1, lsl #24 + *(Bit32u*)(pos+4)=ORR_REG_LSR_IMM(FC_RETOP, FC_RETOP, FC_RETOP, 8); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #8 + *(Bit32u*)(pos+8)=ORR_REG_LSR_IMM(FC_RETOP, FC_RETOP, FC_RETOP, 16); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #16 + *(Bit32u*)(pos+12)=MOV_REG_ROR_REG(FC_RETOP, FC_RETOP, HOST_a2); // mov FC_RETOP, FC_RETOP, ror a2 + *(Bit32u*)(pos+16)=NOP; // nop break; case t_RORw: - *(Bit32u*)pos=0xe1a00000 + (FC_RETOP << 12) + (HOST_a1) + (16 << 7); // mov FC_RETOP, a1, lsl #16 - *(Bit32u*)(pos+4)=0xe1800020 + (FC_RETOP << 12) + (FC_RETOP << 16) + (FC_RETOP) + (16 << 7); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #16 - *(Bit32u*)(pos+8)=0xe1a00070 + (FC_RETOP << 12) + (FC_RETOP) + (HOST_a2 << 8); // mov FC_RETOP, FC_RETOP, ror a2 - *(Bit32u*)(pos+12)=0xe1a00000; // nop - *(Bit32u*)(pos+16)=0xe1a00000; // nop + *(Bit32u*)pos=MOV_REG_LSL_IMM(FC_RETOP, HOST_a1, 16); // mov FC_RETOP, a1, lsl #16 + *(Bit32u*)(pos+4)=ORR_REG_LSR_IMM(FC_RETOP, FC_RETOP, FC_RETOP, 16); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #16 + *(Bit32u*)(pos+8)=MOV_REG_ROR_REG(FC_RETOP, FC_RETOP, HOST_a2); // mov FC_RETOP, FC_RETOP, ror a2 + *(Bit32u*)(pos+12)=NOP; // nop + *(Bit32u*)(pos+16)=NOP; // nop break; case t_RORd: - *(Bit32u*)pos=0xe1a00070 + (FC_RETOP << 12) + (HOST_a1) + (HOST_a2 << 8); // mov FC_RETOP, a1, ror a2 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=MOV_REG_ROR_REG(FC_RETOP, HOST_a1, HOST_a2); // mov FC_RETOP, a1, ror a2 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; case t_ROLb: - *(Bit32u*)pos=0xe1a00000 + (FC_RETOP << 12) + (HOST_a1) + (24 << 7); // mov FC_RETOP, a1, lsl #24 - *(Bit32u*)(pos+4)=0xe2600000 + (HOST_a2 << 12) + (HOST_a2 << 16) + (32); // rsb a2, a2, #32 - *(Bit32u*)(pos+8)=0xe1800020 + (FC_RETOP << 12) + (FC_RETOP << 16) + (FC_RETOP) + (8 << 7); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #8 - *(Bit32u*)(pos+12)=0xe1800020 + (FC_RETOP << 12) + (FC_RETOP << 16) + (FC_RETOP) + (16 << 7); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #16 - *(Bit32u*)(pos+16)=0xe1a00070 + (FC_RETOP << 12) + (FC_RETOP) + (HOST_a2 << 8); // mov FC_RETOP, FC_RETOP, ror a2 + *(Bit32u*)pos=MOV_REG_LSL_IMM(FC_RETOP, HOST_a1, 24); // mov FC_RETOP, a1, lsl #24 + *(Bit32u*)(pos+4)=RSB_IMM(HOST_a2, HOST_a2, 32, 0); // rsb a2, a2, #32 + *(Bit32u*)(pos+8)=ORR_REG_LSR_IMM(FC_RETOP, FC_RETOP, FC_RETOP, 8); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #8 + *(Bit32u*)(pos+12)=ORR_REG_LSR_IMM(FC_RETOP, FC_RETOP, FC_RETOP, 16); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #16 + *(Bit32u*)(pos+16)=MOV_REG_ROR_REG(FC_RETOP, FC_RETOP, HOST_a2); // mov FC_RETOP, FC_RETOP, ror a2 break; case t_ROLw: - *(Bit32u*)pos=0xe1a00000 + (FC_RETOP << 12) + (HOST_a1) + (16 << 7); // mov FC_RETOP, a1, lsl #16 - *(Bit32u*)(pos+4)=0xe2600000 + (HOST_a2 << 12) + (HOST_a2 << 16) + (32); // rsb a2, a2, #32 - *(Bit32u*)(pos+8)=0xe1800020 + (FC_RETOP << 12) + (FC_RETOP << 16) + (FC_RETOP) + (16 << 7); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #16 - *(Bit32u*)(pos+12)=0xe1a00070 + (FC_RETOP << 12) + (FC_RETOP) + (HOST_a2 << 8); // mov FC_RETOP, FC_RETOP, ror a2 - *(Bit32u*)(pos+16)=0xe1a00000; // nop + *(Bit32u*)pos=MOV_REG_LSL_IMM(FC_RETOP, HOST_a1, 16); // mov FC_RETOP, a1, lsl #16 + *(Bit32u*)(pos+4)=RSB_IMM(HOST_a2, HOST_a2, 32, 0); // rsb a2, a2, #32 + *(Bit32u*)(pos+8)=ORR_REG_LSR_IMM(FC_RETOP, FC_RETOP, FC_RETOP, 16); // orr FC_RETOP, FC_RETOP, FC_RETOP, lsr #16 + *(Bit32u*)(pos+12)=MOV_REG_ROR_REG(FC_RETOP, FC_RETOP, HOST_a2); // mov FC_RETOP, FC_RETOP, ror a2 + *(Bit32u*)(pos+16)=NOP; // nop break; case t_ROLd: - *(Bit32u*)pos=0xe2600000 + (HOST_a2 << 12) + (HOST_a2 << 16) + (32); // rsb a2, a2, #32 - *(Bit32u*)(pos+4)=0xe1a00070 + (FC_RETOP << 12) + (HOST_a1) + (HOST_a2 << 8); // mov FC_RETOP, a1, ror a2 - *(Bit32u*)(pos+8)=0xe1a00000; // nop - *(Bit32u*)(pos+12)=0xe1a00000; // nop - *(Bit32u*)(pos+16)=0xe1a00000; // nop + *(Bit32u*)pos=RSB_IMM(HOST_a2, HOST_a2, 32, 0); // rsb a2, a2, #32 + *(Bit32u*)(pos+4)=MOV_REG_ROR_REG(FC_RETOP, HOST_a1, HOST_a2); // mov FC_RETOP, a1, ror a2 + *(Bit32u*)(pos+8)=NOP; // nop + *(Bit32u*)(pos+12)=NOP; // nop + *(Bit32u*)(pos+16)=NOP; // nop break; case t_NEGb: case t_NEGw: case t_NEGd: - *(Bit32u*)pos=0xe2600000 + (FC_RETOP << 12) + (HOST_a1 << 16) + (0); // rsb FC_RETOP, a1, #0 - *(Bit32u*)(pos+4)=0xea000000 + (2); // b (pc+2*4) + *(Bit32u*)pos=RSB_IMM(FC_RETOP, HOST_a1, 0, 0); // rsb FC_RETOP, a1, #0 + *(Bit32u*)(pos+4)=B_FWD(8); // b (pc+2*4) break; default: *(Bit32u*)(pos+12)=(Bit32u)fct_ptr; // simple_func @@ -721,24 +814,23 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { static void cache_block_before_close(void) { } - #ifdef DRC_USE_SEGS_ADDR // mov 16bit value from Segs[index] into dest_reg using FC_SEGS_ADDR (index modulo 2 must be zero) // 16bit moves may destroy the upper 16bit of the destination register static void gen_mov_seg16_to_reg(HostReg dest_reg,Bitu index) { - cache_addd(0xe1d000b0 + (dest_reg << 12) + (FC_SEGS_ADDR << 16) + ((index & 0xf0) << 4) + (index & 0x0f)); // ldrh dest_reg, [FC_SEGS_ADDR, #index] + cache_addd( LDRH_IMM(dest_reg, FC_SEGS_ADDR, index) ); // ldrh dest_reg, [FC_SEGS_ADDR, #index] } // mov 32bit value from Segs[index] into dest_reg using FC_SEGS_ADDR (index modulo 4 must be zero) static void gen_mov_seg32_to_reg(HostReg dest_reg,Bitu index) { - cache_addd(0xe5900000 + (dest_reg << 12) + (FC_SEGS_ADDR << 16) + (index)); // ldr dest_reg, [FC_SEGS_ADDR, #index] + cache_addd( LDR_IMM(dest_reg, FC_SEGS_ADDR, index) ); // ldr dest_reg, [FC_SEGS_ADDR, #index] } // add a 32bit value from Segs[index] to a full register using FC_SEGS_ADDR (index modulo 4 must be zero) static void gen_add_seg32_to_reg(HostReg reg,Bitu index) { - cache_addd(0xe5900000 + (temp1 << 12) + (FC_SEGS_ADDR << 16) + (index)); // ldr temp1, [FC_SEGS_ADDR, #index] - cache_addd(0xe0800000 + (reg << 12) + (reg << 16) + (temp1)); // add reg, reg, temp1 + cache_addd( LDR_IMM(temp1, FC_SEGS_ADDR, index) ); // ldr temp1, [FC_SEGS_ADDR, #index] + cache_addd( ADD_REG_LSL_IMM(reg, reg, temp1, 0) ); // add reg, reg, temp1 } #endif @@ -748,21 +840,21 @@ static void gen_add_seg32_to_reg(HostReg reg,Bitu index) { // mov 16bit value from cpu_regs[index] into dest_reg using FC_REGS_ADDR (index modulo 2 must be zero) // 16bit moves may destroy the upper 16bit of the destination register static void gen_mov_regval16_to_reg(HostReg dest_reg,Bitu index) { - cache_addd(0xe1d000b0 + (dest_reg << 12) + (FC_REGS_ADDR << 16) + ((index & 0xf0) << 4) + (index & 0x0f)); // ldrh dest_reg, [FC_REGS_ADDR, #index] + cache_addd( LDRH_IMM(dest_reg, FC_REGS_ADDR, index) ); // ldrh dest_reg, [FC_REGS_ADDR, #index] } // mov 32bit value from cpu_regs[index] into dest_reg using FC_REGS_ADDR (index modulo 4 must be zero) static void gen_mov_regval32_to_reg(HostReg dest_reg,Bitu index) { - cache_addd(0xe5900000 + (dest_reg << 12) + (FC_REGS_ADDR << 16) + (index)); // ldr dest_reg, [FC_REGS_ADDR, #index] + cache_addd( LDR_IMM(dest_reg, FC_REGS_ADDR, index) ); // ldr dest_reg, [FC_REGS_ADDR, #index] } // move a 32bit (dword==true) or 16bit (dword==false) value from cpu_regs[index] into dest_reg using FC_REGS_ADDR (if dword==true index modulo 4 must be zero) (if dword==false index modulo 2 must be zero) // 16bit moves may destroy the upper 16bit of the destination register static void gen_mov_regword_to_reg(HostReg dest_reg,Bitu index,bool dword) { if (dword) { - cache_addd(0xe5900000 + (dest_reg << 12) + (FC_REGS_ADDR << 16) + (index)); // ldr dest_reg, [FC_REGS_ADDR, #index] + cache_addd( LDR_IMM(dest_reg, FC_REGS_ADDR, index) ); // ldr dest_reg, [FC_REGS_ADDR, #index] } else { - cache_addd(0xe1d000b0 + (dest_reg << 12) + (FC_REGS_ADDR << 16) + ((index & 0xf0) << 4) + (index & 0x0f)); // ldrh dest_reg, [FC_REGS_ADDR, #index] + cache_addd( LDRH_IMM(dest_reg, FC_REGS_ADDR, index) ); // ldrh dest_reg, [FC_REGS_ADDR, #index] } } @@ -771,7 +863,7 @@ static void gen_mov_regword_to_reg(HostReg dest_reg,Bitu index,bool dword) { // this function does not use FC_OP1/FC_OP2 as dest_reg as these // registers might not be directly byte-accessible on some architectures static void gen_mov_regbyte_to_reg_low(HostReg dest_reg,Bitu index) { - cache_addd(0xe5d00000 + (dest_reg << 12) + (FC_REGS_ADDR << 16) + (index)); // ldrb dest_reg, [FC_REGS_ADDR, #index] + cache_addd( LDRB_IMM(dest_reg, FC_REGS_ADDR, index) ); // ldrb dest_reg, [FC_REGS_ADDR, #index] } // move an 8bit value from cpu_regs[index] into dest_reg using FC_REGS_ADDR @@ -779,39 +871,39 @@ static void gen_mov_regbyte_to_reg_low(HostReg dest_reg,Bitu index) { // this function can use FC_OP1/FC_OP2 as dest_reg which are // not directly byte-accessible on some architectures static void INLINE gen_mov_regbyte_to_reg_low_canuseword(HostReg dest_reg,Bitu index) { - cache_addd(0xe5d00000 + (dest_reg << 12) + (FC_REGS_ADDR << 16) + (index)); // ldrb dest_reg, [FC_REGS_ADDR, #index] + cache_addd( LDRB_IMM(dest_reg, FC_REGS_ADDR, index) ); // ldrb dest_reg, [FC_REGS_ADDR, #index] } // add a 32bit value from cpu_regs[index] to a full register using FC_REGS_ADDR (index modulo 4 must be zero) static void gen_add_regval32_to_reg(HostReg reg,Bitu index) { - cache_addd(0xe5900000 + (temp2 << 12) + (FC_REGS_ADDR << 16) + (index)); // ldr temp2, [FC_REGS_ADDR, #index] - cache_addd(0xe0800000 + (reg << 12) + (reg << 16) + (temp2)); // add reg, reg, temp2 + cache_addd( LDR_IMM(temp2, FC_REGS_ADDR, index) ); // ldr temp2, [FC_REGS_ADDR, #index] + cache_addd( ADD_REG_LSL_IMM(reg, reg, temp2, 0) ); // add reg, reg, temp2 } // move 16bit of register into cpu_regs[index] using FC_REGS_ADDR (index modulo 2 must be zero) static void gen_mov_regval16_from_reg(HostReg src_reg,Bitu index) { - cache_addd(0xe1c000b0 + (src_reg << 12) + (FC_REGS_ADDR << 16) + ((index & 0xf0) << 4) + (index & 0x0f)); // strh src_reg, [FC_REGS_ADDR, #index] + cache_addd( STRH_IMM(src_reg, FC_REGS_ADDR, index) ); // strh src_reg, [FC_REGS_ADDR, #index] } // move 32bit of register into cpu_regs[index] using FC_REGS_ADDR (index modulo 4 must be zero) static void gen_mov_regval32_from_reg(HostReg src_reg,Bitu index) { - cache_addd(0xe5800000 + (src_reg << 12) + (FC_REGS_ADDR << 16) + (index)); // str src_reg, [FC_REGS_ADDR, #index] + cache_addd( STR_IMM(src_reg, FC_REGS_ADDR, index) ); // str src_reg, [FC_REGS_ADDR, #index] } // move 32bit (dword==true) or 16bit (dword==false) of a register into cpu_regs[index] using FC_REGS_ADDR (if dword==true index modulo 4 must be zero) (if dword==false index modulo 2 must be zero) static void gen_mov_regword_from_reg(HostReg src_reg,Bitu index,bool dword) { if (dword) { - cache_addd(0xe5800000 + (src_reg << 12) + (FC_REGS_ADDR << 16) + (index)); // str src_reg, [FC_REGS_ADDR, #index] + cache_addd( STR_IMM(src_reg, FC_REGS_ADDR, index) ); // str src_reg, [FC_REGS_ADDR, #index] } else { - cache_addd(0xe1c000b0 + (src_reg << 12) + (FC_REGS_ADDR << 16) + ((index & 0xf0) << 4) + (index & 0x0f)); // strh src_reg, [FC_REGS_ADDR, #index] + cache_addd( STRH_IMM(src_reg, FC_REGS_ADDR, index) ); // strh src_reg, [FC_REGS_ADDR, #index] } } // move the lowest 8bit of a register into cpu_regs[index] using FC_REGS_ADDR static void gen_mov_regbyte_from_reg_low(HostReg src_reg,Bitu index) { - cache_addd(0xe5c00000 + (src_reg << 12) + (FC_REGS_ADDR << 16) + (index)); // strb src_reg, [FC_REGS_ADDR, #index] + cache_addd( STRB_IMM(src_reg, FC_REGS_ADDR, index) ); // strb src_reg, [FC_REGS_ADDR, #index] } #endif diff --git a/src/cpu/core_dynrec/risc_armv4le-thumb-iw.h b/src/cpu/core_dynrec/risc_armv4le-thumb-iw.h index 01ebb28..617df4a 100644 --- a/src/cpu/core_dynrec/risc_armv4le-thumb-iw.h +++ b/src/cpu/core_dynrec/risc_armv4le-thumb-iw.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2002-2008 The DOSBox Team + * Copyright (C) 2002-2009 The DOSBox Team * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,7 +16,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $Id: risc_armv4le-thumb-iw.h,v 1.2 2008/09/19 16:48:02 c2woody Exp $ */ +/* $Id: risc_armv4le-thumb-iw.h,v 1.3 2009/05/16 21:52:47 c2woody Exp $ */ /* ARMv4 (little endian) backend by M-HT (thumb version with data pool, requires -mthumb-interwork switch when compiling dosbox) */ @@ -64,6 +64,97 @@ #endif +// instruction encodings + +// move +// mov dst, #imm @ 0 <= imm <= 255 +#define MOV_IMM(dst, imm) (0x2000 + ((dst) << 8) + (imm) ) +// mov dst, src +#define MOV_REG(dst, src) ADD_IMM3(dst, src, 0) +// mov dst, src +#define MOV_LO_HI(dst, src) (0x4640 + (dst) + (((src) - HOST_r8) << 3) ) +// mov dst, src +#define MOV_HI_LO(dst, src) (0x4680 + ((dst) - HOST_r8) + ((src) << 3) ) + +// arithmetic +// add dst, src, #imm @ 0 <= imm <= 7 +#define ADD_IMM3(dst, src, imm) (0x1c00 + (dst) + ((src) << 3) + ((imm) << 6) ) +// add dst, #imm @ 0 <= imm <= 255 +#define ADD_IMM8(dst, imm) (0x3000 + ((dst) << 8) + (imm) ) +// add dst, src1, src2 +#define ADD_REG(dst, src1, src2) (0x1800 + (dst) + ((src1) << 3) + ((src2) << 6) ) +// add dst, src +#define ADD_LO_HI(dst, src) (0x4440 + (dst) + (((src) - HOST_r8) << 3) ) +// add dst, pc, #imm @ 0 <= imm < 1024 & imm mod 4 = 0 +#define ADD_LO_PC_IMM(dst, imm) (0xa000 + ((dst) << 8) + ((imm) >> 2) ) +// sub dst, src1, src2 +#define SUB_REG(dst, src1, src2) (0x1a00 + (dst) + ((src1) << 3) + ((src2) << 6) ) +// sub dst, src, #imm @ 0 <= imm <= 7 +#define SUB_IMM3(dst, src, imm) (0x1e00 + (dst) + ((src) << 3) + ((imm) << 6) ) +// sub dst, #imm @ 0 <= imm <= 255 +#define SUB_IMM8(dst, imm) (0x3800 + ((dst) << 8) + (imm) ) +// neg dst, src +#define NEG(dst, src) (0x4240 + (dst) + ((src) << 3) ) +// cmp dst, #imm @ 0 <= imm <= 255 +#define CMP_IMM(dst, imm) (0x2800 + ((dst) << 8) + (imm) ) +// nop +#define NOP (0x46c0) + +// logical +// and dst, src +#define AND(dst, src) (0x4000 + (dst) + ((src) << 3) ) +// eor dst, src +#define EOR(dst, src) (0x4040 + (dst) + ((src) << 3) ) +// orr dst, src +#define ORR(dst, src) (0x4300 + (dst) + ((src) << 3) ) + +// shift/rotate +// lsl dst, src, #imm +#define LSL_IMM(dst, src, imm) (0x0000 + (dst) + ((src) << 3) + ((imm) << 6) ) +// lsl dst, reg +#define LSL_REG(dst, reg) (0x4080 + (dst) + ((reg) << 3) ) +// lsr dst, src, #imm +#define LSR_IMM(dst, src, imm) (0x0800 + (dst) + ((src) << 3) + ((imm) << 6) ) +// lsr dst, reg +#define LSR_REG(dst, reg) (0x40c0 + (dst) + ((reg) << 3) ) +// asr dst, src, #imm +#define ASR_IMM(dst, src, imm) (0x1000 + (dst) + ((src) << 3) + ((imm) << 6) ) +// asr dst, reg +#define ASR_REG(dst, reg) (0x4100 + (dst) + ((reg) << 3) ) +// ror dst, reg +#define ROR_REG(dst, reg) (0x41c0 + (dst) + ((reg) << 3) ) + +// load +// ldr reg, [addr, #imm] @ 0 <= imm < 128 & imm mod 4 = 0 +#define LDR_IMM(reg, addr, imm) (0x6800 + (reg) + ((addr) << 3) + ((imm) << 4) ) +// ldrh reg, [addr, #imm] @ 0 <= imm < 64 & imm mod 2 = 0 +#define LDRH_IMM(reg, addr, imm) (0x8800 + (reg) + ((addr) << 3) + ((imm) << 5) ) +// ldrb reg, [addr, #imm] @ 0 <= imm < 32 +#define LDRB_IMM(reg, addr, imm) (0x7800 + (reg) + ((addr) << 3) + ((imm) << 6) ) +// ldr reg, [pc, #imm] @ 0 <= imm < 1024 & imm mod 4 = 0 +#define LDR_PC_IMM(reg, imm) (0x4800 + ((reg) << 8) + ((imm) >> 2) ) + +// store +// str reg, [addr, #imm] @ 0 <= imm < 128 & imm mod 4 = 0 +#define STR_IMM(reg, addr, imm) (0x6000 + (reg) + ((addr) << 3) + ((imm) << 4) ) +// strh reg, [addr, #imm] @ 0 <= imm < 64 & imm mod 2 = 0 +#define STRH_IMM(reg, addr, imm) (0x8000 + (reg) + ((addr) << 3) + ((imm) << 5) ) +// strb reg, [addr, #imm] @ 0 <= imm < 32 +#define STRB_IMM(reg, addr, imm) (0x7000 + (reg) + ((addr) << 3) + ((imm) << 6) ) + +// branch +// beq pc+imm @ 0 <= imm < 256 & imm mod 2 = 0 +#define BEQ_FWD(imm) (0xd000 + ((imm) >> 1) ) +// bne pc+imm @ 0 <= imm < 256 & imm mod 2 = 0 +#define BNE_FWD(imm) (0xd100 + ((imm) >> 1) ) +// bgt pc+imm @ 0 <= imm < 256 & imm mod 2 = 0 +#define BGT_FWD(imm) (0xdc00 + ((imm) >> 1) ) +// b pc+imm @ 0 <= imm < 2048 & imm mod 2 = 0 +#define B_FWD(imm) (0xe000 + ((imm) >> 1) ) +// bx reg +#define BX(reg) (0x4700 + ((reg) << 3) ) + + // data pool defines #define CACHE_DATA_JUMP (2) #define CACHE_DATA_ALIGN (32) @@ -75,6 +166,7 @@ static Bit8u * cache_datapos = NULL; // position of data pool in the cache block static Bit32u cache_datasize = 0; // total size of data pool static Bit32u cache_dataindex = 0; // used size of data pool = index of free data item (in bytes) in data pool + // forwarded function static void INLINE gen_create_branch_short(void * func); @@ -185,26 +277,26 @@ static void cache_block_before_close(void) { static void gen_mov_regs(HostReg reg_dst,HostReg reg_src) { if(reg_src == reg_dst) return; cache_checkinstr(2); - cache_addw(0x1c00 + reg_dst + (reg_src << 3)); // mov reg_dst, reg_src + cache_addw( MOV_REG(reg_dst, reg_src) ); // mov reg_dst, reg_src } // move a 32bit constant value into dest_reg static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) { if ((imm & 0xffffff00) == 0) { cache_checkinstr(2); - cache_addw(0x2000 + (dest_reg << 8) + imm); // mov dest_reg, #(imm) + cache_addw( MOV_IMM(dest_reg, imm) ); // mov dest_reg, #(imm) } else if ((imm & 0xffff00ff) == 0) { cache_checkinstr(4); - cache_addw(0x2000 + (dest_reg << 8) + (imm >> 8)); // mov dest_reg, #(imm >> 8) - cache_addw(0x0000 + dest_reg + (dest_reg << 3) + (8 << 6)); // lsl dest_reg, dest_reg, #8 + cache_addw( MOV_IMM(dest_reg, imm >> 8) ); // mov dest_reg, #(imm >> 8) + cache_addw( LSL_IMM(dest_reg, dest_reg, 8) ); // lsl dest_reg, dest_reg, #8 } else if ((imm & 0xff00ffff) == 0) { cache_checkinstr(4); - cache_addw(0x2000 + (dest_reg << 8) + (imm >> 16)); // mov dest_reg, #(imm >> 16) - cache_addw(0x0000 + dest_reg + (dest_reg << 3) + (16 << 6)); // lsl dest_reg, dest_reg, #16 + cache_addw( MOV_IMM(dest_reg, imm >> 16) ); // mov dest_reg, #(imm >> 16) + cache_addw( LSL_IMM(dest_reg, dest_reg, 16) ); // lsl dest_reg, dest_reg, #16 } else if ((imm & 0x00ffffff) == 0) { cache_checkinstr(4); - cache_addw(0x2000 + (dest_reg << 8) + (imm >> 24)); // mov dest_reg, #(imm >> 24) - cache_addw(0x0000 + dest_reg + (dest_reg << 3) + (24 << 6)); // lsl dest_reg, dest_reg, #24 + cache_addw( MOV_IMM(dest_reg, imm >> 24) ); // mov dest_reg, #(imm >> 24) + cache_addw( LSL_IMM(dest_reg, dest_reg, 24) ); // lsl dest_reg, dest_reg, #24 } else { Bit32u diff; @@ -214,10 +306,10 @@ static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) { if ((diff < 1024) && ((imm & 0x03) == 0)) { if (((Bit32u)cache.pos & 0x03) == 0) { - cache_addw(0xa000 + (dest_reg << 8) + (diff >> 2)); // add dest_reg, pc, #(diff >> 2) + cache_addw( ADD_LO_PC_IMM(dest_reg, diff >> 2) ); // add dest_reg, pc, #(diff >> 2) } else { - cache_addw(0x46c0); // nop - cache_addw(0xa000 + (dest_reg << 8) + ((diff - 2) >> 2)); // add dest_reg, pc, #((diff - 2) >> 2) + cache_addw( NOP ); // nop + cache_addw( ADD_LO_PC_IMM(dest_reg, (diff - 2) >> 2) ); // add dest_reg, pc, #((diff - 2) >> 2) } } else { Bit8u *datapos; @@ -226,9 +318,9 @@ static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) { *(Bit32u*)datapos=imm; if (((Bit32u)cache.pos & 0x03) == 0) { - cache_addw(0x4800 + (dest_reg << 8) + ((datapos - (cache.pos + 4)) >> 2)); // ldr dest_reg, [pc, datapos] + cache_addw( LDR_PC_IMM(dest_reg, datapos - (cache.pos + 4)) ); // ldr dest_reg, [pc, datapos] } else { - cache_addw(0x4800 + (dest_reg << 8) + ((datapos - (cache.pos + 2)) >> 2)); // ldr dest_reg, [pc, datapos] + cache_addw( LDR_PC_IMM(dest_reg, datapos - (cache.pos + 2)) ); // ldr dest_reg, [pc, datapos] } } } @@ -241,35 +333,35 @@ static void gen_mov_word_to_reg_helper(HostReg dest_reg,void* data,bool dword,Ho if ((Bit32u)data & 3) { if ( ((Bit32u)data & 3) == 2 ) { cache_checkinstr(8); - cache_addw(0x8800 + dest_reg + (data_reg << 3)); // ldrh dest_reg, [data_reg] - cache_addw(0x8800 + templo1 + (data_reg << 3) + (2 << 5)); // ldrh templo1, [data_reg, #2] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (16 << 6)); // lsl templo1, templo1, #16 - cache_addw(0x4300 + dest_reg + (templo1 << 3)); // orr dest_reg, templo1 + cache_addw( LDRH_IMM(dest_reg, data_reg, 0) ); // ldrh dest_reg, [data_reg] + cache_addw( LDRH_IMM(templo1, data_reg, 2) ); // ldrh templo1, [data_reg, #2] + cache_addw( LSL_IMM(templo1, templo1, 16) ); // lsl templo1, templo1, #16 + cache_addw( ORR(dest_reg, templo1) ); // orr dest_reg, templo1 } else { cache_checkinstr(16); - cache_addw(0x7800 + dest_reg + (data_reg << 3)); // ldrb dest_reg, [data_reg] - cache_addw(0x1c00 + templo1 + (data_reg << 3) + (1 << 6)); // add templo1, data_reg, #1 - cache_addw(0x8800 + templo1 + (templo1 << 3)); // ldrh templo1, [templo1] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (8 << 6)); // lsl templo1, templo1, #8 - cache_addw(0x4300 + dest_reg + (templo1 << 3)); // orr dest_reg, templo1 - cache_addw(0x7800 + templo1 + (data_reg << 3) + (3 << 6)); // ldrb templo1, [data_reg, #3] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (24 << 6)); // lsl templo1, templo1, #24 - cache_addw(0x4300 + dest_reg + (templo1 << 3)); // orr dest_reg, templo1 + cache_addw( LDRB_IMM(dest_reg, data_reg, 0) ); // ldrb dest_reg, [data_reg] + cache_addw( ADD_IMM3(templo1, data_reg, 1) ); // add templo1, data_reg, #1 + cache_addw( LDRH_IMM(templo1, templo1, 0) ); // ldrh templo1, [templo1] + cache_addw( LSL_IMM(templo1, templo1, 8) ); // lsl templo1, templo1, #8 + cache_addw( ORR(dest_reg, templo1) ); // orr dest_reg, templo1 + cache_addw( LDRB_IMM(templo1, data_reg, 3) ); // ldrb templo1, [data_reg, #3] + cache_addw( LSL_IMM(templo1, templo1, 24) ); // lsl templo1, templo1, #24 + cache_addw( ORR(dest_reg, templo1) ); // orr dest_reg, templo1 } } else { cache_checkinstr(2); - cache_addw(0x6800 + dest_reg + (data_reg << 3)); // ldr dest_reg, [data_reg] + cache_addw( LDR_IMM(dest_reg, data_reg, 0) ); // ldr dest_reg, [data_reg] } } else { if ((Bit32u)data & 1) { cache_checkinstr(8); - cache_addw(0x7800 + dest_reg + (data_reg << 3)); // ldrb dest_reg, [data_reg] - cache_addw(0x7800 + templo1 + (data_reg << 3) + (1 << 6)); // ldrb templo1, [data_reg, #1] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (8 << 6)); // lsl templo1, templo1, #8 - cache_addw(0x4300 + dest_reg + (templo1 << 3)); // orr dest_reg, templo1 + cache_addw( LDRB_IMM(dest_reg, data_reg, 0) ); // ldrb dest_reg, [data_reg] + cache_addw( LDRB_IMM(templo1, data_reg, 1) ); // ldrb templo1, [data_reg, #1] + cache_addw( LSL_IMM(templo1, templo1, 8) ); // lsl templo1, templo1, #8 + cache_addw( ORR(dest_reg, templo1) ); // orr dest_reg, templo1 } else { cache_checkinstr(2); - cache_addw(0x8800 + dest_reg + (data_reg << 3)); // ldrh dest_reg, [data_reg] + cache_addw( LDRH_IMM(dest_reg, data_reg, 0) ); // ldrh dest_reg, [data_reg] } } } @@ -294,37 +386,37 @@ static void gen_mov_word_from_reg_helper(HostReg src_reg,void* dest,bool dword, if ((Bit32u)dest & 3) { if ( ((Bit32u)dest & 3) == 2 ) { cache_checkinstr(8); - cache_addw(0x8000 + src_reg + (data_reg << 3)); // strh src_reg, [data_reg] - cache_addw(0x1c00 + templo1 + (src_reg << 3)); // mov templo1, src_reg - cache_addw(0x0800 + templo1 + (templo1 << 3) + (16 << 6)); // lsr templo1, templo1, #16 - cache_addw(0x8000 + templo1 + (data_reg << 3) + (2 << 5)); // strh templo1, [data_reg, #2] + cache_addw( STRH_IMM(src_reg, data_reg, 0) ); // strh src_reg, [data_reg] + cache_addw( MOV_REG(templo1, src_reg) ); // mov templo1, src_reg + cache_addw( LSR_IMM(templo1, templo1, 16) ); // lsr templo1, templo1, #16 + cache_addw( STRH_IMM(templo1, data_reg, 2) ); // strh templo1, [data_reg, #2] } else { cache_checkinstr(20); - cache_addw(0x7000 + src_reg + (data_reg << 3)); // strb src_reg, [data_reg] - cache_addw(0x1c00 + templo1 + (src_reg << 3)); // mov templo1, src_reg - cache_addw(0x0800 + templo1 + (templo1 << 3) + (8 << 6)); // lsr templo1, templo1, #8 - cache_addw(0x7000 + templo1 + (data_reg << 3) + (1 << 6)); // strb templo1, [data_reg, #1] - cache_addw(0x1c00 + templo1 + (src_reg << 3)); // mov templo1, src_reg - cache_addw(0x0800 + templo1 + (templo1 << 3) + (16 << 6)); // lsr templo1, templo1, #16 - cache_addw(0x7000 + templo1 + (data_reg << 3) + (2 << 6)); // strb templo1, [data_reg, #2] - cache_addw(0x1c00 + templo1 + (src_reg << 3)); // mov templo1, src_reg - cache_addw(0x0800 + templo1 + (templo1 << 3) + (24 << 6)); // lsr templo1, templo1, #24 - cache_addw(0x7000 + templo1 + (data_reg << 3) + (3 << 6)); // strb templo1, [data_reg, #3] + cache_addw( STRB_IMM(src_reg, data_reg, 0) ); // strb src_reg, [data_reg] + cache_addw( MOV_REG(templo1, src_reg) ); // mov templo1, src_reg + cache_addw( LSR_IMM(templo1, templo1, 8) ); // lsr templo1, templo1, #8 + cache_addw( STRB_IMM(templo1, data_reg, 1) ); // strb templo1, [data_reg, #1] + cache_addw( MOV_REG(templo1, src_reg) ); // mov templo1, src_reg + cache_addw( LSR_IMM(templo1, templo1, 16) ); // lsr templo1, templo1, #16 + cache_addw( STRB_IMM(templo1, data_reg, 2) ); // strb templo1, [data_reg, #2] + cache_addw( MOV_REG(templo1, src_reg) ); // mov templo1, src_reg + cache_addw( LSR_IMM(templo1, templo1, 24) ); // lsr templo1, templo1, #24 + cache_addw( STRB_IMM(templo1, data_reg, 3) ); // strb templo1, [data_reg, #3] } } else { cache_checkinstr(2); - cache_addw(0x6000 + src_reg + (data_reg << 3)); // str src_reg, [data_reg] + cache_addw( STR_IMM(src_reg, data_reg, 0) ); // str src_reg, [data_reg] } } else { if ((Bit32u)dest & 1) { cache_checkinstr(8); - cache_addw(0x7000 + src_reg + (data_reg << 3)); // strb src_reg, [data_reg] - cache_addw(0x1c00 + templo1 + (src_reg << 3)); // mov templo1, src_reg - cache_addw(0x0800 + templo1 + (templo1 << 3) + (8 << 6)); // lsr templo1, templo1, #8 - cache_addw(0x7000 + templo1 + (data_reg << 3) + (1 << 6)); // strb templo1, [data_reg, #1] + cache_addw( STRB_IMM(src_reg, data_reg, 0) ); // strb src_reg, [data_reg] + cache_addw( MOV_REG(templo1, src_reg) ); // mov templo1, src_reg + cache_addw( LSR_IMM(templo1, templo1, 8) ); // lsr templo1, templo1, #8 + cache_addw( STRB_IMM(templo1, data_reg, 1) ); // strb templo1, [data_reg, #1] } else { cache_checkinstr(2); - cache_addw(0x8000 + src_reg + (data_reg << 3)); // strh src_reg, [data_reg] + cache_addw( STRH_IMM(src_reg, data_reg, 0) ); // strh src_reg, [data_reg] } } } @@ -342,7 +434,7 @@ static void gen_mov_word_from_reg(HostReg src_reg,void* dest,bool dword) { static void gen_mov_byte_to_reg_low(HostReg dest_reg,void* data) { gen_mov_dword_to_reg_imm(templo1, (Bit32u)data); cache_checkinstr(2); - cache_addw(0x7800 + dest_reg + (templo1 << 3)); // ldrb dest_reg, [templo1] + cache_addw( LDRB_IMM(dest_reg, templo1, 0) ); // ldrb dest_reg, [templo1] } // move an 8bit value from memory into dest_reg @@ -359,7 +451,7 @@ static void INLINE gen_mov_byte_to_reg_low_canuseword(HostReg dest_reg,void* dat // registers might not be directly byte-accessible on some architectures static void gen_mov_byte_to_reg_low_imm(HostReg dest_reg,Bit8u imm) { cache_checkinstr(2); - cache_addw(0x2000 + (dest_reg << 8) + imm); // mov dest_reg, #(imm) + cache_addw( MOV_IMM(dest_reg, imm) ); // mov dest_reg, #(imm) } // move an 8bit constant value into dest_reg @@ -374,7 +466,7 @@ static void INLINE gen_mov_byte_to_reg_low_imm_canuseword(HostReg dest_reg,Bit8u static void gen_mov_byte_from_reg_low(HostReg src_reg,void* dest) { gen_mov_dword_to_reg_imm(templo1, (Bit32u)dest); cache_checkinstr(2); - cache_addw(0x7000 + src_reg + (templo1 << 3)); // strb src_reg, [templo1] + cache_addw( STRB_IMM(src_reg, templo1, 0) ); // strb src_reg, [templo1] } @@ -383,12 +475,12 @@ static void gen_mov_byte_from_reg_low(HostReg src_reg,void* dest) { // the register is zero-extended (sign==false) or sign-extended (sign==true) static void gen_extend_byte(bool sign,HostReg reg) { cache_checkinstr(4); - cache_addw(0x0000 + reg + (reg << 3) + (24 << 6)); // lsl reg, reg, #24 + cache_addw( LSL_IMM(reg, reg, 24) ); // lsl reg, reg, #24 if (sign) { - cache_addw(0x1000 + reg + (reg << 3) + (24 << 6)); // asr reg, reg, #24 + cache_addw( ASR_IMM(reg, reg, 24) ); // asr reg, reg, #24 } else { - cache_addw(0x0800 + reg + (reg << 3) + (24 << 6)); // lsr reg, reg, #24 + cache_addw( LSR_IMM(reg, reg, 24) ); // lsr reg, reg, #24 } } @@ -396,22 +488,22 @@ static void gen_extend_byte(bool sign,HostReg reg) { // the register is zero-extended (sign==false) or sign-extended (sign==true) static void gen_extend_word(bool sign,HostReg reg) { cache_checkinstr(4); - cache_addw(0x0000 + reg + (reg << 3) + (16 << 6)); // lsl reg, reg, #16 + cache_addw( LSL_IMM(reg, reg, 16) ); // lsl reg, reg, #16 if (sign) { - cache_addw(0x1000 + reg + (reg << 3) + (16 << 6)); // asr reg, reg, #16 + cache_addw( ASR_IMM(reg, reg, 16) ); // asr reg, reg, #16 } else { - cache_addw(0x0800 + reg + (reg << 3) + (16 << 6)); // lsr reg, reg, #16 + cache_addw( LSR_IMM(reg, reg, 16) ); // lsr reg, reg, #16 } } // add a 32bit value from memory to a full register static void gen_add(HostReg reg,void* op) { cache_checkinstr(2); - cache_addw(0x4680 + (temphi1 - HOST_r8) + (reg << 3)); // mov temphi1, reg + cache_addw( MOV_HI_LO(temphi1, reg) ); // mov temphi1, reg gen_mov_word_to_reg(reg, op, 1); cache_checkinstr(2); - cache_addw(0x4440 + (reg) + ((temphi1 - HOST_r8) << 3)); // add reg, temphi1 + cache_addw( ADD_LO_HI(reg, temphi1) ); // add reg, temphi1 } // add a 32bit constant value to a full register @@ -419,7 +511,7 @@ static void gen_add_imm(HostReg reg,Bit32u imm) { if(!imm) return; gen_mov_dword_to_reg_imm(templo1, imm); cache_checkinstr(2); - cache_addw(0x1800 + reg + (reg << 3) + (templo1 << 6)); // add reg, reg, templo1 + cache_addw( ADD_REG(reg, reg, templo1) ); // add reg, reg, templo1 } // and a 32bit constant value with a full register @@ -427,18 +519,18 @@ static void gen_and_imm(HostReg reg,Bit32u imm) { if(imm == 0xffffffff) return; gen_mov_dword_to_reg_imm(templo1, imm); cache_checkinstr(2); - cache_addw(0x4000 + reg + (templo1<< 3)); // and reg, templo1 + cache_addw( AND(reg, templo1) ); // and reg, templo1 } // move a 32bit constant value into memory static void gen_mov_direct_dword(void* dest,Bit32u imm) { cache_checkinstr(2); - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_dword_to_reg_imm(templosav, imm); gen_mov_word_from_reg(templosav, dest, 1); cache_checkinstr(2); - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 } // move an address into memory @@ -450,18 +542,18 @@ static void INLINE gen_mov_direct_ptr(void* dest,DRC_PTR_SIZE_IM imm) { static void gen_add_direct_byte(void* dest,Bit8s imm) { if(!imm) return; cache_checkinstr(2); - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_dword_to_reg_imm(templo2, (Bit32u)dest); gen_mov_word_to_reg_helper(templosav, dest, 1, templo2); cache_checkinstr(2); if (imm >= 0) { - cache_addw(0x3000 + (templosav << 8) + ((Bit32s)imm)); // add templosav, #(imm) + cache_addw( ADD_IMM8(templosav, (Bit32s)imm) ); // add templosav, #(imm) } else { - cache_addw(0x3800 + (templosav << 8) + (-((Bit32s)imm))); // sub templosav, #(-imm) + cache_addw( SUB_IMM8(templosav, -((Bit32s)imm)) ); // sub templosav, #(-imm) } gen_mov_word_from_reg_helper(templosav, dest, 1, templo2); cache_checkinstr(2); - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 } // add a 32bit (dword==true) or 16bit (dword==false) constant value to a memory value @@ -472,7 +564,7 @@ static void gen_add_direct_word(void* dest,Bit32u imm,bool dword) { return; } cache_checkinstr(2); - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_dword_to_reg_imm(templo2, (Bit32u)dest); gen_mov_word_to_reg_helper(templosav, dest, dword, templo2); if (dword) { @@ -481,28 +573,28 @@ static void gen_add_direct_word(void* dest,Bit32u imm,bool dword) { gen_mov_word_to_reg_imm(templo1, (Bit16u)imm); } cache_checkinstr(2); - cache_addw(0x1800 + templosav + (templosav << 3) + (templo1 << 6)); // add templosav, templosav, templo1 + cache_addw( ADD_REG(templosav, templosav, templo1) ); // add templosav, templosav, templo1 gen_mov_word_from_reg_helper(templosav, dest, dword, templo2); cache_checkinstr(2); - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 } // subtract an 8bit constant value from a dword memory value static void gen_sub_direct_byte(void* dest,Bit8s imm) { if(!imm) return; cache_checkinstr(2); - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_dword_to_reg_imm(templo2, (Bit32u)dest); gen_mov_word_to_reg_helper(templosav, dest, 1, templo2); cache_checkinstr(2); if (imm >= 0) { - cache_addw(0x3800 + (templosav << 8) + ((Bit32s)imm)); // sub templosav, #(imm) + cache_addw( SUB_IMM8(templosav, (Bit32s)imm) ); // sub templosav, #(imm) } else { - cache_addw(0x3000 + (templosav << 8) + (-((Bit32s)imm))); // add templosav, #(-imm) + cache_addw( ADD_IMM8(templosav, -((Bit32s)imm)) ); // add templosav, #(-imm) } gen_mov_word_from_reg_helper(templosav, dest, 1, templo2); cache_checkinstr(2); - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 } // subtract a 32bit (dword==true) or 16bit (dword==false) constant value from a memory value @@ -513,7 +605,7 @@ static void gen_sub_direct_word(void* dest,Bit32u imm,bool dword) { return; } cache_checkinstr(2); - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_dword_to_reg_imm(templo2, (Bit32u)dest); gen_mov_word_to_reg_helper(templosav, dest, dword, templo2); if (dword) { @@ -522,10 +614,10 @@ static void gen_sub_direct_word(void* dest,Bit32u imm,bool dword) { gen_mov_word_to_reg_imm(templo1, (Bit16u)imm); } cache_checkinstr(2); - cache_addw(0x1a00 + templosav + (templosav << 3) + (templo1 << 6)); // sub templosav, templosav, templo1 + cache_addw( SUB_REG(templosav, templosav, templo1) ); // sub templosav, templosav, templo1 gen_mov_word_from_reg_helper(templosav, dest, dword, templo2); cache_checkinstr(2); - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 } // effective address calculation, destination is dest_reg @@ -534,11 +626,11 @@ static void gen_sub_direct_word(void* dest,Bit32u imm,bool dword) { static INLINE void gen_lea(HostReg dest_reg,HostReg scale_reg,Bitu scale,Bits imm) { if (scale) { cache_checkinstr(4); - cache_addw(0x0000 + templo1 + (scale_reg << 3) + (scale << 6)); // lsl templo1, scale_reg, #(scale) - cache_addw(0x1800 + dest_reg + (dest_reg << 3) + (templo1 << 6)); // add dest_reg, dest_reg, templo1 + cache_addw( LSL_IMM(templo1, scale_reg, scale) ); // lsl templo1, scale_reg, #(scale) + cache_addw( ADD_REG(dest_reg, dest_reg, templo1) ); // add dest_reg, dest_reg, templo1 } else { cache_checkinstr(2); - cache_addw(0x1800 + dest_reg + (dest_reg << 3) + (scale_reg << 6)); // add dest_reg, dest_reg, scale_reg + cache_addw( ADD_REG(dest_reg, dest_reg, scale_reg) ); // add dest_reg, dest_reg, scale_reg } gen_add_imm(dest_reg, imm); } @@ -549,7 +641,7 @@ static INLINE void gen_lea(HostReg dest_reg,HostReg scale_reg,Bitu scale,Bits im static INLINE void gen_lea(HostReg dest_reg,Bitu scale,Bits imm) { if (scale) { cache_checkinstr(2); - cache_addw(0x0000 + dest_reg + (dest_reg << 3) + (scale << 6)); // lsl dest_reg, dest_reg, #(scale) + cache_addw( LSL_IMM(dest_reg, dest_reg, scale) ); // lsl dest_reg, dest_reg, #(scale) } gen_add_imm(dest_reg, imm); } @@ -562,23 +654,23 @@ static void gen_call_function_helper(void * func) { *(Bit32u*)datapos=(Bit32u)func; if (((Bit32u)cache.pos & 0x03) == 0) { - cache_addw(0x4800 + (templo1 << 8) + ((datapos - (cache.pos + 4)) >> 2)); // ldr templo1, [pc, datapos] - cache_addw(0xa000 + (templo2 << 8) + (8 >> 2)); // adr templo2, after_call (add templo2, pc, #8) - cache_addw(0x3000 + (templo2 << 8) + (1)); // add templo2, #1 - cache_addw(0x4680 + (HOST_lr - HOST_r8) + (templo2 << 3)); // mov lr, templo2 - cache_addw(0x4700 + (templo1 << 3)); // bx templo1 --- switch to arm state - cache_addw(0x46c0); // nop + cache_addw( LDR_PC_IMM(templo1, datapos - (cache.pos + 4)) ); // ldr templo1, [pc, datapos] + cache_addw( ADD_LO_PC_IMM(templo2, 8) ); // adr templo2, after_call (add templo2, pc, #8) + cache_addw( ADD_IMM8(templo2, 1) ); // add templo2, #1 + cache_addw( MOV_HI_LO(HOST_lr, templo2) ); // mov lr, templo2 + cache_addw( BX(templo1) ); // bx templo1 --- switch to arm state + cache_addw( NOP ); // nop } else { - cache_addw(0x4800 + (templo1 << 8) + ((datapos - (cache.pos + 2)) >> 2)); // ldr templo1, [pc, datapos] - cache_addw(0xa000 + (templo2 << 8) + (4 >> 2)); // adr templo2, after_call (add templo2, pc, #4) - cache_addw(0x3000 + (templo2 << 8) + (1)); // add templo2, #1 - cache_addw(0x4680 + (HOST_lr - HOST_r8) + (templo2 << 3)); // mov lr, templo2 - cache_addw(0x4700 + (templo1 << 3)); // bx templo1 --- switch to arm state + cache_addw( LDR_PC_IMM(templo1, datapos - (cache.pos + 2)) ); // ldr templo1, [pc, datapos] + cache_addw( ADD_LO_PC_IMM(templo2, 4) ); // adr templo2, after_call (add templo2, pc, #4) + cache_addw( ADD_IMM8(templo2, 1) ); // add templo2, #1 + cache_addw( MOV_HI_LO(HOST_lr, templo2) ); // mov lr, templo2 + cache_addw( BX(templo1) ); // bx templo1 --- switch to arm state } // after_call: // thumb state from now on - cache_addw(0x1c00 + FC_RETOP + (HOST_a1 << 3)); // mov FC_RETOP, a1 + cache_addw( MOV_REG(FC_RETOP, HOST_a1) ); // mov FC_RETOP, a1 } // generate a call to a parameterless function @@ -629,42 +721,42 @@ static void INLINE gen_load_param_mem(Bitu mem,Bitu param) { // jump to an address pointed at by ptr, offset is in imm static void gen_jmp_ptr(void * ptr,Bits imm=0) { cache_checkinstr(2); - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_word_to_reg(templosav, ptr, 1); if (imm) { gen_mov_dword_to_reg_imm(templo2, imm); cache_checkinstr(2); - cache_addw(0x1800 + templosav + (templosav << 3) + (templo2 << 6)); // add templosav, templosav, templo2 + cache_addw( ADD_REG(templosav, templosav, templo2) ); // add templosav, templosav, templo2 } #if (1) // (*ptr) should be word aligned if ((imm & 0x03) == 0) { cache_checkinstr(8); - cache_addw(0x6800 + templo2 + (templosav << 3)); // ldr templo2, [templosav] + cache_addw( LDR_IMM(templo2, templosav, 0) ); // ldr templo2, [templosav] } else #endif { cache_checkinstr(26); - cache_addw(0x7800 + templo2 + (templosav << 3)); // ldrb templo2, [templosav] - cache_addw(0x7800 + templo1 + (templosav << 3) + (1 << 6)); // ldrb templo1, [templosav, #1] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (8 << 6)); // lsl templo1, templo1, #8 - cache_addw(0x4300 + templo2 + (templo1 << 3)); // orr templo2, templo1 - cache_addw(0x7800 + templo1 + (templosav << 3) + (2 << 6)); // ldrb templo1, [templosav, #2] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (16 << 6)); // lsl templo1, templo1, #16 - cache_addw(0x4300 + templo2 + (templo1 << 3)); // orr templo2, templo1 - cache_addw(0x7800 + templo1 + (templosav << 3) + (3 << 6)); // ldrb templo1, [templosav, #3] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (24 << 6)); // lsl templo1, templo1, #24 - cache_addw(0x4300 + templo2 + (templo1 << 3)); // orr templo2, templo1 + cache_addw( LDRB_IMM(templo2, templosav, 0) ); // ldrb templo2, [templosav] + cache_addw( LDRB_IMM(templo1, templosav, 1) ); // ldrb templo1, [templosav, #1] + cache_addw( LSL_IMM(templo1, templo1, 8) ); // lsl templo1, templo1, #8 + cache_addw( ORR(templo2, templo1) ); // orr templo2, templo1 + cache_addw( LDRB_IMM(templo1, templosav, 2) ); // ldrb templo1, [templosav, #2] + cache_addw( LSL_IMM(templo1, templo1, 16) ); // lsl templo1, templo1, #16 + cache_addw( ORR(templo2, templo1) ); // orr templo2, templo1 + cache_addw( LDRB_IMM(templo1, templosav, 3) ); // ldrb templo1, [templosav, #3] + cache_addw( LSL_IMM(templo1, templo1, 24) ); // lsl templo1, templo1, #24 + cache_addw( ORR(templo2, templo1) ); // orr templo2, templo1 } // increase jmp address to keep thumb state - cache_addw(0x1c00 + templo2 + (templo2 << 3) + (1 << 6)); // add templo2, templo2, #1 + cache_addw( ADD_IMM3(templo2, templo2, 1) ); // add templo2, templo2, #1 - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 - cache_addw(0x4700 + (templo2 << 3)); // bx templo2 + cache_addw( BX(templo2) ); // bx templo2 } // short conditional jump (+-127 bytes) if register is zero @@ -672,11 +764,11 @@ static void gen_jmp_ptr(void * ptr,Bits imm=0) { static Bit32u gen_create_branch_on_zero(HostReg reg,bool dword) { cache_checkinstr(4); if (dword) { - cache_addw(0x2800 + (reg << 8)); // cmp reg, #0 + cache_addw( CMP_IMM(reg, 0) ); // cmp reg, #0 } else { - cache_addw(0x0000 + templo1 + (reg << 3) + (16 << 6)); // lsl templo1, reg, #16 + cache_addw( LSL_IMM(templo1, reg, 16) ); // lsl templo1, reg, #16 } - cache_addw(0xd000); // beq j + cache_addw( BEQ_FWD(0) ); // beq j return ((Bit32u)cache.pos-2); } @@ -685,11 +777,11 @@ static Bit32u gen_create_branch_on_zero(HostReg reg,bool dword) { static Bit32u gen_create_branch_on_nonzero(HostReg reg,bool dword) { cache_checkinstr(4); if (dword) { - cache_addw(0x2800 + (reg << 8)); // cmp reg, #0 + cache_addw( CMP_IMM(reg, 0) ); // cmp reg, #0 } else { - cache_addw(0x0000 + templo1 + (reg << 3) + (16 << 6)); // lsl templo1, reg, #16 + cache_addw( LSL_IMM(templo1, reg, 16) ); // lsl templo1, reg, #16 } - cache_addw(0xd100); // bne j + cache_addw( BNE_FWD(0) ); // bne j return ((Bit32u)cache.pos-2); } @@ -714,17 +806,17 @@ static Bit32u gen_create_branch_long_nonzero(HostReg reg,bool isdword) { datapos = cache_reservedata(); if (isdword) { - cache_addw(0x2800 + (reg << 8)); // cmp reg, #0 + cache_addw( CMP_IMM(reg, 0) ); // cmp reg, #0 } else { - cache_addw(0x0000 + templo2 + (reg << 3) + (24 << 6)); // lsl templo2, reg, #24 + cache_addw( LSL_IMM(templo2, reg, 24) ); // lsl templo2, reg, #24 } - cache_addw(0xd000 + (2 >> 1)); // beq nobranch (pc+2) + cache_addw( BEQ_FWD(2) ); // beq nobranch (pc+2) if (((Bit32u)cache.pos & 0x03) == 0) { - cache_addw(0x4800 + (templo1 << 8) + ((datapos - (cache.pos + 4)) >> 2)); // ldr templo1, [pc, datapos] + cache_addw( LDR_PC_IMM(templo1, datapos - (cache.pos + 4)) ); // ldr templo1, [pc, datapos] } else { - cache_addw(0x4800 + (templo1 << 8) + ((datapos - (cache.pos + 2)) >> 2)); // ldr templo1, [pc, datapos] + cache_addw( LDR_PC_IMM(templo1, datapos - (cache.pos + 2)) ); // ldr templo1, [pc, datapos] } - cache_addw(0x4700 + (templo1 << 3)); // bx templo1 + cache_addw( BX(templo1) ); // bx templo1 // nobranch: return ((Bit32u)datapos); } @@ -736,14 +828,14 @@ static Bit32u gen_create_branch_long_leqzero(HostReg reg) { cache_checkinstr(8); datapos = cache_reservedata(); - cache_addw(0x2800 + (reg << 8)); // cmp reg, #0 - cache_addw(0xdc00 + (2 >> 1)); // bgt nobranch (pc+2) + cache_addw( CMP_IMM(reg, 0) ); // cmp reg, #0 + cache_addw( BGT_FWD(2) ); // bgt nobranch (pc+2) if (((Bit32u)cache.pos & 0x03) == 0) { - cache_addw(0x4800 + (templo1 << 8) + ((datapos - (cache.pos + 4)) >> 2)); // ldr templo1, [pc, datapos] + cache_addw( LDR_PC_IMM(templo1, datapos - (cache.pos + 4)) ); // ldr templo1, [pc, datapos] } else { - cache_addw(0x4800 + (templo1 << 8) + ((datapos - (cache.pos + 2)) >> 2)); // ldr templo1, [pc, datapos] + cache_addw( LDR_PC_IMM(templo1, datapos - (cache.pos + 2)) ); // ldr templo1, [pc, datapos] } - cache_addw(0x4700 + (templo1 << 3)); // bx templo1 + cache_addw( BX(templo1) ); // bx templo1 // nobranch: return ((Bit32u)datapos); } @@ -761,39 +853,39 @@ static void gen_run_code(void) { // thumb state from now on cache_addw(0xb500); // push {lr} - cache_addw(0x4640 + HOST_r3 + ((FC_SEGS_ADDR - HOST_r8) << 3)); // mov r3, FC_SEGS_ADDR - cache_addw(0x4640 + HOST_r2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov r2, FC_REGS_ADDR + cache_addw( MOV_LO_HI(HOST_r3, FC_SEGS_ADDR) ); // mov r3, FC_SEGS_ADDR + cache_addw( MOV_LO_HI(HOST_r2, FC_REGS_ADDR) ); // mov r2, FC_REGS_ADDR cache_addw(0xb4fc); // push {r2,r3,v1-v4} // adr: 16 - cache_addw(0x4800 + (HOST_r3 << 8) + ((64 - (16 + 4)) >> 2)); // ldr r3, [pc, #(&Segs)] + cache_addw( LDR_PC_IMM(HOST_r3, 64 - (16 + 4)) ); // ldr r3, [pc, #(&Segs)] // adr: 18 - cache_addw(0x4800 + (HOST_r2 << 8) + ((68 - (18 + 2)) >> 2)); // ldr r2, [pc, #(&cpu_regs)] - cache_addw(0x4680 + (FC_SEGS_ADDR - HOST_r8) + (HOST_r3 << 3)); // mov FC_SEGS_ADDR, r3 - cache_addw(0x4680 + (FC_REGS_ADDR - HOST_r8) + (HOST_r2 << 3)); // mov FC_REGS_ADDR, r2 + cache_addw( LDR_PC_IMM(HOST_r2, 68 - (18 + 2)) ); // ldr r2, [pc, #(&cpu_regs)] + cache_addw( MOV_HI_LO(FC_SEGS_ADDR, HOST_r3) ); // mov FC_SEGS_ADDR, r3 + cache_addw( MOV_HI_LO(FC_REGS_ADDR, HOST_r2) ); // mov FC_REGS_ADDR, r2 // align 4 - - cache_addw(0xa302); // add r3, pc, #8 - cache_addw(0x3001); // add r0, #1 - cache_addw(0x3301); // add r3, #1 + cache_addw( ADD_LO_PC_IMM(HOST_r3, 8) ); // add r3, pc, #8 + cache_addw( ADD_IMM8(HOST_r0, 1) ); // add r0, #1 + cache_addw( ADD_IMM8(HOST_r3, 1) ); // add r3, #1 cache_addw(0xb408); // push {r3} - cache_addw(0x4700); // bx r0 - cache_addw(0x46c0); // nop + cache_addw( BX(HOST_r0) ); // bx r0 + cache_addw( NOP ); // nop // align 4 cache_addw(0xbcfc); // pop {r2,r3,v1-v4} - cache_addw(0x4680 + (FC_SEGS_ADDR - HOST_r8) + (HOST_r3 << 3)); // mov FC_SEGS_ADDR, r3 - cache_addw(0x4680 + (FC_REGS_ADDR - HOST_r8) + (HOST_r2 << 3)); // mov FC_REGS_ADDR, r2 + cache_addw( MOV_HI_LO(FC_SEGS_ADDR, HOST_r3) ); // mov FC_SEGS_ADDR, r3 + cache_addw( MOV_HI_LO(FC_REGS_ADDR, HOST_r2) ); // mov FC_REGS_ADDR, r2 cache_addw(0xbc08); // pop {r3} - cache_addw(0x4718); // bx r3 + cache_addw( BX(HOST_r3) ); // bx r3 + // fill up to 64 bytes - cache_addw(0x46c0); // nop - cache_addd(0x46c046c0); // nop, nop - cache_addd(0x46c046c0); // nop, nop - cache_addd(0x46c046c0); // nop, nop - cache_addd(0x46c046c0); // nop, nop + cache_addw( NOP ); // nop + cache_addd( NOP | (NOP << 16) ); // nop, nop + cache_addd( NOP | (NOP << 16) ); // nop, nop + cache_addd( NOP | (NOP << 16) ); // nop, nop + cache_addd( NOP | (NOP << 16) ); // nop, nop // adr: 64 cache_addd((Bit32u)&Segs); // address of "Segs" @@ -804,16 +896,16 @@ static void gen_run_code(void) { // return from a function static void gen_return_function(void) { cache_checkinstr(6); - cache_addw(0x1c00 + HOST_a1 + (FC_RETOP << 3)); // mov a1, FC_RETOP + cache_addw( MOV_REG(HOST_a1, FC_RETOP) ); // mov a1, FC_RETOP cache_addw(0xbc08); // pop {r3} - cache_addw(0x4718); // bx r3 + cache_addw( BX(HOST_r3) ); // bx r3 } // short unconditional jump (over data pool) // must emit at most CACHE_DATA_JUMP bytes static void INLINE gen_create_branch_short(void * func) { - cache_addw(0xe000 + (((Bit32u)func - ((Bit32u)cache.pos + 4)) >> 1) ); // b func + cache_addw( B_FWD((Bit32u)func - ((Bit32u)cache.pos + 4)) ); // b func } @@ -838,35 +930,35 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { case t_ADDb: case t_ADDw: case t_ADDd: - *(Bit16u*)pos=0x1800 + FC_RETOP + (HOST_a1 << 3) + (HOST_a2 << 6); // add FC_RETOP, a1, a2 - *(Bit16u*)(pos+2)=0xe000 + (8 >> 1); // b after_call (pc+8) + *(Bit16u*)pos=ADD_REG(FC_RETOP, HOST_a1, HOST_a2); // add FC_RETOP, a1, a2 + *(Bit16u*)(pos+2)=B_FWD(8); // b after_call (pc+8) break; case t_ORb: case t_ORw: case t_ORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4300 + FC_RETOP + (HOST_a2 << 3); // orr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (6 >> 1); // b after_call (pc+6) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ORR(FC_RETOP, HOST_a2); // orr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(6); // b after_call (pc+6) break; case t_ANDb: case t_ANDw: case t_ANDd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4000 + FC_RETOP + (HOST_a2 << 3); // and FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (6 >> 1); // b after_call (pc+6) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=AND(FC_RETOP, HOST_a2); // and FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(6); // b after_call (pc+6) break; case t_SUBb: case t_SUBw: case t_SUBd: - *(Bit16u*)pos=0x1a00 + FC_RETOP + (HOST_a1 << 3) + (HOST_a2 << 6); // sub FC_RETOP, a1, a2 - *(Bit16u*)(pos+2)=0xe000 + (8 >> 1); // b after_call (pc+8) + *(Bit16u*)pos=SUB_REG(FC_RETOP, HOST_a1, HOST_a2); // sub FC_RETOP, a1, a2 + *(Bit16u*)(pos+2)=B_FWD(8); // b after_call (pc+8) break; case t_XORb: case t_XORw: case t_XORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4040 + FC_RETOP + (HOST_a2 << 3); // eor FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (6 >> 1); // b after_call (pc+6) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=EOR(FC_RETOP, HOST_a2); // eor FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(6); // b after_call (pc+6) break; case t_CMPb: case t_CMPw: @@ -874,117 +966,117 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { case t_TESTb: case t_TESTw: case t_TESTd: - *(Bit16u*)pos=0xe000 + (10 >> 1); // b after_call (pc+10) + *(Bit16u*)pos=B_FWD(10); // b after_call (pc+10) break; case t_INCb: case t_INCw: case t_INCd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3) + (1 << 6); // add FC_RETOP, a1, #1 - *(Bit16u*)(pos+2)=0xe000 + (8 >> 1); // b after_call (pc+8) + *(Bit16u*)pos=ADD_IMM3(FC_RETOP, HOST_a1, 1); // add FC_RETOP, a1, #1 + *(Bit16u*)(pos+2)=B_FWD(8); // b after_call (pc+8) break; case t_DECb: case t_DECw: case t_DECd: - *(Bit16u*)pos=0x1e00 + FC_RETOP + (HOST_a1 << 3) + (1 << 6); // sub FC_RETOP, a1, #1 - *(Bit16u*)(pos+2)=0xe000 + (8 >> 1); // b after_call (pc+8) + *(Bit16u*)pos=SUB_IMM3(FC_RETOP, HOST_a1, 1); // sub FC_RETOP, a1, #1 + *(Bit16u*)(pos+2)=B_FWD(8); // b after_call (pc+8) break; case t_SHLb: case t_SHLw: case t_SHLd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4080 + FC_RETOP + (HOST_a2 << 3); // lsl FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (6 >> 1); // b after_call (pc+6) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=LSL_REG(FC_RETOP, HOST_a2); // lsl FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(6); // b after_call (pc+6) break; case t_SHRb: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (24 << 6); // lsl FC_RETOP, a1, #24 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (FC_RETOP << 3) + (24 << 6); // lsr FC_RETOP, FC_RETOP, #24 - *(Bit16u*)(pos+4)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (4 >> 1); // b after_call (pc+4) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 24); // lsl FC_RETOP, a1, #24 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, FC_RETOP, 24); // lsr FC_RETOP, FC_RETOP, #24 + *(Bit16u*)(pos+4)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(4); // b after_call (pc+4) break; case t_SHRw: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsl FC_RETOP, a1, #16 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (FC_RETOP << 3) + (16 << 6); // lsr FC_RETOP, FC_RETOP, #16 - *(Bit16u*)(pos+4)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (4 >> 1); // b after_call (pc+4) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 16); // lsl FC_RETOP, a1, #16 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, FC_RETOP, 16); // lsr FC_RETOP, FC_RETOP, #16 + *(Bit16u*)(pos+4)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(4); // b after_call (pc+4) break; case t_SHRd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (6 >> 1); // b after_call (pc+6) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(6); // b after_call (pc+6) break; case t_SARb: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (24 << 6); // lsl FC_RETOP, a1, #24 - *(Bit16u*)(pos+2)=0x1000 + FC_RETOP + (FC_RETOP << 3) + (24 << 6); // asr FC_RETOP, FC_RETOP, #24 - *(Bit16u*)(pos+4)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (4 >> 1); // b after_call (pc+4) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 24); // lsl FC_RETOP, a1, #24 + *(Bit16u*)(pos+2)=ASR_IMM(FC_RETOP, FC_RETOP, 24); // asr FC_RETOP, FC_RETOP, #24 + *(Bit16u*)(pos+4)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(4); // b after_call (pc+4) break; case t_SARw: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsl FC_RETOP, a1, #16 - *(Bit16u*)(pos+2)=0x1000 + FC_RETOP + (FC_RETOP << 3) + (16 << 6); // asr FC_RETOP, FC_RETOP, #16 - *(Bit16u*)(pos+4)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (4 >> 1); // b after_call (pc+4) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 16); // lsl FC_RETOP, a1, #16 + *(Bit16u*)(pos+2)=ASR_IMM(FC_RETOP, FC_RETOP, 16); // asr FC_RETOP, FC_RETOP, #16 + *(Bit16u*)(pos+4)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(4); // b after_call (pc+4) break; case t_SARd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (6 >> 1); // b after_call (pc+6) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(6); // b after_call (pc+6) break; case t_RORb: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (24 << 6); // lsl a1, a1, #24 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (8 << 6); // lsr FC_RETOP, a1, #8 - *(Bit16u*)(pos+4)=0x4300 + HOST_a1 + (FC_RETOP << 3); // orr a1, FC_RETOP - *(Bit16u*)(pos+6)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+8)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+10)=0x46c0; // nop - *(Bit16u*)(pos+12)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 24); // lsl a1, a1, #24 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, HOST_a1, 8); // lsr FC_RETOP, a1, #8 + *(Bit16u*)(pos+4)=ORR(HOST_a1, FC_RETOP); // orr a1, FC_RETOP + *(Bit16u*)(pos+6)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+8)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+10)=NOP; // nop + *(Bit16u*)(pos+12)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 break; case t_RORw: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (16 << 6); // lsl a1, a1, #16 - *(Bit16u*)(pos+2)=0x46c0; // nop - *(Bit16u*)(pos+4)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+6)=0x46c0; // nop - *(Bit16u*)(pos+8)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+10)=0x46c0; // nop - *(Bit16u*)(pos+12)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 16); // lsl a1, a1, #16 + *(Bit16u*)(pos+2)=NOP; // nop + *(Bit16u*)(pos+4)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+6)=NOP; // nop + *(Bit16u*)(pos+8)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+10)=NOP; // nop + *(Bit16u*)(pos+12)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 break; case t_RORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (6 >> 1); // b after_call (pc+6) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(6); // b after_call (pc+6) break; /*case t_ROLb: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (24 << 6); // lsl a1, a1, #24 - *(Bit16u*)(pos+2)=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+4)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (8 << 6); // lsr FC_RETOP, a1, #8 - *(Bit16u*)(pos+6)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+8)=0x4300 + HOST_a1 + (FC_RETOP << 3); // orr a1, FC_RETOP - *(Bit16u*)(pos+10)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+12)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+14)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 24); // lsl a1, a1, #24 + *(Bit16u*)(pos+2)=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+4)=LSR_IMM(FC_RETOP, HOST_a1, 8); // lsr FC_RETOP, a1, #8 + *(Bit16u*)(pos+6)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+8)=ORR(HOST_a1, FC_RETOP); // orr a1, FC_RETOP + *(Bit16u*)(pos+10)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+12)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+14)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 break;*/ case t_ROLw: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (16 << 6); // lsl a1, a1, #16 - *(Bit16u*)(pos+2)=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+4)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+6)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+8)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+10)=0x46c0; // nop - *(Bit16u*)(pos+12)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 16); // lsl a1, a1, #16 + *(Bit16u*)(pos+2)=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+4)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+6)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+8)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+10)=NOP; // nop + *(Bit16u*)(pos+12)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 break; case t_ROLd: - *(Bit16u*)pos=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+2)=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+4)=0x46c0; // nop - *(Bit16u*)(pos+6)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+8)=0x46c0; // nop - *(Bit16u*)(pos+10)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 - *(Bit16u*)(pos+12)=0x46c0; // nop + *(Bit16u*)pos=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+2)=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+4)=NOP; // nop + *(Bit16u*)(pos+6)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+8)=NOP; // nop + *(Bit16u*)(pos+10)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 + *(Bit16u*)(pos+12)=NOP; // nop break; case t_NEGb: case t_NEGw: case t_NEGd: - *(Bit16u*)pos=0x4240 + FC_RETOP + (HOST_a1 << 3); // neg FC_RETOP, a1 - *(Bit16u*)(pos+2)=0xe000 + (8 >> 1); // b after_call (pc+8) + *(Bit16u*)pos=NEG(FC_RETOP, HOST_a1); // neg FC_RETOP, a1 + *(Bit16u*)(pos+2)=B_FWD(8); // b after_call (pc+8) break; default: *(Bit32u*)( ( ((Bit32u) (*pos)) << 2 ) + ((Bit32u)pos + 4) ) = (Bit32u)fct_ptr; // simple_func @@ -998,35 +1090,35 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { case t_ADDb: case t_ADDw: case t_ADDd: - *(Bit16u*)pos=0x1800 + FC_RETOP + (HOST_a1 << 3) + (HOST_a2 << 6); // add FC_RETOP, a1, a2 - *(Bit16u*)(pos+2)=0xe000 + (6 >> 1); // b after_call (pc+6) + *(Bit16u*)pos=ADD_REG(FC_RETOP, HOST_a1, HOST_a2); // add FC_RETOP, a1, a2 + *(Bit16u*)(pos+2)=B_FWD(6); // b after_call (pc+6) break; case t_ORb: case t_ORw: case t_ORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4300 + FC_RETOP + (HOST_a2 << 3); // orr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (4 >> 1); // b after_call (pc+4) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ORR(FC_RETOP, HOST_a2); // orr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(4); // b after_call (pc+4) break; case t_ANDb: case t_ANDw: case t_ANDd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4000 + FC_RETOP + (HOST_a2 << 3); // and FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (4 >> 1); // b after_call (pc+4) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=AND(FC_RETOP, HOST_a2); // and FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(4); // b after_call (pc+4) break; case t_SUBb: case t_SUBw: case t_SUBd: - *(Bit16u*)pos=0x1a00 + FC_RETOP + (HOST_a1 << 3) + (HOST_a2 << 6); // sub FC_RETOP, a1, a2 - *(Bit16u*)(pos+2)=0xe000 + (6 >> 1); // b after_call (pc+6) + *(Bit16u*)pos=SUB_REG(FC_RETOP, HOST_a1, HOST_a2); // sub FC_RETOP, a1, a2 + *(Bit16u*)(pos+2)=B_FWD(6); // b after_call (pc+6) break; case t_XORb: case t_XORw: case t_XORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4040 + FC_RETOP + (HOST_a2 << 3); // eor FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (4 >> 1); // b after_call (pc+4) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=EOR(FC_RETOP, HOST_a2); // eor FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(4); // b after_call (pc+4) break; case t_CMPb: case t_CMPw: @@ -1034,121 +1126,121 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { case t_TESTb: case t_TESTw: case t_TESTd: - *(Bit16u*)pos=0xe000 + (8 >> 1); // b after_call (pc+8) + *(Bit16u*)pos=B_FWD(8); // b after_call (pc+8) break; case t_INCb: case t_INCw: case t_INCd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3) + (1 << 6); // add FC_RETOP, a1, #1 - *(Bit16u*)(pos+2)=0xe000 + (6 >> 1); // b after_call (pc+6) + *(Bit16u*)pos=ADD_IMM3(FC_RETOP, HOST_a1, 1); // add FC_RETOP, a1, #1 + *(Bit16u*)(pos+2)=B_FWD(6); // b after_call (pc+6) break; case t_DECb: case t_DECw: case t_DECd: - *(Bit16u*)pos=0x1e00 + FC_RETOP + (HOST_a1 << 3) + (1 << 6); // sub FC_RETOP, a1, #1 - *(Bit16u*)(pos+2)=0xe000 + (6 >> 1); // b after_call (pc+6) + *(Bit16u*)pos=SUB_IMM3(FC_RETOP, HOST_a1, 1); // sub FC_RETOP, a1, #1 + *(Bit16u*)(pos+2)=B_FWD(6); // b after_call (pc+6) break; case t_SHLb: case t_SHLw: case t_SHLd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4080 + FC_RETOP + (HOST_a2 << 3); // lsl FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (4 >> 1); // b after_call (pc+4) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=LSL_REG(FC_RETOP, HOST_a2); // lsl FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(4); // b after_call (pc+4) break; case t_SHRb: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (24 << 6); // lsl FC_RETOP, a1, #24 - *(Bit16u*)(pos+2)=0x46c0; // nop - *(Bit16u*)(pos+4)=0x0800 + FC_RETOP + (FC_RETOP << 3) + (24 << 6); // lsr FC_RETOP, FC_RETOP, #24 - *(Bit16u*)(pos+6)=0x46c0; // nop - *(Bit16u*)(pos+8)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+10)=0x46c0; // nop + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 24); // lsl FC_RETOP, a1, #24 + *(Bit16u*)(pos+2)=NOP; // nop + *(Bit16u*)(pos+4)=LSR_IMM(FC_RETOP, FC_RETOP, 24); // lsr FC_RETOP, FC_RETOP, #24 + *(Bit16u*)(pos+6)=NOP; // nop + *(Bit16u*)(pos+8)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+10)=NOP; // nop break; case t_SHRw: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsl FC_RETOP, a1, #16 - *(Bit16u*)(pos+2)=0x46c0; // nop - *(Bit16u*)(pos+4)=0x0800 + FC_RETOP + (FC_RETOP << 3) + (16 << 6); // lsr FC_RETOP, FC_RETOP, #16 - *(Bit16u*)(pos+6)=0x46c0; // nop - *(Bit16u*)(pos+8)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+10)=0x46c0; // nop + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 16); // lsl FC_RETOP, a1, #16 + *(Bit16u*)(pos+2)=NOP; // nop + *(Bit16u*)(pos+4)=LSR_IMM(FC_RETOP, FC_RETOP, 16); // lsr FC_RETOP, FC_RETOP, #16 + *(Bit16u*)(pos+6)=NOP; // nop + *(Bit16u*)(pos+8)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+10)=NOP; // nop break; case t_SHRd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (4 >> 1); // b after_call (pc+4) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(4); // b after_call (pc+4) break; case t_SARb: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (24 << 6); // lsl FC_RETOP, a1, #24 - *(Bit16u*)(pos+2)=0x46c0; // nop - *(Bit16u*)(pos+4)=0x1000 + FC_RETOP + (FC_RETOP << 3) + (24 << 6); // asr FC_RETOP, FC_RETOP, #24 - *(Bit16u*)(pos+6)=0x46c0; // nop - *(Bit16u*)(pos+8)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+10)=0x46c0; // nop + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 24); // lsl FC_RETOP, a1, #24 + *(Bit16u*)(pos+2)=NOP; // nop + *(Bit16u*)(pos+4)=ASR_IMM(FC_RETOP, FC_RETOP, 24); // asr FC_RETOP, FC_RETOP, #24 + *(Bit16u*)(pos+6)=NOP; // nop + *(Bit16u*)(pos+8)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+10)=NOP; // nop break; case t_SARw: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsl FC_RETOP, a1, #16 - *(Bit16u*)(pos+2)=0x46c0; // nop - *(Bit16u*)(pos+4)=0x1000 + FC_RETOP + (FC_RETOP << 3) + (16 << 6); // asr FC_RETOP, FC_RETOP, #16 - *(Bit16u*)(pos+6)=0x46c0; // nop - *(Bit16u*)(pos+8)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+10)=0x46c0; // nop + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 16); // lsl FC_RETOP, a1, #16 + *(Bit16u*)(pos+2)=NOP; // nop + *(Bit16u*)(pos+4)=ASR_IMM(FC_RETOP, FC_RETOP, 16); // asr FC_RETOP, FC_RETOP, #16 + *(Bit16u*)(pos+6)=NOP; // nop + *(Bit16u*)(pos+8)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+10)=NOP; // nop break; case t_SARd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (4 >> 1); // b after_call (pc+4) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(4); // b after_call (pc+4) break; case t_RORb: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (24 << 6); // lsl a1, a1, #24 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (8 << 6); // lsr FC_RETOP, a1, #8 - *(Bit16u*)(pos+4)=0x4300 + HOST_a1 + (FC_RETOP << 3); // orr a1, FC_RETOP - *(Bit16u*)(pos+6)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+8)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+10)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 24); // lsl a1, a1, #24 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, HOST_a1, 8); // lsr FC_RETOP, a1, #8 + *(Bit16u*)(pos+4)=ORR(HOST_a1, FC_RETOP); // orr a1, FC_RETOP + *(Bit16u*)(pos+6)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+8)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+10)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 break; case t_RORw: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (16 << 6); // lsl a1, a1, #16 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+4)=0x46c0; // nop - *(Bit16u*)(pos+6)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+8)=0x46c0; // nop - *(Bit16u*)(pos+10)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 16); // lsl a1, a1, #16 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+4)=NOP; // nop + *(Bit16u*)(pos+6)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+8)=NOP; // nop + *(Bit16u*)(pos+10)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 break; case t_RORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (4 >> 1); // b after_call (pc+4) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(4); // b after_call (pc+4) break; /*case t_ROLb: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (24 << 6); // lsl a1, a1, #24 - *(Bit16u*)(pos+2)=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+4)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (8 << 6); // lsr FC_RETOP, a1, #8 - *(Bit16u*)(pos+6)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+8)=0x4300 + HOST_a1 + (FC_RETOP << 3); // orr a1, FC_RETOP - *(Bit16u*)(pos+10)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+12)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+14)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 24); // lsl a1, a1, #24 + *(Bit16u*)(pos+2)=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+4)=LSR_IMM(FC_RETOP, HOST_a1, 8); // lsr FC_RETOP, a1, #8 + *(Bit16u*)(pos+6)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+8)=ORR(HOST_a1, FC_RETOP); // orr a1, FC_RETOP + *(Bit16u*)(pos+10)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+12)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+14)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 break;*/ case t_ROLw: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (16 << 6); // lsl a1, a1, #16 - *(Bit16u*)(pos+2)=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+4)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+6)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+8)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+10)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 16); // lsl a1, a1, #16 + *(Bit16u*)(pos+2)=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+4)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+6)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+8)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+10)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 break; case t_ROLd: - *(Bit16u*)pos=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+2)=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+4)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+6)=0x46c0; // nop - *(Bit16u*)(pos+8)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 - *(Bit16u*)(pos+10)=0x46c0; // nop + *(Bit16u*)pos=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+2)=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+4)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+6)=NOP; // nop + *(Bit16u*)(pos+8)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 + *(Bit16u*)(pos+10)=NOP; // nop break; case t_NEGb: case t_NEGw: case t_NEGd: - *(Bit16u*)pos=0x4240 + FC_RETOP + (HOST_a1 << 3); // neg FC_RETOP, a1 - *(Bit16u*)(pos+2)=0xe000 + (6 >> 1); // b after_call (pc+6) + *(Bit16u*)pos=NEG(FC_RETOP, HOST_a1); // neg FC_RETOP, a1 + *(Bit16u*)(pos+2)=B_FWD(6); // b after_call (pc+6) break; default: *(Bit32u*)( ( ((Bit32u) (*pos)) << 2 ) + ((Bit32u)pos + 2) ) = (Bit32u)fct_ptr; // simple_func @@ -1175,23 +1267,23 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { // 16bit moves may destroy the upper 16bit of the destination register static void gen_mov_seg16_to_reg(HostReg dest_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo1 + ((FC_SEGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_SEGS_ADDR - cache_addw(0x8800 + dest_reg + (templo1 << 3) + (index << 5)); // ldrh dest_reg, [templo1, #index] + cache_addw( MOV_LO_HI(templo1, FC_SEGS_ADDR) ); // mov templo1, FC_SEGS_ADDR + cache_addw( LDRH_IMM(dest_reg, templo1, index) ); // ldrh dest_reg, [templo1, #index] } // mov 32bit value from Segs[index] into dest_reg using FC_SEGS_ADDR (index modulo 4 must be zero) static void gen_mov_seg32_to_reg(HostReg dest_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo1 + ((FC_SEGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_SEGS_ADDR - cache_addw(0x6800 + dest_reg + (templo1 << 3) + (index << 4)); // ldr dest_reg, [templo1, #index] + cache_addw( MOV_LO_HI(templo1, FC_SEGS_ADDR) ); // mov templo1, FC_SEGS_ADDR + cache_addw( LDR_IMM(dest_reg, templo1, index) ); // ldr dest_reg, [templo1, #index] } // add a 32bit value from Segs[index] to a full register using FC_SEGS_ADDR (index modulo 4 must be zero) static void gen_add_seg32_to_reg(HostReg reg,Bitu index) { cache_checkinstr(6); - cache_addw(0x4640 + templo1 + ((FC_SEGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_SEGS_ADDR - cache_addw(0x6800 + templo2 + (templo1 << 3) + (index << 4)); // ldr templo2, [templo1, #index] - cache_addw(0x1800 + reg + (reg << 3) + (templo2 << 6)); // add reg, reg, templo2 + cache_addw( MOV_LO_HI(templo1, FC_SEGS_ADDR) ); // mov templo1, FC_SEGS_ADDR + cache_addw( LDR_IMM(templo2, templo1, index) ); // ldr templo2, [templo1, #index] + cache_addw( ADD_REG(reg, reg, templo2) ); // add reg, reg, templo2 } #endif @@ -1202,26 +1294,26 @@ static void gen_add_seg32_to_reg(HostReg reg,Bitu index) { // 16bit moves may destroy the upper 16bit of the destination register static void gen_mov_regval16_to_reg(HostReg dest_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR - cache_addw(0x8800 + dest_reg + (templo2 << 3) + (index << 5)); // ldrh dest_reg, [templo2, #index] + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR + cache_addw( LDRH_IMM(dest_reg, templo2, index) ); // ldrh dest_reg, [templo2, #index] } // mov 32bit value from cpu_regs[index] into dest_reg using FC_REGS_ADDR (index modulo 4 must be zero) static void gen_mov_regval32_to_reg(HostReg dest_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR - cache_addw(0x6800 + dest_reg + (templo2 << 3) + (index << 4)); // ldr dest_reg, [templo2, #index] + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR + cache_addw( LDR_IMM(dest_reg, templo2, index) ); // ldr dest_reg, [templo2, #index] } // move a 32bit (dword==true) or 16bit (dword==false) value from cpu_regs[index] into dest_reg using FC_REGS_ADDR (if dword==true index modulo 4 must be zero) (if dword==false index modulo 2 must be zero) // 16bit moves may destroy the upper 16bit of the destination register static void gen_mov_regword_to_reg(HostReg dest_reg,Bitu index,bool dword) { cache_checkinstr(4); - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR if (dword) { - cache_addw(0x6800 + dest_reg + (templo2 << 3) + (index << 4)); // ldr dest_reg, [templo2, #index] + cache_addw( LDR_IMM(dest_reg, templo2, index) ); // ldr dest_reg, [templo2, #index] } else { - cache_addw(0x8800 + dest_reg + (templo2 << 3) + (index << 5)); // ldrh dest_reg, [templo2, #index] + cache_addw( LDRH_IMM(dest_reg, templo2, index) ); // ldrh dest_reg, [templo2, #index] } } @@ -1231,8 +1323,8 @@ static void gen_mov_regword_to_reg(HostReg dest_reg,Bitu index,bool dword) { // registers might not be directly byte-accessible on some architectures static void gen_mov_regbyte_to_reg_low(HostReg dest_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR - cache_addw(0x7800 + dest_reg + (templo2 << 3) + (index << 6)); // ldrb dest_reg, [templo2, #index] + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR + cache_addw( LDRB_IMM(dest_reg, templo2, index) ); // ldrb dest_reg, [templo2, #index] } // move an 8bit value from cpu_regs[index] into dest_reg using FC_REGS_ADDR @@ -1241,49 +1333,50 @@ static void gen_mov_regbyte_to_reg_low(HostReg dest_reg,Bitu index) { // not directly byte-accessible on some architectures static void INLINE gen_mov_regbyte_to_reg_low_canuseword(HostReg dest_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR - cache_addw(0x7800 + dest_reg + (templo2 << 3) + (index << 6)); // ldrb dest_reg, [templo2, #index] + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR + cache_addw( LDRB_IMM(dest_reg, templo2, index) ); // ldrb dest_reg, [templo2, #index] } // add a 32bit value from cpu_regs[index] to a full register using FC_REGS_ADDR (index modulo 4 must be zero) static void gen_add_regval32_to_reg(HostReg reg,Bitu index) { cache_checkinstr(6); - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR - cache_addw(0x6800 + templo1 + (templo2 << 3) + (index << 4)); // ldr templo1, [templo2, #index] - cache_addw(0x1800 + reg + (reg << 3) + (templo1 << 6)); // add reg, reg, templo1 + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR + cache_addw( LDR_IMM(templo1, templo2, index) ); // ldr templo1, [templo2, #index] + cache_addw( ADD_REG(reg, reg, templo1) ); // add reg, reg, templo1 } // move 16bit of register into cpu_regs[index] using FC_REGS_ADDR (index modulo 2 must be zero) static void gen_mov_regval16_from_reg(HostReg src_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo1 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_REGS_ADDR - cache_addw(0x8000 + src_reg + (templo1 << 3) + (index << 5)); // strh src_reg, [templo1, #index] + cache_addw( MOV_LO_HI(templo1, FC_REGS_ADDR) ); // mov templo1, FC_REGS_ADDR + cache_addw( STRH_IMM(src_reg, templo1, index) ); // strh src_reg, [templo1, #index] } // move 32bit of register into cpu_regs[index] using FC_REGS_ADDR (index modulo 4 must be zero) static void gen_mov_regval32_from_reg(HostReg src_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo1 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_REGS_ADDR - cache_addw(0x6000 + src_reg + (templo1 << 3) + (index << 4)); // str src_reg, [templo1, #index] + cache_addw( MOV_LO_HI(templo1, FC_REGS_ADDR) ); // mov templo1, FC_REGS_ADDR + cache_addw( STR_IMM(src_reg, templo1, index) ); // str src_reg, [templo1, #index] } // move 32bit (dword==true) or 16bit (dword==false) of a register into cpu_regs[index] using FC_REGS_ADDR (if dword==true index modulo 4 must be zero) (if dword==false index modulo 2 must be zero) static void gen_mov_regword_from_reg(HostReg src_reg,Bitu index,bool dword) { cache_checkinstr(4); - cache_addw(0x4640 + templo1 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_REGS_ADDR + cache_addw( MOV_LO_HI(templo1, FC_REGS_ADDR) ); // mov templo1, FC_REGS_ADDR if (dword) { - cache_addw(0x6000 + src_reg + (templo1 << 3) + (index << 4)); // str src_reg, [templo1, #index] + cache_addw( STR_IMM(src_reg, templo1, index) ); // str src_reg, [templo1, #index] } else { - cache_addw(0x8000 + src_reg + (templo1 << 3) + (index << 5)); // strh src_reg, [templo1, #index] + cache_addw( STRH_IMM(src_reg, templo1, index) ); // strh src_reg, [templo1, #index] } } // move the lowest 8bit of a register into cpu_regs[index] using FC_REGS_ADDR static void gen_mov_regbyte_from_reg_low(HostReg src_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo1 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_REGS_ADDR - cache_addw(0x7000 + src_reg + (templo1 << 3) + (index << 6)); // strb src_reg, [templo1, #index] + cache_addw( MOV_LO_HI(templo1, FC_REGS_ADDR) ); // mov templo1, FC_REGS_ADDR + cache_addw( STRB_IMM(src_reg, templo1, index) ); // strb src_reg, [templo1, #index] } + #endif diff --git a/src/cpu/core_dynrec/risc_armv4le-thumb-niw.h b/src/cpu/core_dynrec/risc_armv4le-thumb-niw.h index 0853b8e..64a3de8 100644 --- a/src/cpu/core_dynrec/risc_armv4le-thumb-niw.h +++ b/src/cpu/core_dynrec/risc_armv4le-thumb-niw.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2002-2008 The DOSBox Team + * Copyright (C) 2002-2009 The DOSBox Team * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,7 +16,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $Id: risc_armv4le-thumb-niw.h,v 1.2 2008/09/19 16:48:02 c2woody Exp $ */ +/* $Id: risc_armv4le-thumb-niw.h,v 1.3 2009/05/16 21:52:47 c2woody Exp $ */ /* ARMv4 (little endian) backend by M-HT (thumb version with data pool) */ @@ -64,6 +64,97 @@ #endif +// instruction encodings + +// move +// mov dst, #imm @ 0 <= imm <= 255 +#define MOV_IMM(dst, imm) (0x2000 + ((dst) << 8) + (imm) ) +// mov dst, src +#define MOV_REG(dst, src) ADD_IMM3(dst, src, 0) +// mov dst, src +#define MOV_LO_HI(dst, src) (0x4640 + (dst) + (((src) - HOST_r8) << 3) ) +// mov dst, src +#define MOV_HI_LO(dst, src) (0x4680 + ((dst) - HOST_r8) + ((src) << 3) ) + +// arithmetic +// add dst, src, #imm @ 0 <= imm <= 7 +#define ADD_IMM3(dst, src, imm) (0x1c00 + (dst) + ((src) << 3) + ((imm) << 6) ) +// add dst, #imm @ 0 <= imm <= 255 +#define ADD_IMM8(dst, imm) (0x3000 + ((dst) << 8) + (imm) ) +// add dst, src1, src2 +#define ADD_REG(dst, src1, src2) (0x1800 + (dst) + ((src1) << 3) + ((src2) << 6) ) +// add dst, src +#define ADD_LO_HI(dst, src) (0x4440 + (dst) + (((src) - HOST_r8) << 3) ) +// add dst, pc, #imm @ 0 <= imm < 1024 & imm mod 4 = 0 +#define ADD_LO_PC_IMM(dst, imm) (0xa000 + ((dst) << 8) + ((imm) >> 2) ) +// sub dst, src1, src2 +#define SUB_REG(dst, src1, src2) (0x1a00 + (dst) + ((src1) << 3) + ((src2) << 6) ) +// sub dst, src, #imm @ 0 <= imm <= 7 +#define SUB_IMM3(dst, src, imm) (0x1e00 + (dst) + ((src) << 3) + ((imm) << 6) ) +// sub dst, #imm @ 0 <= imm <= 255 +#define SUB_IMM8(dst, imm) (0x3800 + ((dst) << 8) + (imm) ) +// neg dst, src +#define NEG(dst, src) (0x4240 + (dst) + ((src) << 3) ) +// cmp dst, #imm @ 0 <= imm <= 255 +#define CMP_IMM(dst, imm) (0x2800 + ((dst) << 8) + (imm) ) +// nop +#define NOP (0x46c0) + +// logical +// and dst, src +#define AND(dst, src) (0x4000 + (dst) + ((src) << 3) ) +// eor dst, src +#define EOR(dst, src) (0x4040 + (dst) + ((src) << 3) ) +// orr dst, src +#define ORR(dst, src) (0x4300 + (dst) + ((src) << 3) ) + +// shift/rotate +// lsl dst, src, #imm +#define LSL_IMM(dst, src, imm) (0x0000 + (dst) + ((src) << 3) + ((imm) << 6) ) +// lsl dst, reg +#define LSL_REG(dst, reg) (0x4080 + (dst) + ((reg) << 3) ) +// lsr dst, src, #imm +#define LSR_IMM(dst, src, imm) (0x0800 + (dst) + ((src) << 3) + ((imm) << 6) ) +// lsr dst, reg +#define LSR_REG(dst, reg) (0x40c0 + (dst) + ((reg) << 3) ) +// asr dst, src, #imm +#define ASR_IMM(dst, src, imm) (0x1000 + (dst) + ((src) << 3) + ((imm) << 6) ) +// asr dst, reg +#define ASR_REG(dst, reg) (0x4100 + (dst) + ((reg) << 3) ) +// ror dst, reg +#define ROR_REG(dst, reg) (0x41c0 + (dst) + ((reg) << 3) ) + +// load +// ldr reg, [addr, #imm] @ 0 <= imm < 128 & imm mod 4 = 0 +#define LDR_IMM(reg, addr, imm) (0x6800 + (reg) + ((addr) << 3) + ((imm) << 4) ) +// ldrh reg, [addr, #imm] @ 0 <= imm < 64 & imm mod 2 = 0 +#define LDRH_IMM(reg, addr, imm) (0x8800 + (reg) + ((addr) << 3) + ((imm) << 5) ) +// ldrb reg, [addr, #imm] @ 0 <= imm < 32 +#define LDRB_IMM(reg, addr, imm) (0x7800 + (reg) + ((addr) << 3) + ((imm) << 6) ) +// ldr reg, [pc, #imm] @ 0 <= imm < 1024 & imm mod 4 = 0 +#define LDR_PC_IMM(reg, imm) (0x4800 + ((reg) << 8) + ((imm) >> 2) ) + +// store +// str reg, [addr, #imm] @ 0 <= imm < 128 & imm mod 4 = 0 +#define STR_IMM(reg, addr, imm) (0x6000 + (reg) + ((addr) << 3) + ((imm) << 4) ) +// strh reg, [addr, #imm] @ 0 <= imm < 64 & imm mod 2 = 0 +#define STRH_IMM(reg, addr, imm) (0x8000 + (reg) + ((addr) << 3) + ((imm) << 5) ) +// strb reg, [addr, #imm] @ 0 <= imm < 32 +#define STRB_IMM(reg, addr, imm) (0x7000 + (reg) + ((addr) << 3) + ((imm) << 6) ) + +// branch +// beq pc+imm @ 0 <= imm < 256 & imm mod 2 = 0 +#define BEQ_FWD(imm) (0xd000 + ((imm) >> 1) ) +// bne pc+imm @ 0 <= imm < 256 & imm mod 2 = 0 +#define BNE_FWD(imm) (0xd100 + ((imm) >> 1) ) +// bgt pc+imm @ 0 <= imm < 256 & imm mod 2 = 0 +#define BGT_FWD(imm) (0xdc00 + ((imm) >> 1) ) +// b pc+imm @ 0 <= imm < 2048 & imm mod 2 = 0 +#define B_FWD(imm) (0xe000 + ((imm) >> 1) ) +// bx reg +#define BX(reg) (0x4700 + ((reg) << 3) ) + + // data pool defines #define CACHE_DATA_JUMP (2) #define CACHE_DATA_ALIGN (32) @@ -75,6 +166,7 @@ static Bit8u * cache_datapos = NULL; // position of data pool in the cache block static Bit32u cache_datasize = 0; // total size of data pool static Bit32u cache_dataindex = 0; // used size of data pool = index of free data item (in bytes) in data pool + // forwarded function static void INLINE gen_create_branch_short(void * func); @@ -185,26 +277,26 @@ static void cache_block_before_close(void) { static void gen_mov_regs(HostReg reg_dst,HostReg reg_src) { if(reg_src == reg_dst) return; cache_checkinstr(2); - cache_addw(0x1c00 + reg_dst + (reg_src << 3)); // mov reg_dst, reg_src + cache_addw( MOV_REG(reg_dst, reg_src) ); // mov reg_dst, reg_src } // move a 32bit constant value into dest_reg static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) { if ((imm & 0xffffff00) == 0) { cache_checkinstr(2); - cache_addw(0x2000 + (dest_reg << 8) + imm); // mov dest_reg, #(imm) + cache_addw( MOV_IMM(dest_reg, imm) ); // mov dest_reg, #(imm) } else if ((imm & 0xffff00ff) == 0) { cache_checkinstr(4); - cache_addw(0x2000 + (dest_reg << 8) + (imm >> 8)); // mov dest_reg, #(imm >> 8) - cache_addw(0x0000 + dest_reg + (dest_reg << 3) + (8 << 6)); // lsl dest_reg, dest_reg, #8 + cache_addw( MOV_IMM(dest_reg, imm >> 8) ); // mov dest_reg, #(imm >> 8) + cache_addw( LSL_IMM(dest_reg, dest_reg, 8) ); // lsl dest_reg, dest_reg, #8 } else if ((imm & 0xff00ffff) == 0) { cache_checkinstr(4); - cache_addw(0x2000 + (dest_reg << 8) + (imm >> 16)); // mov dest_reg, #(imm >> 16) - cache_addw(0x0000 + dest_reg + (dest_reg << 3) + (16 << 6)); // lsl dest_reg, dest_reg, #16 + cache_addw( MOV_IMM(dest_reg, imm >> 16) ); // mov dest_reg, #(imm >> 16) + cache_addw( LSL_IMM(dest_reg, dest_reg, 16) ); // lsl dest_reg, dest_reg, #16 } else if ((imm & 0x00ffffff) == 0) { cache_checkinstr(4); - cache_addw(0x2000 + (dest_reg << 8) + (imm >> 24)); // mov dest_reg, #(imm >> 24) - cache_addw(0x0000 + dest_reg + (dest_reg << 3) + (24 << 6)); // lsl dest_reg, dest_reg, #24 + cache_addw( MOV_IMM(dest_reg, imm >> 24) ); // mov dest_reg, #(imm >> 24) + cache_addw( LSL_IMM(dest_reg, dest_reg, 24) ); // lsl dest_reg, dest_reg, #24 } else { Bit32u diff; @@ -214,10 +306,10 @@ static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) { if ((diff < 1024) && ((imm & 0x03) == 0)) { if (((Bit32u)cache.pos & 0x03) == 0) { - cache_addw(0xa000 + (dest_reg << 8) + (diff >> 2)); // add dest_reg, pc, #(diff >> 2) + cache_addw( ADD_LO_PC_IMM(dest_reg, diff >> 2) ); // add dest_reg, pc, #(diff >> 2) } else { - cache_addw(0x46c0); // nop - cache_addw(0xa000 + (dest_reg << 8) + ((diff - 2) >> 2)); // add dest_reg, pc, #((diff - 2) >> 2) + cache_addw( NOP ); // nop + cache_addw( ADD_LO_PC_IMM(dest_reg, (diff - 2) >> 2) ); // add dest_reg, pc, #((diff - 2) >> 2) } } else { Bit8u *datapos; @@ -226,9 +318,9 @@ static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) { *(Bit32u*)datapos=imm; if (((Bit32u)cache.pos & 0x03) == 0) { - cache_addw(0x4800 + (dest_reg << 8) + ((datapos - (cache.pos + 4)) >> 2)); // ldr dest_reg, [pc, datapos] + cache_addw( LDR_PC_IMM(dest_reg, datapos - (cache.pos + 4)) ); // ldr dest_reg, [pc, datapos] } else { - cache_addw(0x4800 + (dest_reg << 8) + ((datapos - (cache.pos + 2)) >> 2)); // ldr dest_reg, [pc, datapos] + cache_addw( LDR_PC_IMM(dest_reg, datapos - (cache.pos + 2)) ); // ldr dest_reg, [pc, datapos] } } } @@ -241,35 +333,35 @@ static void gen_mov_word_to_reg_helper(HostReg dest_reg,void* data,bool dword,Ho if ((Bit32u)data & 3) { if ( ((Bit32u)data & 3) == 2 ) { cache_checkinstr(8); - cache_addw(0x8800 + dest_reg + (data_reg << 3)); // ldrh dest_reg, [data_reg] - cache_addw(0x8800 + templo1 + (data_reg << 3) + (2 << 5)); // ldrh templo1, [data_reg, #2] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (16 << 6)); // lsl templo1, templo1, #16 - cache_addw(0x4300 + dest_reg + (templo1 << 3)); // orr dest_reg, templo1 + cache_addw( LDRH_IMM(dest_reg, data_reg, 0) ); // ldrh dest_reg, [data_reg] + cache_addw( LDRH_IMM(templo1, data_reg, 2) ); // ldrh templo1, [data_reg, #2] + cache_addw( LSL_IMM(templo1, templo1, 16) ); // lsl templo1, templo1, #16 + cache_addw( ORR(dest_reg, templo1) ); // orr dest_reg, templo1 } else { cache_checkinstr(16); - cache_addw(0x7800 + dest_reg + (data_reg << 3)); // ldrb dest_reg, [data_reg] - cache_addw(0x1c00 + templo1 + (data_reg << 3) + (1 << 6)); // add templo1, data_reg, #1 - cache_addw(0x8800 + templo1 + (templo1 << 3)); // ldrh templo1, [templo1] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (8 << 6)); // lsl templo1, templo1, #8 - cache_addw(0x4300 + dest_reg + (templo1 << 3)); // orr dest_reg, templo1 - cache_addw(0x7800 + templo1 + (data_reg << 3) + (3 << 6)); // ldrb templo1, [data_reg, #3] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (24 << 6)); // lsl templo1, templo1, #24 - cache_addw(0x4300 + dest_reg + (templo1 << 3)); // orr dest_reg, templo1 + cache_addw( LDRB_IMM(dest_reg, data_reg, 0) ); // ldrb dest_reg, [data_reg] + cache_addw( ADD_IMM3(templo1, data_reg, 1) ); // add templo1, data_reg, #1 + cache_addw( LDRH_IMM(templo1, templo1, 0) ); // ldrh templo1, [templo1] + cache_addw( LSL_IMM(templo1, templo1, 8) ); // lsl templo1, templo1, #8 + cache_addw( ORR(dest_reg, templo1) ); // orr dest_reg, templo1 + cache_addw( LDRB_IMM(templo1, data_reg, 3) ); // ldrb templo1, [data_reg, #3] + cache_addw( LSL_IMM(templo1, templo1, 24) ); // lsl templo1, templo1, #24 + cache_addw( ORR(dest_reg, templo1) ); // orr dest_reg, templo1 } } else { cache_checkinstr(2); - cache_addw(0x6800 + dest_reg + (data_reg << 3)); // ldr dest_reg, [data_reg] + cache_addw( LDR_IMM(dest_reg, data_reg, 0) ); // ldr dest_reg, [data_reg] } } else { if ((Bit32u)data & 1) { cache_checkinstr(8); - cache_addw(0x7800 + dest_reg + (data_reg << 3)); // ldrb dest_reg, [data_reg] - cache_addw(0x7800 + templo1 + (data_reg << 3) + (1 << 6)); // ldrb templo1, [data_reg, #1] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (8 << 6)); // lsl templo1, templo1, #8 - cache_addw(0x4300 + dest_reg + (templo1 << 3)); // orr dest_reg, templo1 + cache_addw( LDRB_IMM(dest_reg, data_reg, 0) ); // ldrb dest_reg, [data_reg] + cache_addw( LDRB_IMM(templo1, data_reg, 1) ); // ldrb templo1, [data_reg, #1] + cache_addw( LSL_IMM(templo1, templo1, 8) ); // lsl templo1, templo1, #8 + cache_addw( ORR(dest_reg, templo1) ); // orr dest_reg, templo1 } else { cache_checkinstr(2); - cache_addw(0x8800 + dest_reg + (data_reg << 3)); // ldrh dest_reg, [data_reg] + cache_addw( LDRH_IMM(dest_reg, data_reg, 0) ); // ldrh dest_reg, [data_reg] } } } @@ -294,37 +386,37 @@ static void gen_mov_word_from_reg_helper(HostReg src_reg,void* dest,bool dword, if ((Bit32u)dest & 3) { if ( ((Bit32u)dest & 3) == 2 ) { cache_checkinstr(8); - cache_addw(0x8000 + src_reg + (data_reg << 3)); // strh src_reg, [data_reg] - cache_addw(0x1c00 + templo1 + (src_reg << 3)); // mov templo1, src_reg - cache_addw(0x0800 + templo1 + (templo1 << 3) + (16 << 6)); // lsr templo1, templo1, #16 - cache_addw(0x8000 + templo1 + (data_reg << 3) + (2 << 5)); // strh templo1, [data_reg, #2] + cache_addw( STRH_IMM(src_reg, data_reg, 0) ); // strh src_reg, [data_reg] + cache_addw( MOV_REG(templo1, src_reg) ); // mov templo1, src_reg + cache_addw( LSR_IMM(templo1, templo1, 16) ); // lsr templo1, templo1, #16 + cache_addw( STRH_IMM(templo1, data_reg, 2) ); // strh templo1, [data_reg, #2] } else { cache_checkinstr(20); - cache_addw(0x7000 + src_reg + (data_reg << 3)); // strb src_reg, [data_reg] - cache_addw(0x1c00 + templo1 + (src_reg << 3)); // mov templo1, src_reg - cache_addw(0x0800 + templo1 + (templo1 << 3) + (8 << 6)); // lsr templo1, templo1, #8 - cache_addw(0x7000 + templo1 + (data_reg << 3) + (1 << 6)); // strb templo1, [data_reg, #1] - cache_addw(0x1c00 + templo1 + (src_reg << 3)); // mov templo1, src_reg - cache_addw(0x0800 + templo1 + (templo1 << 3) + (16 << 6)); // lsr templo1, templo1, #16 - cache_addw(0x7000 + templo1 + (data_reg << 3) + (2 << 6)); // strb templo1, [data_reg, #2] - cache_addw(0x1c00 + templo1 + (src_reg << 3)); // mov templo1, src_reg - cache_addw(0x0800 + templo1 + (templo1 << 3) + (24 << 6)); // lsr templo1, templo1, #24 - cache_addw(0x7000 + templo1 + (data_reg << 3) + (3 << 6)); // strb templo1, [data_reg, #3] + cache_addw( STRB_IMM(src_reg, data_reg, 0) ); // strb src_reg, [data_reg] + cache_addw( MOV_REG(templo1, src_reg) ); // mov templo1, src_reg + cache_addw( LSR_IMM(templo1, templo1, 8) ); // lsr templo1, templo1, #8 + cache_addw( STRB_IMM(templo1, data_reg, 1) ); // strb templo1, [data_reg, #1] + cache_addw( MOV_REG(templo1, src_reg) ); // mov templo1, src_reg + cache_addw( LSR_IMM(templo1, templo1, 16) ); // lsr templo1, templo1, #16 + cache_addw( STRB_IMM(templo1, data_reg, 2) ); // strb templo1, [data_reg, #2] + cache_addw( MOV_REG(templo1, src_reg) ); // mov templo1, src_reg + cache_addw( LSR_IMM(templo1, templo1, 24) ); // lsr templo1, templo1, #24 + cache_addw( STRB_IMM(templo1, data_reg, 3) ); // strb templo1, [data_reg, #3] } } else { cache_checkinstr(2); - cache_addw(0x6000 + src_reg + (data_reg << 3)); // str src_reg, [data_reg] + cache_addw( STR_IMM(src_reg, data_reg, 0) ); // str src_reg, [data_reg] } } else { if ((Bit32u)dest & 1) { cache_checkinstr(8); - cache_addw(0x7000 + src_reg + (data_reg << 3)); // strb src_reg, [data_reg] - cache_addw(0x1c00 + templo1 + (src_reg << 3)); // mov templo1, src_reg - cache_addw(0x0800 + templo1 + (templo1 << 3) + (8 << 6)); // lsr templo1, templo1, #8 - cache_addw(0x7000 + templo1 + (data_reg << 3) + (1 << 6)); // strb templo1, [data_reg, #1] + cache_addw( STRB_IMM(src_reg, data_reg, 0) ); // strb src_reg, [data_reg] + cache_addw( MOV_REG(templo1, src_reg) ); // mov templo1, src_reg + cache_addw( LSR_IMM(templo1, templo1, 8) ); // lsr templo1, templo1, #8 + cache_addw( STRB_IMM(templo1, data_reg, 1) ); // strb templo1, [data_reg, #1] } else { cache_checkinstr(2); - cache_addw(0x8000 + src_reg + (data_reg << 3)); // strh src_reg, [data_reg] + cache_addw( STRH_IMM(src_reg, data_reg, 0) ); // strh src_reg, [data_reg] } } } @@ -342,7 +434,7 @@ static void gen_mov_word_from_reg(HostReg src_reg,void* dest,bool dword) { static void gen_mov_byte_to_reg_low(HostReg dest_reg,void* data) { gen_mov_dword_to_reg_imm(templo1, (Bit32u)data); cache_checkinstr(2); - cache_addw(0x7800 + dest_reg + (templo1 << 3)); // ldrb dest_reg, [templo1] + cache_addw( LDRB_IMM(dest_reg, templo1, 0) ); // ldrb dest_reg, [templo1] } // move an 8bit value from memory into dest_reg @@ -359,7 +451,7 @@ static void INLINE gen_mov_byte_to_reg_low_canuseword(HostReg dest_reg,void* dat // registers might not be directly byte-accessible on some architectures static void gen_mov_byte_to_reg_low_imm(HostReg dest_reg,Bit8u imm) { cache_checkinstr(2); - cache_addw(0x2000 + (dest_reg << 8) + imm); // mov dest_reg, #(imm) + cache_addw( MOV_IMM(dest_reg, imm) ); // mov dest_reg, #(imm) } // move an 8bit constant value into dest_reg @@ -374,7 +466,7 @@ static void INLINE gen_mov_byte_to_reg_low_imm_canuseword(HostReg dest_reg,Bit8u static void gen_mov_byte_from_reg_low(HostReg src_reg,void* dest) { gen_mov_dword_to_reg_imm(templo1, (Bit32u)dest); cache_checkinstr(2); - cache_addw(0x7000 + src_reg + (templo1 << 3)); // strb src_reg, [templo1] + cache_addw( STRB_IMM(src_reg, templo1, 0) ); // strb src_reg, [templo1] } @@ -383,12 +475,12 @@ static void gen_mov_byte_from_reg_low(HostReg src_reg,void* dest) { // the register is zero-extended (sign==false) or sign-extended (sign==true) static void gen_extend_byte(bool sign,HostReg reg) { cache_checkinstr(4); - cache_addw(0x0000 + reg + (reg << 3) + (24 << 6)); // lsl reg, reg, #24 + cache_addw( LSL_IMM(reg, reg, 24) ); // lsl reg, reg, #24 if (sign) { - cache_addw(0x1000 + reg + (reg << 3) + (24 << 6)); // asr reg, reg, #24 + cache_addw( ASR_IMM(reg, reg, 24) ); // asr reg, reg, #24 } else { - cache_addw(0x0800 + reg + (reg << 3) + (24 << 6)); // lsr reg, reg, #24 + cache_addw( LSR_IMM(reg, reg, 24) ); // lsr reg, reg, #24 } } @@ -396,22 +488,22 @@ static void gen_extend_byte(bool sign,HostReg reg) { // the register is zero-extended (sign==false) or sign-extended (sign==true) static void gen_extend_word(bool sign,HostReg reg) { cache_checkinstr(4); - cache_addw(0x0000 + reg + (reg << 3) + (16 << 6)); // lsl reg, reg, #16 + cache_addw( LSL_IMM(reg, reg, 16) ); // lsl reg, reg, #16 if (sign) { - cache_addw(0x1000 + reg + (reg << 3) + (16 << 6)); // asr reg, reg, #16 + cache_addw( ASR_IMM(reg, reg, 16) ); // asr reg, reg, #16 } else { - cache_addw(0x0800 + reg + (reg << 3) + (16 << 6)); // lsr reg, reg, #16 + cache_addw( LSR_IMM(reg, reg, 16) ); // lsr reg, reg, #16 } } // add a 32bit value from memory to a full register static void gen_add(HostReg reg,void* op) { cache_checkinstr(2); - cache_addw(0x4680 + (temphi1 - HOST_r8) + (reg << 3)); // mov temphi1, reg + cache_addw( MOV_HI_LO(temphi1, reg) ); // mov temphi1, reg gen_mov_word_to_reg(reg, op, 1); cache_checkinstr(2); - cache_addw(0x4440 + (reg) + ((temphi1 - HOST_r8) << 3)); // add reg, temphi1 + cache_addw( ADD_LO_HI(reg, temphi1) ); // add reg, temphi1 } // add a 32bit constant value to a full register @@ -419,7 +511,7 @@ static void gen_add_imm(HostReg reg,Bit32u imm) { if(!imm) return; gen_mov_dword_to_reg_imm(templo1, imm); cache_checkinstr(2); - cache_addw(0x1800 + reg + (reg << 3) + (templo1 << 6)); // add reg, reg, templo1 + cache_addw( ADD_REG(reg, reg, templo1) ); // add reg, reg, templo1 } // and a 32bit constant value with a full register @@ -427,18 +519,18 @@ static void gen_and_imm(HostReg reg,Bit32u imm) { if(imm == 0xffffffff) return; gen_mov_dword_to_reg_imm(templo1, imm); cache_checkinstr(2); - cache_addw(0x4000 + reg + (templo1<< 3)); // and reg, templo1 + cache_addw( AND(reg, templo1) ); // and reg, templo1 } // move a 32bit constant value into memory static void gen_mov_direct_dword(void* dest,Bit32u imm) { cache_checkinstr(2); - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_dword_to_reg_imm(templosav, imm); gen_mov_word_from_reg(templosav, dest, 1); cache_checkinstr(2); - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 } // move an address into memory @@ -450,18 +542,18 @@ static void INLINE gen_mov_direct_ptr(void* dest,DRC_PTR_SIZE_IM imm) { static void gen_add_direct_byte(void* dest,Bit8s imm) { if(!imm) return; cache_checkinstr(2); - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_dword_to_reg_imm(templo2, (Bit32u)dest); gen_mov_word_to_reg_helper(templosav, dest, 1, templo2); cache_checkinstr(2); if (imm >= 0) { - cache_addw(0x3000 + (templosav << 8) + ((Bit32s)imm)); // add templosav, #(imm) + cache_addw( ADD_IMM8(templosav, (Bit32s)imm) ); // add templosav, #(imm) } else { - cache_addw(0x3800 + (templosav << 8) + (-((Bit32s)imm))); // sub templosav, #(-imm) + cache_addw( SUB_IMM8(templosav, -((Bit32s)imm)) ); // sub templosav, #(-imm) } gen_mov_word_from_reg_helper(templosav, dest, 1, templo2); cache_checkinstr(2); - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 } // add a 32bit (dword==true) or 16bit (dword==false) constant value to a memory value @@ -472,7 +564,7 @@ static void gen_add_direct_word(void* dest,Bit32u imm,bool dword) { return; } cache_checkinstr(2); - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_dword_to_reg_imm(templo2, (Bit32u)dest); gen_mov_word_to_reg_helper(templosav, dest, dword, templo2); if (dword) { @@ -481,28 +573,28 @@ static void gen_add_direct_word(void* dest,Bit32u imm,bool dword) { gen_mov_word_to_reg_imm(templo1, (Bit16u)imm); } cache_checkinstr(2); - cache_addw(0x1800 + templosav + (templosav << 3) + (templo1 << 6)); // add templosav, templosav, templo1 + cache_addw( ADD_REG(templosav, templosav, templo1) ); // add templosav, templosav, templo1 gen_mov_word_from_reg_helper(templosav, dest, dword, templo2); cache_checkinstr(2); - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 } // subtract an 8bit constant value from a dword memory value static void gen_sub_direct_byte(void* dest,Bit8s imm) { if(!imm) return; cache_checkinstr(2); - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_dword_to_reg_imm(templo2, (Bit32u)dest); gen_mov_word_to_reg_helper(templosav, dest, 1, templo2); cache_checkinstr(2); if (imm >= 0) { - cache_addw(0x3800 + (templosav << 8) + ((Bit32s)imm)); // sub templosav, #(imm) + cache_addw( SUB_IMM8(templosav, (Bit32s)imm) ); // sub templosav, #(imm) } else { - cache_addw(0x3000 + (templosav << 8) + (-((Bit32s)imm))); // add templosav, #(-imm) + cache_addw( ADD_IMM8(templosav, -((Bit32s)imm)) ); // add templosav, #(-imm) } gen_mov_word_from_reg_helper(templosav, dest, 1, templo2); cache_checkinstr(2); - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 } // subtract a 32bit (dword==true) or 16bit (dword==false) constant value from a memory value @@ -513,7 +605,7 @@ static void gen_sub_direct_word(void* dest,Bit32u imm,bool dword) { return; } cache_checkinstr(2); - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_dword_to_reg_imm(templo2, (Bit32u)dest); gen_mov_word_to_reg_helper(templosav, dest, dword, templo2); if (dword) { @@ -522,10 +614,10 @@ static void gen_sub_direct_word(void* dest,Bit32u imm,bool dword) { gen_mov_word_to_reg_imm(templo1, (Bit16u)imm); } cache_checkinstr(2); - cache_addw(0x1a00 + templosav + (templosav << 3) + (templo1 << 6)); // sub templosav, templosav, templo1 + cache_addw( SUB_REG(templosav, templosav, templo1) ); // sub templosav, templosav, templo1 gen_mov_word_from_reg_helper(templosav, dest, dword, templo2); cache_checkinstr(2); - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 } // effective address calculation, destination is dest_reg @@ -534,11 +626,11 @@ static void gen_sub_direct_word(void* dest,Bit32u imm,bool dword) { static INLINE void gen_lea(HostReg dest_reg,HostReg scale_reg,Bitu scale,Bits imm) { if (scale) { cache_checkinstr(4); - cache_addw(0x0000 + templo1 + (scale_reg << 3) + (scale << 6)); // lsl templo1, scale_reg, #(scale) - cache_addw(0x1800 + dest_reg + (dest_reg << 3) + (templo1 << 6)); // add dest_reg, dest_reg, templo1 + cache_addw( LSL_IMM(templo1, scale_reg, scale) ); // lsl templo1, scale_reg, #(scale) + cache_addw( ADD_REG(dest_reg, dest_reg, templo1) ); // add dest_reg, dest_reg, templo1 } else { cache_checkinstr(2); - cache_addw(0x1800 + dest_reg + (dest_reg << 3) + (scale_reg << 6)); // add dest_reg, dest_reg, scale_reg + cache_addw( ADD_REG(dest_reg, dest_reg, scale_reg) ); // add dest_reg, dest_reg, scale_reg } gen_add_imm(dest_reg, imm); } @@ -549,7 +641,7 @@ static INLINE void gen_lea(HostReg dest_reg,HostReg scale_reg,Bitu scale,Bits im static INLINE void gen_lea(HostReg dest_reg,Bitu scale,Bits imm) { if (scale) { cache_checkinstr(2); - cache_addw(0x0000 + dest_reg + (dest_reg << 3) + (scale << 6)); // lsl dest_reg, dest_reg, #(scale) + cache_addw( LSL_IMM(dest_reg, dest_reg, scale) ); // lsl dest_reg, dest_reg, #(scale) } gen_add_imm(dest_reg, imm); } @@ -562,16 +654,16 @@ static void gen_call_function_helper(void * func) { *(Bit32u*)datapos=(Bit32u)func; if (((Bit32u)cache.pos & 0x03) == 0) { - cache_addw(0x4800 + (templo1 << 8) + ((datapos - (cache.pos + 4)) >> 2)); // ldr templo1, [pc, datapos] - cache_addw(0xa000 + (templo2 << 8) + (4 >> 2)); // adr templo2, after_call (add templo2, pc, #4) - cache_addw(0x4680 + (HOST_lr - HOST_r8) + (templo2 << 3)); // mov lr, templo2 - cache_addw(0x4700 + (templo1 << 3)); // bx templo1 --- switch to arm state + cache_addw( LDR_PC_IMM(templo1, datapos - (cache.pos + 4)) ); // ldr templo1, [pc, datapos] + cache_addw( ADD_LO_PC_IMM(templo2, 4) ); // adr templo2, after_call (add templo2, pc, #4) + cache_addw( MOV_HI_LO(HOST_lr, templo2) ); // mov lr, templo2 + cache_addw( BX(templo1) ); // bx templo1 --- switch to arm state } else { - cache_addw(0x4800 + (templo1 << 8) + ((datapos - (cache.pos + 2)) >> 2)); // ldr templo1, [pc, datapos] - cache_addw(0xa000 + (templo2 << 8) + (4 >> 2)); // adr templo2, after_call (add templo2, pc, #4) - cache_addw(0x4680 + (HOST_lr - HOST_r8) + (templo2 << 3)); // mov lr, templo2 - cache_addw(0x4700 + (templo1 << 3)); // bx templo1 --- switch to arm state - cache_addw(0x46c0); // nop + cache_addw( LDR_PC_IMM(templo1, datapos - (cache.pos + 2)) ); // ldr templo1, [pc, datapos] + cache_addw( ADD_LO_PC_IMM(templo2, 4) ); // adr templo2, after_call (add templo2, pc, #4) + cache_addw( MOV_HI_LO(HOST_lr, templo2) ); // mov lr, templo2 + cache_addw( BX(templo1) ); // bx templo1 --- switch to arm state + cache_addw( NOP ); // nop } // after_call: @@ -580,7 +672,7 @@ static void gen_call_function_helper(void * func) { cache_addd(0xe12fff10 + (templo1)); // bx templo1 // thumb state from now on - cache_addw(0x1c00 + FC_RETOP + (HOST_a1 << 3)); // mov FC_RETOP, a1 + cache_addw( MOV_REG(FC_RETOP, HOST_a1) ); // mov FC_RETOP, a1 } // generate a call to a parameterless function @@ -631,42 +723,42 @@ static void INLINE gen_load_param_mem(Bitu mem,Bitu param) { // jump to an address pointed at by ptr, offset is in imm static void gen_jmp_ptr(void * ptr,Bits imm=0) { cache_checkinstr(2); - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_word_to_reg(templosav, ptr, 1); if (imm) { gen_mov_dword_to_reg_imm(templo2, imm); cache_checkinstr(2); - cache_addw(0x1800 + templosav + (templosav << 3) + (templo2 << 6)); // add templosav, templosav, templo2 + cache_addw( ADD_REG(templosav, templosav, templo2) ); // add templosav, templosav, templo2 } #if (1) // (*ptr) should be word aligned if ((imm & 0x03) == 0) { cache_checkinstr(8); - cache_addw(0x6800 + templo2 + (templosav << 3)); // ldr templo2, [templosav] + cache_addw( LDR_IMM(templo2, templosav, 0) ); // ldr templo2, [templosav] } else #endif { cache_checkinstr(26); - cache_addw(0x7800 + templo2 + (templosav << 3)); // ldrb templo2, [templosav] - cache_addw(0x7800 + templo1 + (templosav << 3) + (1 << 6)); // ldrb templo1, [templosav, #1] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (8 << 6)); // lsl templo1, templo1, #8 - cache_addw(0x4300 + templo2 + (templo1 << 3)); // orr templo2, templo1 - cache_addw(0x7800 + templo1 + (templosav << 3) + (2 << 6)); // ldrb templo1, [templosav, #2] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (16 << 6)); // lsl templo1, templo1, #16 - cache_addw(0x4300 + templo2 + (templo1 << 3)); // orr templo2, templo1 - cache_addw(0x7800 + templo1 + (templosav << 3) + (3 << 6)); // ldrb templo1, [templosav, #3] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (24 << 6)); // lsl templo1, templo1, #24 - cache_addw(0x4300 + templo2 + (templo1 << 3)); // orr templo2, templo1 + cache_addw( LDRB_IMM(templo2, templosav, 0) ); // ldrb templo2, [templosav] + cache_addw( LDRB_IMM(templo1, templosav, 1) ); // ldrb templo1, [templosav, #1] + cache_addw( LSL_IMM(templo1, templo1, 8) ); // lsl templo1, templo1, #8 + cache_addw( ORR(templo2, templo1) ); // orr templo2, templo1 + cache_addw( LDRB_IMM(templo1, templosav, 2) ); // ldrb templo1, [templosav, #2] + cache_addw( LSL_IMM(templo1, templo1, 16) ); // lsl templo1, templo1, #16 + cache_addw( ORR(templo2, templo1) ); // orr templo2, templo1 + cache_addw( LDRB_IMM(templo1, templosav, 3) ); // ldrb templo1, [templosav, #3] + cache_addw( LSL_IMM(templo1, templo1, 24) ); // lsl templo1, templo1, #24 + cache_addw( ORR(templo2, templo1) ); // orr templo2, templo1 } // increase jmp address to keep thumb state - cache_addw(0x1c00 + templo2 + (templo2 << 3) + (1 << 6)); // add templo2, templo2, #1 + cache_addw( ADD_IMM3(templo2, templo2, 1) ); // add templo2, templo2, #1 - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 - cache_addw(0x4700 + (templo2 << 3)); // bx templo2 + cache_addw( BX(templo2) ); // bx templo2 } // short conditional jump (+-127 bytes) if register is zero @@ -674,11 +766,11 @@ static void gen_jmp_ptr(void * ptr,Bits imm=0) { static Bit32u gen_create_branch_on_zero(HostReg reg,bool dword) { cache_checkinstr(4); if (dword) { - cache_addw(0x2800 + (reg << 8)); // cmp reg, #0 + cache_addw( CMP_IMM(reg, 0) ); // cmp reg, #0 } else { - cache_addw(0x0000 + templo1 + (reg << 3) + (16 << 6)); // lsl templo1, reg, #16 + cache_addw( LSL_IMM(templo1, reg, 16) ); // lsl templo1, reg, #16 } - cache_addw(0xd000); // beq j + cache_addw( BEQ_FWD(0) ); // beq j return ((Bit32u)cache.pos-2); } @@ -687,11 +779,11 @@ static Bit32u gen_create_branch_on_zero(HostReg reg,bool dword) { static Bit32u gen_create_branch_on_nonzero(HostReg reg,bool dword) { cache_checkinstr(4); if (dword) { - cache_addw(0x2800 + (reg << 8)); // cmp reg, #0 + cache_addw( CMP_IMM(reg, 0) ); // cmp reg, #0 } else { - cache_addw(0x0000 + templo1 + (reg << 3) + (16 << 6)); // lsl templo1, reg, #16 + cache_addw( LSL_IMM(templo1, reg, 16) ); // lsl templo1, reg, #16 } - cache_addw(0xd100); // bne j + cache_addw( BNE_FWD(0) ); // bne j return ((Bit32u)cache.pos-2); } @@ -716,17 +808,17 @@ static Bit32u gen_create_branch_long_nonzero(HostReg reg,bool isdword) { datapos = cache_reservedata(); if (isdword) { - cache_addw(0x2800 + (reg << 8)); // cmp reg, #0 + cache_addw( CMP_IMM(reg, 0) ); // cmp reg, #0 } else { - cache_addw(0x0000 + templo2 + (reg << 3) + (24 << 6)); // lsl templo2, reg, #24 + cache_addw( LSL_IMM(templo2, reg, 24) ); // lsl templo2, reg, #24 } - cache_addw(0xd000 + (2 >> 1)); // beq nobranch (pc+2) + cache_addw( BEQ_FWD(2) ); // beq nobranch (pc+2) if (((Bit32u)cache.pos & 0x03) == 0) { - cache_addw(0x4800 + (templo1 << 8) + ((datapos - (cache.pos + 4)) >> 2)); // ldr templo1, [pc, datapos] + cache_addw( LDR_PC_IMM(templo1, datapos - (cache.pos + 4)) ); // ldr templo1, [pc, datapos] } else { - cache_addw(0x4800 + (templo1 << 8) + ((datapos - (cache.pos + 2)) >> 2)); // ldr templo1, [pc, datapos] + cache_addw( LDR_PC_IMM(templo1, datapos - (cache.pos + 2)) ); // ldr templo1, [pc, datapos] } - cache_addw(0x4700 + (templo1 << 3)); // bx templo1 + cache_addw( BX(templo1) ); // bx templo1 // nobranch: return ((Bit32u)datapos); } @@ -738,14 +830,14 @@ static Bit32u gen_create_branch_long_leqzero(HostReg reg) { cache_checkinstr(8); datapos = cache_reservedata(); - cache_addw(0x2800 + (reg << 8)); // cmp reg, #0 - cache_addw(0xdc00 + (2 >> 1)); // bgt nobranch (pc+2) + cache_addw( CMP_IMM(reg, 0) ); // cmp reg, #0 + cache_addw( BGT_FWD(2) ); // bgt nobranch (pc+2) if (((Bit32u)cache.pos & 0x03) == 0) { - cache_addw(0x4800 + (templo1 << 8) + ((datapos - (cache.pos + 4)) >> 2)); // ldr templo1, [pc, datapos] + cache_addw( LDR_PC_IMM(templo1, datapos - (cache.pos + 4)) ); // ldr templo1, [pc, datapos] } else { - cache_addw(0x4800 + (templo1 << 8) + ((datapos - (cache.pos + 2)) >> 2)); // ldr templo1, [pc, datapos] + cache_addw( LDR_PC_IMM(templo1, datapos - (cache.pos + 2)) ); // ldr templo1, [pc, datapos] } - cache_addw(0x4700 + (templo1 << 3)); // bx templo1 + cache_addw( BX(templo1) ); // bx templo1 // nobranch: return ((Bit32u)datapos); } @@ -763,39 +855,39 @@ static void gen_run_code(void) { // thumb state from now on cache_addw(0xb500); // push {lr} - cache_addw(0x4640 + HOST_r3 + ((FC_SEGS_ADDR - HOST_r8) << 3)); // mov r3, FC_SEGS_ADDR - cache_addw(0x4640 + HOST_r2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov r2, FC_REGS_ADDR + cache_addw( MOV_LO_HI(HOST_r3, FC_SEGS_ADDR) ); // mov r3, FC_SEGS_ADDR + cache_addw( MOV_LO_HI(HOST_r2, FC_REGS_ADDR) ); // mov r2, FC_REGS_ADDR cache_addw(0xb4fc); // push {r2,r3,v1-v4} // adr: 16 - cache_addw(0x4800 + (HOST_r3 << 8) + ((64 - (16 + 4)) >> 2)); // ldr r3, [pc, #(&Segs)] + cache_addw( LDR_PC_IMM(HOST_r3, 64 - (16 + 4)) ); // ldr r3, [pc, #(&Segs)] // adr: 18 - cache_addw(0x4800 + (HOST_r2 << 8) + ((68 - (18 + 2)) >> 2)); // ldr r2, [pc, #(&cpu_regs)] - cache_addw(0x4680 + (FC_SEGS_ADDR - HOST_r8) + (HOST_r3 << 3)); // mov FC_SEGS_ADDR, r3 - cache_addw(0x4680 + (FC_REGS_ADDR - HOST_r8) + (HOST_r2 << 3)); // mov FC_REGS_ADDR, r2 + cache_addw( LDR_PC_IMM(HOST_r2, 68 - (18 + 2)) ); // ldr r2, [pc, #(&cpu_regs)] + cache_addw( MOV_HI_LO(FC_SEGS_ADDR, HOST_r3) ); // mov FC_SEGS_ADDR, r3 + cache_addw( MOV_HI_LO(FC_REGS_ADDR, HOST_r2) ); // mov FC_REGS_ADDR, r2 // align 4 - - cache_addw(0xa302); // add r3, pc, #8 - cache_addw(0x3001); // add r0, #1 - cache_addw(0x3301); // add r3, #1 + cache_addw( ADD_LO_PC_IMM(HOST_r3, 8) ); // add r3, pc, #8 + cache_addw( ADD_IMM8(HOST_r0, 1) ); // add r0, #1 + cache_addw( ADD_IMM8(HOST_r3, 1) ); // add r3, #1 cache_addw(0xb408); // push {r3} - cache_addw(0x4700); // bx r0 - cache_addw(0x46c0); // nop + cache_addw( BX(HOST_r0) ); // bx r0 + cache_addw( NOP ); // nop // align 4 cache_addw(0xbcfc); // pop {r2,r3,v1-v4} - cache_addw(0x4680 + (FC_SEGS_ADDR - HOST_r8) + (HOST_r3 << 3)); // mov FC_SEGS_ADDR, r3 - cache_addw(0x4680 + (FC_REGS_ADDR - HOST_r8) + (HOST_r2 << 3)); // mov FC_REGS_ADDR, r2 + cache_addw( MOV_HI_LO(FC_SEGS_ADDR, HOST_r3) ); // mov FC_SEGS_ADDR, r3 + cache_addw( MOV_HI_LO(FC_REGS_ADDR, HOST_r2) ); // mov FC_REGS_ADDR, r2 cache_addw(0xbc08); // pop {r3} - cache_addw(0x4718); // bx r3 + cache_addw( BX(HOST_r3) ); // bx r3 + // fill up to 64 bytes - cache_addw(0x46c0); // nop - cache_addd(0x46c046c0); // nop, nop - cache_addd(0x46c046c0); // nop, nop - cache_addd(0x46c046c0); // nop, nop - cache_addd(0x46c046c0); // nop, nop + cache_addw( NOP ); // nop + cache_addd( NOP | (NOP << 16) ); // nop, nop + cache_addd( NOP | (NOP << 16) ); // nop, nop + cache_addd( NOP | (NOP << 16) ); // nop, nop + cache_addd( NOP | (NOP << 16) ); // nop, nop // adr: 64 cache_addd((Bit32u)&Segs); // address of "Segs" @@ -806,16 +898,16 @@ static void gen_run_code(void) { // return from a function static void gen_return_function(void) { cache_checkinstr(6); - cache_addw(0x1c00 + HOST_a1 + (FC_RETOP << 3)); // mov a1, FC_RETOP + cache_addw( MOV_REG(HOST_a1, FC_RETOP) ); // mov a1, FC_RETOP cache_addw(0xbc08); // pop {r3} - cache_addw(0x4718); // bx r3 + cache_addw( BX(HOST_r3) ); // bx r3 } // short unconditional jump (over data pool) // must emit at most CACHE_DATA_JUMP bytes static void INLINE gen_create_branch_short(void * func) { - cache_addw(0xe000 + (((Bit32u)func - ((Bit32u)cache.pos + 4)) >> 1) ); // b func + cache_addw( B_FWD((Bit32u)func - ((Bit32u)cache.pos + 4)) ); // b func } @@ -840,35 +932,35 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { case t_ADDb: case t_ADDw: case t_ADDd: - *(Bit16u*)pos=0x1800 + FC_RETOP + (HOST_a1 << 3) + (HOST_a2 << 6); // add FC_RETOP, a1, a2 - *(Bit16u*)(pos+2)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=ADD_REG(FC_RETOP, HOST_a1, HOST_a2); // add FC_RETOP, a1, a2 + *(Bit16u*)(pos+2)=B_FWD(12); // b after_call (pc+12) break; case t_ORb: case t_ORw: case t_ORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4300 + FC_RETOP + (HOST_a2 << 3); // orr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (10 >> 1); // b after_call (pc+10) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ORR(FC_RETOP, HOST_a2); // orr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(10); // b after_call (pc+10) break; case t_ANDb: case t_ANDw: case t_ANDd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4000 + FC_RETOP + (HOST_a2 << 3); // and FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (10 >> 1); // b after_call (pc+10) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=AND(FC_RETOP, HOST_a2); // and FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(10); // b after_call (pc+10) break; case t_SUBb: case t_SUBw: case t_SUBd: - *(Bit16u*)pos=0x1a00 + FC_RETOP + (HOST_a1 << 3) + (HOST_a2 << 6); // sub FC_RETOP, a1, a2 - *(Bit16u*)(pos+2)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=SUB_REG(FC_RETOP, HOST_a1, HOST_a2); // sub FC_RETOP, a1, a2 + *(Bit16u*)(pos+2)=B_FWD(12); // b after_call (pc+12) break; case t_XORb: case t_XORw: case t_XORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4040 + FC_RETOP + (HOST_a2 << 3); // eor FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (10 >> 1); // b after_call (pc+10) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=EOR(FC_RETOP, HOST_a2); // eor FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(10); // b after_call (pc+10) break; case t_CMPb: case t_CMPw: @@ -876,118 +968,118 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { case t_TESTb: case t_TESTw: case t_TESTd: - *(Bit16u*)pos=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=B_FWD(14); // b after_call (pc+14) break; case t_INCb: case t_INCw: case t_INCd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3) + (1 << 6); // add FC_RETOP, a1, #1 - *(Bit16u*)(pos+2)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=ADD_IMM3(FC_RETOP, HOST_a1, 1); // add FC_RETOP, a1, #1 + *(Bit16u*)(pos+2)=B_FWD(12); // b after_call (pc+12) break; case t_DECb: case t_DECw: case t_DECd: - *(Bit16u*)pos=0x1e00 + FC_RETOP + (HOST_a1 << 3) + (1 << 6); // sub FC_RETOP, a1, #1 - *(Bit16u*)(pos+2)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=SUB_IMM3(FC_RETOP, HOST_a1, 1); // sub FC_RETOP, a1, #1 + *(Bit16u*)(pos+2)=B_FWD(12); // b after_call (pc+12) break; case t_SHLb: case t_SHLw: case t_SHLd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4080 + FC_RETOP + (HOST_a2 << 3); // lsl FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (10 >> 1); // b after_call (pc+10) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=LSL_REG(FC_RETOP, HOST_a2); // lsl FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(10); // b after_call (pc+10) break; case t_SHRb: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (24 << 6); // lsl FC_RETOP, a1, #24 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (FC_RETOP << 3) + (24 << 6); // lsr FC_RETOP, FC_RETOP, #24 - *(Bit16u*)(pos+4)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (8 >> 1); // b after_call (pc+8) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 24); // lsl FC_RETOP, a1, #24 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, FC_RETOP, 24); // lsr FC_RETOP, FC_RETOP, #24 + *(Bit16u*)(pos+4)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(8); // b after_call (pc+8) break; case t_SHRw: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsl FC_RETOP, a1, #16 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (FC_RETOP << 3) + (16 << 6); // lsr FC_RETOP, FC_RETOP, #16 - *(Bit16u*)(pos+4)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (8 >> 1); // b after_call (pc+8) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 16); // lsl FC_RETOP, a1, #16 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, FC_RETOP, 16); // lsr FC_RETOP, FC_RETOP, #16 + *(Bit16u*)(pos+4)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(8); // b after_call (pc+8) break; case t_SHRd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (10 >> 1); // b after_call (pc+10) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(10); // b after_call (pc+10) break; case t_SARb: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (24 << 6); // lsl FC_RETOP, a1, #24 - *(Bit16u*)(pos+2)=0x1000 + FC_RETOP + (FC_RETOP << 3) + (24 << 6); // asr FC_RETOP, FC_RETOP, #24 - *(Bit16u*)(pos+4)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (8 >> 1); // b after_call (pc+8) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 24); // lsl FC_RETOP, a1, #24 + *(Bit16u*)(pos+2)=ASR_IMM(FC_RETOP, FC_RETOP, 24); // asr FC_RETOP, FC_RETOP, #24 + *(Bit16u*)(pos+4)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(8); // b after_call (pc+8) break; case t_SARw: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsl FC_RETOP, a1, #16 - *(Bit16u*)(pos+2)=0x1000 + FC_RETOP + (FC_RETOP << 3) + (16 << 6); // asr FC_RETOP, FC_RETOP, #16 - *(Bit16u*)(pos+4)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (8 >> 1); // b after_call (pc+8) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 16); // lsl FC_RETOP, a1, #16 + *(Bit16u*)(pos+2)=ASR_IMM(FC_RETOP, FC_RETOP, 16); // asr FC_RETOP, FC_RETOP, #16 + *(Bit16u*)(pos+4)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(8); // b after_call (pc+8) break; case t_SARd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (10 >> 1); // b after_call (pc+10) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(10); // b after_call (pc+10) break; case t_RORb: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (24 << 6); // lsl a1, a1, #24 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (8 << 6); // lsr FC_RETOP, a1, #8 - *(Bit16u*)(pos+4)=0x4300 + HOST_a1 + (FC_RETOP << 3); // orr a1, FC_RETOP - *(Bit16u*)(pos+6)=0x46c0; // nop - *(Bit16u*)(pos+8)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+10)=0x46c0; // nop - *(Bit16u*)(pos+12)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+14)=0x46c0; // nop - *(Bit16u*)(pos+16)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 24); // lsl a1, a1, #24 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, HOST_a1, 8); // lsr FC_RETOP, a1, #8 + *(Bit16u*)(pos+4)=ORR(HOST_a1, FC_RETOP); // orr a1, FC_RETOP + *(Bit16u*)(pos+6)=NOP; // nop + *(Bit16u*)(pos+8)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+10)=NOP; // nop + *(Bit16u*)(pos+12)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+14)=NOP; // nop + *(Bit16u*)(pos+16)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 break; case t_RORw: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (16 << 6); // lsl a1, a1, #16 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+4)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+6)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 - *(Bit16u*)(pos+8)=0xe000 + (6 >> 1); // b after_call (pc+6) + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 16); // lsl a1, a1, #16 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+4)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+6)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 + *(Bit16u*)(pos+8)=B_FWD(6); // b after_call (pc+6) break; case t_RORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (10 >> 1); // b after_call (pc+10) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(10); // b after_call (pc+10) break; case t_ROLb: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (24 << 6); // lsl a1, a1, #24 - *(Bit16u*)(pos+2)=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+4)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (8 << 6); // lsr FC_RETOP, a1, #8 - *(Bit16u*)(pos+6)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+8)=0x4300 + HOST_a1 + (FC_RETOP << 3); // orr a1, FC_RETOP - *(Bit16u*)(pos+10)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+12)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+14)=0x46c0; // nop - *(Bit16u*)(pos+16)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 24); // lsl a1, a1, #24 + *(Bit16u*)(pos+2)=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+4)=LSR_IMM(FC_RETOP, HOST_a1, 8); // lsr FC_RETOP, a1, #8 + *(Bit16u*)(pos+6)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+8)=ORR(HOST_a1, FC_RETOP); // orr a1, FC_RETOP + *(Bit16u*)(pos+10)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+12)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+14)=NOP; // nop + *(Bit16u*)(pos+16)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 break; case t_ROLw: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (16 << 6); // lsl a1, a1, #16 - *(Bit16u*)(pos+2)=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+4)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+6)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+8)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+10)=0x46c0; // nop - *(Bit16u*)(pos+12)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 - *(Bit16u*)(pos+14)=0x46c0; // nop - *(Bit16u*)(pos+16)=0x46c0; // nop + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 16); // lsl a1, a1, #16 + *(Bit16u*)(pos+2)=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+4)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+6)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+8)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+10)=NOP; // nop + *(Bit16u*)(pos+12)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 + *(Bit16u*)(pos+14)=NOP; // nop + *(Bit16u*)(pos+16)=NOP; // nop break; case t_ROLd: - *(Bit16u*)pos=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+2)=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+4)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+6)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 - *(Bit16u*)(pos+8)=0xe000 + (6 >> 1); // b after_call (pc+6) + *(Bit16u*)pos=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+2)=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+4)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+6)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 + *(Bit16u*)(pos+8)=B_FWD(6); // b after_call (pc+6) break; case t_NEGb: case t_NEGw: case t_NEGd: - *(Bit16u*)pos=0x4240 + FC_RETOP + (HOST_a1 << 3); // neg FC_RETOP, a1 - *(Bit16u*)(pos+2)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=NEG(FC_RETOP, HOST_a1); // neg FC_RETOP, a1 + *(Bit16u*)(pos+2)=B_FWD(12); // b after_call (pc+12) break; default: *(Bit32u*)( ( ((Bit32u) (*pos)) << 2 ) + ((Bit32u)pos + 4) ) = (Bit32u)fct_ptr; // simple_func @@ -1001,35 +1093,35 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { case t_ADDb: case t_ADDw: case t_ADDd: - *(Bit16u*)pos=0x1800 + FC_RETOP + (HOST_a1 << 3) + (HOST_a2 << 6); // add FC_RETOP, a1, a2 - *(Bit16u*)(pos+2)=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=ADD_REG(FC_RETOP, HOST_a1, HOST_a2); // add FC_RETOP, a1, a2 + *(Bit16u*)(pos+2)=B_FWD(14); // b after_call (pc+14) break; case t_ORb: case t_ORw: case t_ORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4300 + FC_RETOP + (HOST_a2 << 3); // orr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ORR(FC_RETOP, HOST_a2); // orr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(12); // b after_call (pc+12) break; case t_ANDb: case t_ANDw: case t_ANDd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4000 + FC_RETOP + (HOST_a2 << 3); // and FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=AND(FC_RETOP, HOST_a2); // and FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(12); // b after_call (pc+12) break; case t_SUBb: case t_SUBw: case t_SUBd: - *(Bit16u*)pos=0x1a00 + FC_RETOP + (HOST_a1 << 3) + (HOST_a2 << 6); // sub FC_RETOP, a1, a2 - *(Bit16u*)(pos+2)=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=SUB_REG(FC_RETOP, HOST_a1, HOST_a2); // sub FC_RETOP, a1, a2 + *(Bit16u*)(pos+2)=B_FWD(14); // b after_call (pc+14) break; case t_XORb: case t_XORw: case t_XORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4040 + FC_RETOP + (HOST_a2 << 3); // eor FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=EOR(FC_RETOP, HOST_a2); // eor FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(12); // b after_call (pc+12) break; case t_CMPb: case t_CMPw: @@ -1037,115 +1129,115 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { case t_TESTb: case t_TESTw: case t_TESTd: - *(Bit16u*)pos=0xe000 + (16 >> 1); // b after_call (pc+16) + *(Bit16u*)pos=B_FWD(16); // b after_call (pc+16) break; case t_INCb: case t_INCw: case t_INCd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3) + (1 << 6); // add FC_RETOP, a1, #1 - *(Bit16u*)(pos+2)=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=ADD_IMM3(FC_RETOP, HOST_a1, 1); // add FC_RETOP, a1, #1 + *(Bit16u*)(pos+2)=B_FWD(14); // b after_call (pc+14) break; case t_DECb: case t_DECw: case t_DECd: - *(Bit16u*)pos=0x1e00 + FC_RETOP + (HOST_a1 << 3) + (1 << 6); // sub FC_RETOP, a1, #1 - *(Bit16u*)(pos+2)=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=SUB_IMM3(FC_RETOP, HOST_a1, 1); // sub FC_RETOP, a1, #1 + *(Bit16u*)(pos+2)=B_FWD(14); // b after_call (pc+14) break; case t_SHLb: case t_SHLw: case t_SHLd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4080 + FC_RETOP + (HOST_a2 << 3); // lsl FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=LSL_REG(FC_RETOP, HOST_a2); // lsl FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(12); // b after_call (pc+12) break; case t_SHRb: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (24 << 6); // lsl FC_RETOP, a1, #24 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (FC_RETOP << 3) + (24 << 6); // lsr FC_RETOP, FC_RETOP, #24 - *(Bit16u*)(pos+4)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (10 >> 1); // b after_call (pc+10) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 24); // lsl FC_RETOP, a1, #24 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, FC_RETOP, 24); // lsr FC_RETOP, FC_RETOP, #24 + *(Bit16u*)(pos+4)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(10); // b after_call (pc+10) break; case t_SHRw: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsl FC_RETOP, a1, #16 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (FC_RETOP << 3) + (16 << 6); // lsr FC_RETOP, FC_RETOP, #16 - *(Bit16u*)(pos+4)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (10 >> 1); // b after_call (pc+10) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 16); // lsl FC_RETOP, a1, #16 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, FC_RETOP, 16); // lsr FC_RETOP, FC_RETOP, #16 + *(Bit16u*)(pos+4)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(10); // b after_call (pc+10) break; case t_SHRd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(12); // b after_call (pc+12) break; case t_SARb: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (24 << 6); // lsl FC_RETOP, a1, #24 - *(Bit16u*)(pos+2)=0x1000 + FC_RETOP + (FC_RETOP << 3) + (24 << 6); // asr FC_RETOP, FC_RETOP, #24 - *(Bit16u*)(pos+4)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (10 >> 1); // b after_call (pc+10) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 24); // lsl FC_RETOP, a1, #24 + *(Bit16u*)(pos+2)=ASR_IMM(FC_RETOP, FC_RETOP, 24); // asr FC_RETOP, FC_RETOP, #24 + *(Bit16u*)(pos+4)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(10); // b after_call (pc+10) break; case t_SARw: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsl FC_RETOP, a1, #16 - *(Bit16u*)(pos+2)=0x1000 + FC_RETOP + (FC_RETOP << 3) + (16 << 6); // asr FC_RETOP, FC_RETOP, #16 - *(Bit16u*)(pos+4)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (10 >> 1); // b after_call (pc+10) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 16); // lsl FC_RETOP, a1, #16 + *(Bit16u*)(pos+2)=ASR_IMM(FC_RETOP, FC_RETOP, 16); // asr FC_RETOP, FC_RETOP, #16 + *(Bit16u*)(pos+4)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(10); // b after_call (pc+10) break; case t_SARd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(12); // b after_call (pc+12) break; case t_RORb: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (24 << 6); // lsl a1, a1, #24 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (8 << 6); // lsr FC_RETOP, a1, #8 - *(Bit16u*)(pos+4)=0x4300 + HOST_a1 + (FC_RETOP << 3); // orr a1, FC_RETOP - *(Bit16u*)(pos+6)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+8)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+10)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 - *(Bit16u*)(pos+12)=0xe000 + (4 >> 1); // b after_call (pc+4) + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 24); // lsl a1, a1, #24 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, HOST_a1, 8); // lsr FC_RETOP, a1, #8 + *(Bit16u*)(pos+4)=ORR(HOST_a1, FC_RETOP); // orr a1, FC_RETOP + *(Bit16u*)(pos+6)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+8)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+10)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 + *(Bit16u*)(pos+12)=B_FWD(4); // b after_call (pc+4) break; case t_RORw: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (16 << 6); // lsl a1, a1, #16 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+4)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+6)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 - *(Bit16u*)(pos+8)=0xe000 + (8 >> 1); // b after_call (pc+8) + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 16); // lsl a1, a1, #16 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+4)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+6)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 + *(Bit16u*)(pos+8)=B_FWD(8); // b after_call (pc+8) break; case t_RORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(12); // b after_call (pc+12) break; case t_ROLb: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (24 << 6); // lsl a1, a1, #24 - *(Bit16u*)(pos+2)=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+4)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (8 << 6); // lsr FC_RETOP, a1, #8 - *(Bit16u*)(pos+6)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+8)=0x4300 + HOST_a1 + (FC_RETOP << 3); // orr a1, FC_RETOP - *(Bit16u*)(pos+10)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+12)=0x46c0; // nop - *(Bit16u*)(pos+14)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+16)=0x46c0; // nop - *(Bit16u*)(pos+18)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 24); // lsl a1, a1, #24 + *(Bit16u*)(pos+2)=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+4)=LSR_IMM(FC_RETOP, HOST_a1, 8); // lsr FC_RETOP, a1, #8 + *(Bit16u*)(pos+6)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+8)=ORR(HOST_a1, FC_RETOP); // orr a1, FC_RETOP + *(Bit16u*)(pos+10)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+12)=NOP; // nop + *(Bit16u*)(pos+14)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+16)=NOP; // nop + *(Bit16u*)(pos+18)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 break; case t_ROLw: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (16 << 6); // lsl a1, a1, #16 - *(Bit16u*)(pos+2)=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+4)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+6)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+8)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+10)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 - *(Bit16u*)(pos+12)=0xe000 + (4 >> 1); // b after_call (pc+4) + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 16); // lsl a1, a1, #16 + *(Bit16u*)(pos+2)=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+4)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+6)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+8)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+10)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 + *(Bit16u*)(pos+12)=B_FWD(4); // b after_call (pc+4) break; case t_ROLd: - *(Bit16u*)pos=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+2)=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+4)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+6)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 - *(Bit16u*)(pos+8)=0xe000 + (8 >> 1); // b after_call (pc+8) + *(Bit16u*)pos=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+2)=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+4)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+6)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 + *(Bit16u*)(pos+8)=B_FWD(8); // b after_call (pc+8) break; case t_NEGb: case t_NEGw: case t_NEGd: - *(Bit16u*)pos=0x4240 + FC_RETOP + (HOST_a1 << 3); // neg FC_RETOP, a1 - *(Bit16u*)(pos+2)=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=NEG(FC_RETOP, HOST_a1); // neg FC_RETOP, a1 + *(Bit16u*)(pos+2)=B_FWD(14); // b after_call (pc+14) break; default: *(Bit32u*)( ( ((Bit32u) (*pos)) << 2 ) + ((Bit32u)pos + 2) ) = (Bit32u)fct_ptr; // simple_func @@ -1172,23 +1264,23 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { // 16bit moves may destroy the upper 16bit of the destination register static void gen_mov_seg16_to_reg(HostReg dest_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo1 + ((FC_SEGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_SEGS_ADDR - cache_addw(0x8800 + dest_reg + (templo1 << 3) + (index << 5)); // ldrh dest_reg, [templo1, #index] + cache_addw( MOV_LO_HI(templo1, FC_SEGS_ADDR) ); // mov templo1, FC_SEGS_ADDR + cache_addw( LDRH_IMM(dest_reg, templo1, index) ); // ldrh dest_reg, [templo1, #index] } // mov 32bit value from Segs[index] into dest_reg using FC_SEGS_ADDR (index modulo 4 must be zero) static void gen_mov_seg32_to_reg(HostReg dest_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo1 + ((FC_SEGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_SEGS_ADDR - cache_addw(0x6800 + dest_reg + (templo1 << 3) + (index << 4)); // ldr dest_reg, [templo1, #index] + cache_addw( MOV_LO_HI(templo1, FC_SEGS_ADDR) ); // mov templo1, FC_SEGS_ADDR + cache_addw( LDR_IMM(dest_reg, templo1, index) ); // ldr dest_reg, [templo1, #index] } // add a 32bit value from Segs[index] to a full register using FC_SEGS_ADDR (index modulo 4 must be zero) static void gen_add_seg32_to_reg(HostReg reg,Bitu index) { cache_checkinstr(6); - cache_addw(0x4640 + templo1 + ((FC_SEGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_SEGS_ADDR - cache_addw(0x6800 + templo2 + (templo1 << 3) + (index << 4)); // ldr templo2, [templo1, #index] - cache_addw(0x1800 + reg + (reg << 3) + (templo2 << 6)); // add reg, reg, templo2 + cache_addw( MOV_LO_HI(templo1, FC_SEGS_ADDR) ); // mov templo1, FC_SEGS_ADDR + cache_addw( LDR_IMM(templo2, templo1, index) ); // ldr templo2, [templo1, #index] + cache_addw( ADD_REG(reg, reg, templo2) ); // add reg, reg, templo2 } #endif @@ -1199,26 +1291,26 @@ static void gen_add_seg32_to_reg(HostReg reg,Bitu index) { // 16bit moves may destroy the upper 16bit of the destination register static void gen_mov_regval16_to_reg(HostReg dest_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR - cache_addw(0x8800 + dest_reg + (templo2 << 3) + (index << 5)); // ldrh dest_reg, [templo2, #index] + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR + cache_addw( LDRH_IMM(dest_reg, templo2, index) ); // ldrh dest_reg, [templo2, #index] } // mov 32bit value from cpu_regs[index] into dest_reg using FC_REGS_ADDR (index modulo 4 must be zero) static void gen_mov_regval32_to_reg(HostReg dest_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR - cache_addw(0x6800 + dest_reg + (templo2 << 3) + (index << 4)); // ldr dest_reg, [templo2, #index] + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR + cache_addw( LDR_IMM(dest_reg, templo2, index) ); // ldr dest_reg, [templo2, #index] } // move a 32bit (dword==true) or 16bit (dword==false) value from cpu_regs[index] into dest_reg using FC_REGS_ADDR (if dword==true index modulo 4 must be zero) (if dword==false index modulo 2 must be zero) // 16bit moves may destroy the upper 16bit of the destination register static void gen_mov_regword_to_reg(HostReg dest_reg,Bitu index,bool dword) { cache_checkinstr(4); - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR if (dword) { - cache_addw(0x6800 + dest_reg + (templo2 << 3) + (index << 4)); // ldr dest_reg, [templo2, #index] + cache_addw( LDR_IMM(dest_reg, templo2, index) ); // ldr dest_reg, [templo2, #index] } else { - cache_addw(0x8800 + dest_reg + (templo2 << 3) + (index << 5)); // ldrh dest_reg, [templo2, #index] + cache_addw( LDRH_IMM(dest_reg, templo2, index) ); // ldrh dest_reg, [templo2, #index] } } @@ -1228,8 +1320,8 @@ static void gen_mov_regword_to_reg(HostReg dest_reg,Bitu index,bool dword) { // registers might not be directly byte-accessible on some architectures static void gen_mov_regbyte_to_reg_low(HostReg dest_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR - cache_addw(0x7800 + dest_reg + (templo2 << 3) + (index << 6)); // ldrb dest_reg, [templo2, #index] + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR + cache_addw( LDRB_IMM(dest_reg, templo2, index) ); // ldrb dest_reg, [templo2, #index] } // move an 8bit value from cpu_regs[index] into dest_reg using FC_REGS_ADDR @@ -1238,49 +1330,50 @@ static void gen_mov_regbyte_to_reg_low(HostReg dest_reg,Bitu index) { // not directly byte-accessible on some architectures static void INLINE gen_mov_regbyte_to_reg_low_canuseword(HostReg dest_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR - cache_addw(0x7800 + dest_reg + (templo2 << 3) + (index << 6)); // ldrb dest_reg, [templo2, #index] + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR + cache_addw( LDRB_IMM(dest_reg, templo2, index) ); // ldrb dest_reg, [templo2, #index] } // add a 32bit value from cpu_regs[index] to a full register using FC_REGS_ADDR (index modulo 4 must be zero) static void gen_add_regval32_to_reg(HostReg reg,Bitu index) { cache_checkinstr(6); - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR - cache_addw(0x6800 + templo1 + (templo2 << 3) + (index << 4)); // ldr templo1, [templo2, #index] - cache_addw(0x1800 + reg + (reg << 3) + (templo1 << 6)); // add reg, reg, templo1 + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR + cache_addw( LDR_IMM(templo1, templo2, index) ); // ldr templo1, [templo2, #index] + cache_addw( ADD_REG(reg, reg, templo1) ); // add reg, reg, templo1 } // move 16bit of register into cpu_regs[index] using FC_REGS_ADDR (index modulo 2 must be zero) static void gen_mov_regval16_from_reg(HostReg src_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo1 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_REGS_ADDR - cache_addw(0x8000 + src_reg + (templo1 << 3) + (index << 5)); // strh src_reg, [templo1, #index] + cache_addw( MOV_LO_HI(templo1, FC_REGS_ADDR) ); // mov templo1, FC_REGS_ADDR + cache_addw( STRH_IMM(src_reg, templo1, index) ); // strh src_reg, [templo1, #index] } // move 32bit of register into cpu_regs[index] using FC_REGS_ADDR (index modulo 4 must be zero) static void gen_mov_regval32_from_reg(HostReg src_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo1 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_REGS_ADDR - cache_addw(0x6000 + src_reg + (templo1 << 3) + (index << 4)); // str src_reg, [templo1, #index] + cache_addw( MOV_LO_HI(templo1, FC_REGS_ADDR) ); // mov templo1, FC_REGS_ADDR + cache_addw( STR_IMM(src_reg, templo1, index) ); // str src_reg, [templo1, #index] } // move 32bit (dword==true) or 16bit (dword==false) of a register into cpu_regs[index] using FC_REGS_ADDR (if dword==true index modulo 4 must be zero) (if dword==false index modulo 2 must be zero) static void gen_mov_regword_from_reg(HostReg src_reg,Bitu index,bool dword) { cache_checkinstr(4); - cache_addw(0x4640 + templo1 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_REGS_ADDR + cache_addw( MOV_LO_HI(templo1, FC_REGS_ADDR) ); // mov templo1, FC_REGS_ADDR if (dword) { - cache_addw(0x6000 + src_reg + (templo1 << 3) + (index << 4)); // str src_reg, [templo1, #index] + cache_addw( STR_IMM(src_reg, templo1, index) ); // str src_reg, [templo1, #index] } else { - cache_addw(0x8000 + src_reg + (templo1 << 3) + (index << 5)); // strh src_reg, [templo1, #index] + cache_addw( STRH_IMM(src_reg, templo1, index) ); // strh src_reg, [templo1, #index] } } // move the lowest 8bit of a register into cpu_regs[index] using FC_REGS_ADDR static void gen_mov_regbyte_from_reg_low(HostReg src_reg,Bitu index) { cache_checkinstr(4); - cache_addw(0x4640 + templo1 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_REGS_ADDR - cache_addw(0x7000 + src_reg + (templo1 << 3) + (index << 6)); // strb src_reg, [templo1, #index] + cache_addw( MOV_LO_HI(templo1, FC_REGS_ADDR) ); // mov templo1, FC_REGS_ADDR + cache_addw( STRB_IMM(src_reg, templo1, index) ); // strb src_reg, [templo1, #index] } + #endif diff --git a/src/cpu/core_dynrec/risc_armv4le-thumb.h b/src/cpu/core_dynrec/risc_armv4le-thumb.h index 4ed007b..aaeea90 100644 --- a/src/cpu/core_dynrec/risc_armv4le-thumb.h +++ b/src/cpu/core_dynrec/risc_armv4le-thumb.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2002-2008 The DOSBox Team + * Copyright (C) 2002-2009 The DOSBox Team * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,7 +16,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $Id: risc_armv4le-thumb.h,v 1.3 2008/09/19 16:48:03 c2woody Exp $ */ +/* $Id: risc_armv4le-thumb.h,v 1.4 2009/05/16 21:52:47 c2woody Exp $ */ /* ARMv4 (little endian) backend by M-HT (thumb version) */ @@ -63,25 +63,117 @@ #define FC_SEGS_ADDR HOST_v8 #endif + +// instruction encodings + +// move +// mov dst, #imm @ 0 <= imm <= 255 +#define MOV_IMM(dst, imm) (0x2000 + ((dst) << 8) + (imm) ) +// mov dst, src +#define MOV_REG(dst, src) ADD_IMM3(dst, src, 0) +// mov dst, src +#define MOV_LO_HI(dst, src) (0x4640 + (dst) + (((src) - HOST_r8) << 3) ) +// mov dst, src +#define MOV_HI_LO(dst, src) (0x4680 + ((dst) - HOST_r8) + ((src) << 3) ) + +// arithmetic +// add dst, src, #imm @ 0 <= imm <= 7 +#define ADD_IMM3(dst, src, imm) (0x1c00 + (dst) + ((src) << 3) + ((imm) << 6) ) +// add dst, #imm @ 0 <= imm <= 255 +#define ADD_IMM8(dst, imm) (0x3000 + ((dst) << 8) + (imm) ) +// add dst, src1, src2 +#define ADD_REG(dst, src1, src2) (0x1800 + (dst) + ((src1) << 3) + ((src2) << 6) ) +// add dst, src +#define ADD_LO_HI(dst, src) (0x4440 + (dst) + (((src) - HOST_r8) << 3) ) +// add dst, pc, #imm @ 0 <= imm < 1024 & imm mod 4 = 0 +#define ADD_LO_PC_IMM(dst, imm) (0xa000 + ((dst) << 8) + ((imm) >> 2) ) +// sub dst, src1, src2 +#define SUB_REG(dst, src1, src2) (0x1a00 + (dst) + ((src1) << 3) + ((src2) << 6) ) +// sub dst, src, #imm @ 0 <= imm <= 7 +#define SUB_IMM3(dst, src, imm) (0x1e00 + (dst) + ((src) << 3) + ((imm) << 6) ) +// sub dst, #imm @ 0 <= imm <= 255 +#define SUB_IMM8(dst, imm) (0x3800 + ((dst) << 8) + (imm) ) +// neg dst, src +#define NEG(dst, src) (0x4240 + (dst) + ((src) << 3) ) +// cmp dst, #imm @ 0 <= imm <= 255 +#define CMP_IMM(dst, imm) (0x2800 + ((dst) << 8) + (imm) ) +// nop +#define NOP (0x46c0) + +// logical +// and dst, src +#define AND(dst, src) (0x4000 + (dst) + ((src) << 3) ) +// eor dst, src +#define EOR(dst, src) (0x4040 + (dst) + ((src) << 3) ) +// orr dst, src +#define ORR(dst, src) (0x4300 + (dst) + ((src) << 3) ) + +// shift/rotate +// lsl dst, src, #imm +#define LSL_IMM(dst, src, imm) (0x0000 + (dst) + ((src) << 3) + ((imm) << 6) ) +// lsl dst, reg +#define LSL_REG(dst, reg) (0x4080 + (dst) + ((reg) << 3) ) +// lsr dst, src, #imm +#define LSR_IMM(dst, src, imm) (0x0800 + (dst) + ((src) << 3) + ((imm) << 6) ) +// lsr dst, reg +#define LSR_REG(dst, reg) (0x40c0 + (dst) + ((reg) << 3) ) +// asr dst, src, #imm +#define ASR_IMM(dst, src, imm) (0x1000 + (dst) + ((src) << 3) + ((imm) << 6) ) +// asr dst, reg +#define ASR_REG(dst, reg) (0x4100 + (dst) + ((reg) << 3) ) +// ror dst, reg +#define ROR_REG(dst, reg) (0x41c0 + (dst) + ((reg) << 3) ) + +// load +// ldr reg, [addr, #imm] @ 0 <= imm < 128 & imm mod 4 = 0 +#define LDR_IMM(reg, addr, imm) (0x6800 + (reg) + ((addr) << 3) + ((imm) << 4) ) +// ldrh reg, [addr, #imm] @ 0 <= imm < 64 & imm mod 2 = 0 +#define LDRH_IMM(reg, addr, imm) (0x8800 + (reg) + ((addr) << 3) + ((imm) << 5) ) +// ldrb reg, [addr, #imm] @ 0 <= imm < 32 +#define LDRB_IMM(reg, addr, imm) (0x7800 + (reg) + ((addr) << 3) + ((imm) << 6) ) +// ldr reg, [pc, #imm] @ 0 <= imm < 1024 & imm mod 4 = 0 +#define LDR_PC_IMM(reg, imm) (0x4800 + ((reg) << 8) + ((imm) >> 2) ) + +// store +// str reg, [addr, #imm] @ 0 <= imm < 128 & imm mod 4 = 0 +#define STR_IMM(reg, addr, imm) (0x6000 + (reg) + ((addr) << 3) + ((imm) << 4) ) +// strh reg, [addr, #imm] @ 0 <= imm < 64 & imm mod 2 = 0 +#define STRH_IMM(reg, addr, imm) (0x8000 + (reg) + ((addr) << 3) + ((imm) << 5) ) +// strb reg, [addr, #imm] @ 0 <= imm < 32 +#define STRB_IMM(reg, addr, imm) (0x7000 + (reg) + ((addr) << 3) + ((imm) << 6) ) + +// branch +// beq pc+imm @ 0 <= imm < 256 & imm mod 2 = 0 +#define BEQ_FWD(imm) (0xd000 + ((imm) >> 1) ) +// bne pc+imm @ 0 <= imm < 256 & imm mod 2 = 0 +#define BNE_FWD(imm) (0xd100 + ((imm) >> 1) ) +// bgt pc+imm @ 0 <= imm < 256 & imm mod 2 = 0 +#define BGT_FWD(imm) (0xdc00 + ((imm) >> 1) ) +// b pc+imm @ 0 <= imm < 2048 & imm mod 2 = 0 +#define B_FWD(imm) (0xe000 + ((imm) >> 1) ) +// bx reg +#define BX(reg) (0x4700 + ((reg) << 3) ) + + // move a full register from reg_src to reg_dst static void gen_mov_regs(HostReg reg_dst,HostReg reg_src) { if(reg_src == reg_dst) return; - cache_addw(0x1c00 + reg_dst + (reg_src << 3)); // mov reg_dst, reg_src + cache_addw( MOV_REG(reg_dst, reg_src) ); // mov reg_dst, reg_src } // move a 32bit constant value into dest_reg static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) { if ((imm & 0xffffff00) == 0) { - cache_addw(0x2000 + (dest_reg << 8) + (Bit8u)(imm & 0xff)); // mov dest_reg, #(imm) + cache_addw( MOV_IMM(dest_reg, imm) ); // mov dest_reg, #(imm) } else if ((imm & 0xffff00ff) == 0) { - cache_addw(0x2000 + (dest_reg << 8) + (Bit8u)(imm >> 8)); // mov dest_reg, #(imm >> 8) - cache_addw(0x0000 + dest_reg + (dest_reg << 3) + (8 << 6)); // lsl dest_reg, dest_reg, #8 + cache_addw( MOV_IMM(dest_reg, imm >> 8) ); // mov dest_reg, #(imm >> 8) + cache_addw( LSL_IMM(dest_reg, dest_reg, 8) ); // lsl dest_reg, dest_reg, #8 } else if ((imm & 0xff00ffff) == 0) { - cache_addw(0x2000 + (dest_reg << 8) + (imm >> 16)); // mov dest_reg, #(imm >> 16) - cache_addw(0x0000 + dest_reg + (dest_reg << 3) + (16 << 6)); // lsl dest_reg, dest_reg, #16 + cache_addw( MOV_IMM(dest_reg, imm >> 16) ); // mov dest_reg, #(imm >> 16) + cache_addw( LSL_IMM(dest_reg, dest_reg, 16) ); // lsl dest_reg, dest_reg, #16 } else if ((imm & 0x00ffffff) == 0) { - cache_addw(0x2000 + (dest_reg << 8) + (imm >> 24)); // mov dest_reg, #(imm >> 24) - cache_addw(0x0000 + dest_reg + (dest_reg << 3) + (24 << 6)); // lsl dest_reg, dest_reg, #24 + cache_addw( MOV_IMM(dest_reg, imm >> 24) ); // mov dest_reg, #(imm >> 24) + cache_addw( LSL_IMM(dest_reg, dest_reg, 24) ); // lsl dest_reg, dest_reg, #24 } else { Bit32u diff; @@ -89,21 +181,21 @@ static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) { if ((diff < 1024) && ((imm & 0x03) == 0)) { if (((Bit32u)cache.pos & 0x03) == 0) { - cache_addw(0xa000 + (dest_reg << 8) + (Bit8u)(diff >> 2)); // add dest_reg, pc, #(dist >> 2) + cache_addw( ADD_LO_PC_IMM(dest_reg, diff) ); // add dest_reg, pc, #(diff >> 2) } else { - cache_addw(0x46c0); // nop - cache_addw(0xa000 + (dest_reg << 8) + (Bit8u)((diff - 2) >> 2)); // add dest_reg, pc, #((dist - 2) >> 2) + cache_addw( NOP ); // nop + cache_addw( ADD_LO_PC_IMM(dest_reg, diff - 2) ); // add dest_reg, pc, #((diff - 2) >> 2) } } else { if (((Bit32u)cache.pos & 0x03) == 0) { - cache_addw(0x4800 + (dest_reg << 8)); // ldr dest_reg, [pc, #0] - cache_addw(0xe000 + (2 >> 1)); // b next_code (pc+2) + cache_addw( LDR_PC_IMM(dest_reg, 0) ); // ldr dest_reg, [pc, #0] + cache_addw( B_FWD(2) ); // b next_code (pc+2) cache_addd(imm); // .int imm // next_code: } else { - cache_addw(0x4800 + (dest_reg << 8) + (4 >> 2)); // ldr dest_reg, [pc, #4] - cache_addw(0xe000 + (4 >> 1)); // b next_code (pc+4) - cache_addw(0x46c0); // nop + cache_addw( LDR_PC_IMM(dest_reg, 4) ); // ldr dest_reg, [pc, #4] + cache_addw( B_FWD(4) ); // b next_code (pc+4) + cache_addw( NOP ); // nop cache_addd(imm); // .int imm // next_code: } @@ -117,31 +209,31 @@ static void gen_mov_word_to_reg_helper(HostReg dest_reg,void* data,bool dword,Ho if (dword) { if ((Bit32u)data & 3) { if ( ((Bit32u)data & 3) == 2 ) { - cache_addw(0x8800 + dest_reg + (data_reg << 3)); // ldrh dest_reg, [data_reg] - cache_addw(0x8800 + templo1 + (data_reg << 3) + (2 << 5)); // ldrh templo1, [data_reg, #2] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (16 << 6)); // lsl templo1, templo1, #16 - cache_addw(0x4300 + dest_reg + (templo1 << 3)); // orr dest_reg, templo1 + cache_addw( LDRH_IMM(dest_reg, data_reg, 0) ); // ldrh dest_reg, [data_reg] + cache_addw( LDRH_IMM(templo1, data_reg, 2) ); // ldrh templo1, [data_reg, #2] + cache_addw( LSL_IMM(templo1, templo1, 16) ); // lsl templo1, templo1, #16 + cache_addw( ORR(dest_reg, templo1) ); // orr dest_reg, templo1 } else { - cache_addw(0x7800 + dest_reg + (data_reg << 3)); // ldrb dest_reg, [data_reg] - cache_addw(0x1c00 + templo1 + (data_reg << 3) + (1 << 6)); // add templo1, data_reg, #1 - cache_addw(0x8800 + templo1 + (templo1 << 3)); // ldrh templo1, [templo1] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (8 << 6)); // lsl templo1, templo1, #8 - cache_addw(0x4300 + dest_reg + (templo1 << 3)); // orr dest_reg, templo1 - cache_addw(0x7800 + templo1 + (data_reg << 3) + (3 << 6)); // ldrb templo1, [data_reg, #3] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (24 << 6)); // lsl templo1, templo1, #24 - cache_addw(0x4300 + dest_reg + (templo1 << 3)); // orr dest_reg, templo1 + cache_addw( LDRB_IMM(dest_reg, data_reg, 0) ); // ldrb dest_reg, [data_reg] + cache_addw( ADD_IMM3(templo1, data_reg, 1) ); // add templo1, data_reg, #1 + cache_addw( LDRH_IMM(templo1, templo1, 0) ); // ldrh templo1, [templo1] + cache_addw( LSL_IMM(templo1, templo1, 8) ); // lsl templo1, templo1, #8 + cache_addw( ORR(dest_reg, templo1) ); // orr dest_reg, templo1 + cache_addw( LDRB_IMM(templo1, data_reg, 3) ); // ldrb templo1, [data_reg, #3] + cache_addw( LSL_IMM(templo1, templo1, 24) ); // lsl templo1, templo1, #24 + cache_addw( ORR(dest_reg, templo1) ); // orr dest_reg, templo1 } } else { - cache_addw(0x6800 + dest_reg + (data_reg << 3)); // ldr dest_reg, [data_reg] + cache_addw( LDR_IMM(dest_reg, data_reg, 0) ); // ldr dest_reg, [data_reg] } } else { if ((Bit32u)data & 1) { - cache_addw(0x7800 + dest_reg + (data_reg << 3)); // ldrb dest_reg, [data_reg] - cache_addw(0x7800 + templo1 + (data_reg << 3) + (1 << 6)); // ldrb templo1, [data_reg, #1] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (8 << 6)); // lsl templo1, templo1, #8 - cache_addw(0x4300 + dest_reg + (templo1 << 3)); // orr dest_reg, templo1 + cache_addw( LDRB_IMM(dest_reg, data_reg, 0) ); // ldrb dest_reg, [data_reg] + cache_addw( LDRB_IMM(templo1, data_reg, 1) ); // ldrb templo1, [data_reg, #1] + cache_addw( LSL_IMM(templo1, templo1, 8) ); // lsl templo1, templo1, #8 + cache_addw( ORR(dest_reg, templo1) ); // orr dest_reg, templo1 } else { - cache_addw(0x8800 + dest_reg + (data_reg << 3)); // ldrh dest_reg, [data_reg] + cache_addw( LDRH_IMM(dest_reg, data_reg, 0) ); // ldrh dest_reg, [data_reg] } } } @@ -165,33 +257,33 @@ static void gen_mov_word_from_reg_helper(HostReg src_reg,void* dest,bool dword, if (dword) { if ((Bit32u)dest & 3) { if ( ((Bit32u)dest & 3) == 2 ) { - cache_addw(0x8000 + src_reg + (data_reg << 3)); // strh src_reg, [data_reg] - cache_addw(0x1c00 + templo1 + (src_reg << 3)); // mov templo1, src_reg - cache_addw(0x0800 + templo1 + (templo1 << 3) + (16 << 6)); // lsr templo1, templo1, #16 - cache_addw(0x8000 + templo1 + (data_reg << 3) + (2 << 5)); // strh templo1, [data_reg, #2] + cache_addw( STRH_IMM(src_reg, data_reg, 0) ); // strh src_reg, [data_reg] + cache_addw( MOV_REG(templo1, src_reg) ); // mov templo1, src_reg + cache_addw( LSR_IMM(templo1, templo1, 16) ); // lsr templo1, templo1, #16 + cache_addw( STRH_IMM(templo1, data_reg, 2) ); // strh templo1, [data_reg, #2] } else { - cache_addw(0x7000 + src_reg + (data_reg << 3)); // strb src_reg, [data_reg] - cache_addw(0x1c00 + templo1 + (src_reg << 3)); // mov templo1, src_reg - cache_addw(0x0800 + templo1 + (templo1 << 3) + (8 << 6)); // lsr templo1, templo1, #8 - cache_addw(0x7000 + templo1 + (data_reg << 3) + (1 << 6)); // strb templo1, [data_reg, #1] - cache_addw(0x1c00 + templo1 + (src_reg << 3)); // mov templo1, src_reg - cache_addw(0x0800 + templo1 + (templo1 << 3) + (16 << 6)); // lsr templo1, templo1, #16 - cache_addw(0x7000 + templo1 + (data_reg << 3) + (2 << 6)); // strb templo1, [data_reg, #2] - cache_addw(0x1c00 + templo1 + (src_reg << 3)); // mov templo1, src_reg - cache_addw(0x0800 + templo1 + (templo1 << 3) + (24 << 6)); // lsr templo1, templo1, #24 - cache_addw(0x7000 + templo1 + (data_reg << 3) + (3 << 6)); // strb templo1, [data_reg, #3] + cache_addw( STRB_IMM(src_reg, data_reg, 0) ); // strb src_reg, [data_reg] + cache_addw( MOV_REG(templo1, src_reg) ); // mov templo1, src_reg + cache_addw( LSR_IMM(templo1, templo1, 8) ); // lsr templo1, templo1, #8 + cache_addw( STRB_IMM(templo1, data_reg, 1) ); // strb templo1, [data_reg, #1] + cache_addw( MOV_REG(templo1, src_reg) ); // mov templo1, src_reg + cache_addw( LSR_IMM(templo1, templo1, 16) ); // lsr templo1, templo1, #16 + cache_addw( STRB_IMM(templo1, data_reg, 2) ); // strb templo1, [data_reg, #2] + cache_addw( MOV_REG(templo1, src_reg) ); // mov templo1, src_reg + cache_addw( LSR_IMM(templo1, templo1, 24) ); // lsr templo1, templo1, #24 + cache_addw( STRB_IMM(templo1, data_reg, 3) ); // strb templo1, [data_reg, #3] } } else { - cache_addw(0x6000 + src_reg + (data_reg << 3)); // str src_reg, [data_reg] + cache_addw( STR_IMM(src_reg, data_reg, 0) ); // str src_reg, [data_reg] } } else { if ((Bit32u)dest & 1) { - cache_addw(0x7000 + src_reg + (data_reg << 3)); // strb src_reg, [data_reg] - cache_addw(0x1c00 + templo1 + (src_reg << 3)); // mov templo1, src_reg - cache_addw(0x0800 + templo1 + (templo1 << 3) + (8 << 6)); // lsr templo1, templo1, #8 - cache_addw(0x7000 + templo1 + (data_reg << 3) + (1 << 6)); // strb templo1, [data_reg, #1] + cache_addw( STRB_IMM(src_reg, data_reg, 0) ); // strb src_reg, [data_reg] + cache_addw( MOV_REG(templo1, src_reg) ); // mov templo1, src_reg + cache_addw( LSR_IMM(templo1, templo1, 8) ); // lsr templo1, templo1, #8 + cache_addw( STRB_IMM(templo1, data_reg, 1) ); // strb templo1, [data_reg, #1] } else { - cache_addw(0x8000 + src_reg + (data_reg << 3)); // strh src_reg, [data_reg] + cache_addw( STRH_IMM(src_reg, data_reg, 0) ); // strh src_reg, [data_reg] } } } @@ -208,7 +300,7 @@ static void gen_mov_word_from_reg(HostReg src_reg,void* dest,bool dword) { // registers might not be directly byte-accessible on some architectures static void gen_mov_byte_to_reg_low(HostReg dest_reg,void* data) { gen_mov_dword_to_reg_imm(templo1, (Bit32u)data); - cache_addw(0x7800 + dest_reg + (templo1 << 3)); // ldrb dest_reg, [templo1] + cache_addw( LDRB_IMM(dest_reg, templo1, 0) ); // ldrb dest_reg, [templo1] } // move an 8bit value from memory into dest_reg @@ -224,7 +316,7 @@ static void INLINE gen_mov_byte_to_reg_low_canuseword(HostReg dest_reg,void* dat // this function does not use FC_OP1/FC_OP2 as dest_reg as these // registers might not be directly byte-accessible on some architectures static void gen_mov_byte_to_reg_low_imm(HostReg dest_reg,Bit8u imm) { - cache_addw(0x2000 + (dest_reg << 8) + imm); // mov dest_reg, #(imm) + cache_addw( MOV_IMM(dest_reg, imm) ); // mov dest_reg, #(imm) } // move an 8bit constant value into dest_reg @@ -238,7 +330,7 @@ static void INLINE gen_mov_byte_to_reg_low_imm_canuseword(HostReg dest_reg,Bit8u // move the lowest 8bit of a register into memory static void gen_mov_byte_from_reg_low(HostReg src_reg,void* dest) { gen_mov_dword_to_reg_imm(templo1, (Bit32u)dest); - cache_addw(0x7000 + src_reg + (templo1 << 3)); // strb src_reg, [templo1] + cache_addw( STRB_IMM(src_reg, templo1, 0) ); // strb src_reg, [templo1] } @@ -246,55 +338,55 @@ static void gen_mov_byte_from_reg_low(HostReg src_reg,void* dest) { // convert an 8bit word to a 32bit dword // the register is zero-extended (sign==false) or sign-extended (sign==true) static void gen_extend_byte(bool sign,HostReg reg) { - cache_addw(0x0000 + reg + (reg << 3) + (24 << 6)); // lsl reg, reg, #24 + cache_addw( LSL_IMM(reg, reg, 24) ); // lsl reg, reg, #24 if (sign) { - cache_addw(0x1000 + reg + (reg << 3) + (24 << 6)); // asr reg, reg, #24 + cache_addw( ASR_IMM(reg, reg, 24) ); // asr reg, reg, #24 } else { - cache_addw(0x0800 + reg + (reg << 3) + (24 << 6)); // lsr reg, reg, #24 + cache_addw( LSR_IMM(reg, reg, 24) ); // lsr reg, reg, #24 } } // convert a 16bit word to a 32bit dword // the register is zero-extended (sign==false) or sign-extended (sign==true) static void gen_extend_word(bool sign,HostReg reg) { - cache_addw(0x0000 + reg + (reg << 3) + (16 << 6)); // lsl reg, reg, #16 + cache_addw( LSL_IMM(reg, reg, 16) ); // lsl reg, reg, #16 if (sign) { - cache_addw(0x1000 + reg + (reg << 3) + (16 << 6)); // asr reg, reg, #16 + cache_addw( ASR_IMM(reg, reg, 16) ); // asr reg, reg, #16 } else { - cache_addw(0x0800 + reg + (reg << 3) + (16 << 6)); // lsr reg, reg, #16 + cache_addw( LSR_IMM(reg, reg, 16) ); // lsr reg, reg, #16 } } // add a 32bit value from memory to a full register static void gen_add(HostReg reg,void* op) { - cache_addw(0x4680 + (temphi1 - HOST_r8) + (reg << 3)); // mov temphi1, reg + cache_addw( MOV_HI_LO(temphi1, reg) ); // mov temphi1, reg gen_mov_word_to_reg(reg, op, 1); - cache_addw(0x4440 + (reg) + ((temphi1 - HOST_r8) << 3)); // add reg, temphi1 + cache_addw( ADD_LO_HI(reg, temphi1) ); // add reg, temphi1 } // add a 32bit constant value to a full register static void gen_add_imm(HostReg reg,Bit32u imm) { if(!imm) return; gen_mov_dword_to_reg_imm(templo1, imm); - cache_addw(0x1800 + reg + (reg << 3) + (templo1 << 6)); // add reg, reg, templo1 + cache_addw( ADD_REG(reg, reg, templo1) ); // add reg, reg, templo1 } // and a 32bit constant value with a full register static void gen_and_imm(HostReg reg,Bit32u imm) { if(imm == 0xffffffff) return; gen_mov_dword_to_reg_imm(templo1, imm); - cache_addw(0x4000 + reg + (templo1<< 3)); // and reg, templo1 + cache_addw( AND(reg, templo1) ); // and reg, templo1 } // move a 32bit constant value into memory static void gen_mov_direct_dword(void* dest,Bit32u imm) { - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_dword_to_reg_imm(templosav, imm); gen_mov_word_from_reg(templosav, dest, 1); - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 } // move an address into memory @@ -305,16 +397,16 @@ static void INLINE gen_mov_direct_ptr(void* dest,DRC_PTR_SIZE_IM imm) { // add an 8bit constant value to a dword memory value static void gen_add_direct_byte(void* dest,Bit8s imm) { if(!imm) return; - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_dword_to_reg_imm(templo2, (Bit32u)dest); gen_mov_word_to_reg_helper(templosav, dest, 1, templo2); if (imm >= 0) { - cache_addw(0x3000 + (templosav << 8) + ((Bit32s)imm)); // add templosav, #(imm) + cache_addw( ADD_IMM8(templosav, (Bit32s)imm) ); // add templosav, #(imm) } else { - cache_addw(0x3800 + (templosav << 8) + (-((Bit32s)imm))); // sub templosav, #(-imm) + cache_addw( SUB_IMM8(templosav, -((Bit32s)imm)) ); // sub templosav, #(-imm) } gen_mov_word_from_reg_helper(templosav, dest, 1, templo2); - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 } // add a 32bit (dword==true) or 16bit (dword==false) constant value to a memory value @@ -324,7 +416,7 @@ static void gen_add_direct_word(void* dest,Bit32u imm,bool dword) { gen_add_direct_byte(dest,(Bit8s)imm); return; } - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_dword_to_reg_imm(templo2, (Bit32u)dest); gen_mov_word_to_reg_helper(templosav, dest, dword, templo2); if (dword) { @@ -332,24 +424,24 @@ static void gen_add_direct_word(void* dest,Bit32u imm,bool dword) { } else { gen_mov_word_to_reg_imm(templo1, (Bit16u)imm); } - cache_addw(0x1800 + templosav + (templosav << 3) + (templo1 << 6)); // add templosav, templosav, templo1 + cache_addw( ADD_REG(templosav, templosav, templo1) ); // add templosav, templosav, templo1 gen_mov_word_from_reg_helper(templosav, dest, dword, templo2); - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 } // subtract an 8bit constant value from a dword memory value static void gen_sub_direct_byte(void* dest,Bit8s imm) { if(!imm) return; - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_dword_to_reg_imm(templo2, (Bit32u)dest); gen_mov_word_to_reg_helper(templosav, dest, 1, templo2); if (imm >= 0) { - cache_addw(0x3800 + (templosav << 8) + ((Bit32s)imm)); // sub templosav, #(imm) + cache_addw( SUB_IMM8(templosav, (Bit32s)imm) ); // sub templosav, #(imm) } else { - cache_addw(0x3000 + (templosav << 8) + (-((Bit32s)imm))); // add templosav, #(-imm) + cache_addw( ADD_IMM8(templosav, -((Bit32s)imm)) ); // add templosav, #(-imm) } gen_mov_word_from_reg_helper(templosav, dest, 1, templo2); - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 } // subtract a 32bit (dword==true) or 16bit (dword==false) constant value from a memory value @@ -359,7 +451,7 @@ static void gen_sub_direct_word(void* dest,Bit32u imm,bool dword) { gen_sub_direct_byte(dest,(Bit8s)imm); return; } - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_dword_to_reg_imm(templo2, (Bit32u)dest); gen_mov_word_to_reg_helper(templosav, dest, dword, templo2); if (dword) { @@ -367,9 +459,9 @@ static void gen_sub_direct_word(void* dest,Bit32u imm,bool dword) { } else { gen_mov_word_to_reg_imm(templo1, (Bit16u)imm); } - cache_addw(0x1a00 + templosav + (templosav << 3) + (templo1 << 6)); // sub templosav, templosav, templo1 + cache_addw( SUB_REG(templosav, templosav, templo1) ); // sub templosav, templosav, templo1 gen_mov_word_from_reg_helper(templosav, dest, dword, templo2); - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 } // effective address calculation, destination is dest_reg @@ -377,10 +469,10 @@ static void gen_sub_direct_word(void* dest,Bit32u imm,bool dword) { // added to dest_reg, then the immediate value is added static INLINE void gen_lea(HostReg dest_reg,HostReg scale_reg,Bitu scale,Bits imm) { if (scale) { - cache_addw(0x0000 + templo1 + (scale_reg << 3) + (scale << 6)); // lsl templo1, scale_reg, #(scale) - cache_addw(0x1800 + dest_reg + (dest_reg << 3) + (templo1 << 6)); // add dest_reg, dest_reg, templo1 + cache_addw( LSL_IMM(templo1, scale_reg, scale) ); // lsl templo1, scale_reg, #(scale) + cache_addw( ADD_REG(dest_reg, dest_reg, templo1) ); // add dest_reg, dest_reg, templo1 } else { - cache_addw(0x1800 + dest_reg + (dest_reg << 3) + (scale_reg << 6)); // add dest_reg, dest_reg, scale_reg + cache_addw( ADD_REG(dest_reg, dest_reg, scale_reg) ); // add dest_reg, dest_reg, scale_reg } gen_add_imm(dest_reg, imm); } @@ -390,7 +482,7 @@ static INLINE void gen_lea(HostReg dest_reg,HostReg scale_reg,Bitu scale,Bits im // then the immediate value is added static INLINE void gen_lea(HostReg dest_reg,Bitu scale,Bits imm) { if (scale) { - cache_addw(0x0000 + dest_reg + (dest_reg << 3) + (scale << 6)); // lsl dest_reg, dest_reg, #(scale) + cache_addw( LSL_IMM(dest_reg, dest_reg, scale) ); // lsl dest_reg, dest_reg, #(scale) } gen_add_imm(dest_reg, imm); } @@ -398,16 +490,16 @@ static INLINE void gen_lea(HostReg dest_reg,Bitu scale,Bits imm) { // generate a call to a parameterless function static void INLINE gen_call_function_raw(void * func) { if (((Bit32u)cache.pos & 0x03) == 0) { - cache_addw(0x4800 + (templo1 << 8) + (4 >> 2)); // ldr templo1, [pc, #4] - cache_addw(0xa000 + (templo2 << 8) + (8 >> 2)); // adr templo2, after_call (add templo2, pc, #8) - cache_addw(0x4680 + (HOST_lr - HOST_r8) + (templo2 << 3)); // mov lr, templo2 - cache_addw(0x4700 + (templo1 << 3)); // bx templo1 --- switch to arm state + cache_addw( LDR_PC_IMM(templo1, 4) ); // ldr templo1, [pc, #4] + cache_addw( ADD_LO_PC_IMM(templo2, 8) ); // adr templo2, after_call (add templo2, pc, #8) + cache_addw( MOV_HI_LO(HOST_lr, templo2) ); // mov lr, templo2 + cache_addw( BX(templo1) ); // bx templo1 --- switch to arm state } else { - cache_addw(0x4800 + (templo1 << 8) + (8 >> 2)); // ldr templo1, [pc, #8] - cache_addw(0xa000 + (templo2 << 8) + (8 >> 2)); // adr templo2, after_call (add templo2, pc, #8) - cache_addw(0x4680 + (HOST_lr - HOST_r8) + (templo2 << 3)); // mov lr, templo2 - cache_addw(0x4700 + (templo1 << 3)); // bx templo1 --- switch to arm state - cache_addw(0x46c0); // nop + cache_addw( LDR_PC_IMM(templo1, 8) ); // ldr templo1, [pc, #8] + cache_addw( ADD_LO_PC_IMM(templo2, 8) ); // adr templo2, after_call (add templo2, pc, #8) + cache_addw( MOV_HI_LO(HOST_lr, templo2) ); // mov lr, templo2 + cache_addw( BX(templo1) ); // bx templo1 --- switch to arm state + cache_addw( NOP ); // nop } cache_addd((Bit32u)func); // .int func // after_call: @@ -417,7 +509,7 @@ static void INLINE gen_call_function_raw(void * func) { cache_addd(0xe12fff10 + (templo1)); // bx templo1 // thumb state from now on - cache_addw(0x1c00 + FC_RETOP + (HOST_a1 << 3)); // mov FC_RETOP, a1 + cache_addw( MOV_REG(FC_RETOP, HOST_a1) ); // mov FC_RETOP, a1 } // generate a call to a function with paramcount parameters @@ -460,50 +552,50 @@ static void INLINE gen_load_param_mem(Bitu mem,Bitu param) { // jump to an address pointed at by ptr, offset is in imm static void gen_jmp_ptr(void * ptr,Bits imm=0) { - cache_addw(0x4680 + (temphi1 - HOST_r8) + (templosav << 3)); // mov temphi1, templosav + cache_addw( MOV_HI_LO(temphi1, templosav) ); // mov temphi1, templosav gen_mov_word_to_reg(templosav, ptr, 1); if (imm) { gen_mov_dword_to_reg_imm(templo2, imm); - cache_addw(0x1800 + templosav + (templosav << 3) + (templo2 << 6)); // add templosav, templosav, templo2 + cache_addw( ADD_REG(templosav, templosav, templo2) ); // add templosav, templosav, templo2 } #if (1) // (*ptr) should be word aligned if ((imm & 0x03) == 0) { - cache_addw(0x6800 + templo2 + (templosav << 3)); // ldr templo2, [templosav] + cache_addw( LDR_IMM(templo2, templosav, 0) ); // ldr templo2, [templosav] } else #endif { - cache_addw(0x7800 + templo2 + (templosav << 3)); // ldrb templo2, [templosav] - cache_addw(0x7800 + templo1 + (templosav << 3) + (1 << 6)); // ldrb templo1, [templosav, #1] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (8 << 6)); // lsl templo1, templo1, #8 - cache_addw(0x4300 + templo2 + (templo1 << 3)); // orr templo2, templo1 - cache_addw(0x7800 + templo1 + (templosav << 3) + (2 << 6)); // ldrb templo1, [templosav, #2] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (16 << 6)); // lsl templo1, templo1, #16 - cache_addw(0x4300 + templo2 + (templo1 << 3)); // orr templo2, templo1 - cache_addw(0x7800 + templo1 + (templosav << 3) + (3 << 6)); // ldrb templo1, [templosav, #3] - cache_addw(0x0000 + templo1 + (templo1 << 3) + (24 << 6)); // lsl templo1, templo1, #24 - cache_addw(0x4300 + templo2 + (templo1 << 3)); // orr templo2, templo1 + cache_addw( LDRB_IMM(templo2, templosav, 0) ); // ldrb templo2, [templosav] + cache_addw( LDRB_IMM(templo1, templosav, 1) ); // ldrb templo1, [templosav, #1] + cache_addw( LSL_IMM(templo1, templo1, 8) ); // lsl templo1, templo1, #8 + cache_addw( ORR(templo2, templo1) ); // orr templo2, templo1 + cache_addw( LDRB_IMM(templo1, templosav, 2) ); // ldrb templo1, [templosav, #2] + cache_addw( LSL_IMM(templo1, templo1, 16) ); // lsl templo1, templo1, #16 + cache_addw( ORR(templo2, templo1) ); // orr templo2, templo1 + cache_addw( LDRB_IMM(templo1, templosav, 3) ); // ldrb templo1, [templosav, #3] + cache_addw( LSL_IMM(templo1, templo1, 24) ); // lsl templo1, templo1, #24 + cache_addw( ORR(templo2, templo1) ); // orr templo2, templo1 } // increase jmp address to keep thumb state - cache_addw(0x1c00 + templo2 + (templo2 << 3) + (1 << 6)); // add templo2, templo2, #1 + cache_addw( ADD_IMM3(templo2, templo2, 1) ); // add templo2, templo2, #1 - cache_addw(0x4640 + templosav + ((temphi1 - HOST_r8) << 3)); // mov templosav, temphi1 + cache_addw( MOV_LO_HI(templosav, temphi1) ); // mov templosav, temphi1 - cache_addw(0x4700 + (templo2 << 3)); // bx templo2 + cache_addw( BX(templo2) ); // bx templo2 } // short conditional jump (+-127 bytes) if register is zero // the destination is set by gen_fill_branch() later static Bit32u gen_create_branch_on_zero(HostReg reg,bool dword) { if (dword) { - cache_addw(0x2800 + (reg << 8)); // cmp reg, #0 + cache_addw( CMP_IMM(reg, 0) ); // cmp reg, #0 } else { - cache_addw(0x0000 + templo1 + (reg << 3) + (16 << 6)); // lsl templo1, reg, #16 + cache_addw( LSL_IMM(templo1, reg, 16) ); // lsl templo1, reg, #16 } - cache_addw(0xd000); // beq j + cache_addw( BEQ_FWD(0) ); // beq j return ((Bit32u)cache.pos-2); } @@ -511,11 +603,11 @@ static Bit32u gen_create_branch_on_zero(HostReg reg,bool dword) { // the destination is set by gen_fill_branch() later static Bit32u gen_create_branch_on_nonzero(HostReg reg,bool dword) { if (dword) { - cache_addw(0x2800 + (reg << 8)); // cmp reg, #0 + cache_addw( CMP_IMM(reg, 0) ); // cmp reg, #0 } else { - cache_addw(0x0000 + templo1 + (reg << 3) + (16 << 6)); // lsl templo1, reg, #16 + cache_addw( LSL_IMM(templo1, reg, 16) ); // lsl templo1, reg, #16 } - cache_addw(0xd100); // bne j + cache_addw( BNE_FWD(0) ); // bne j return ((Bit32u)cache.pos-2); } @@ -534,19 +626,19 @@ static void INLINE gen_fill_branch(DRC_PTR_SIZE_IM data) { // for isdword==false the lowest 8bit of the register are tested static Bit32u gen_create_branch_long_nonzero(HostReg reg,bool isdword) { if (isdword) { - cache_addw(0x2800 + (reg << 8)); // cmp reg, #0 + cache_addw( CMP_IMM(reg, 0) ); // cmp reg, #0 } else { - cache_addw(0x0000 + templo2 + (reg << 3) + (24 << 6)); // lsl templo2, reg, #24 + cache_addw( LSL_IMM(templo2, reg, 24) ); // lsl templo2, reg, #24 } if (((Bit32u)cache.pos & 0x03) == 0) { - cache_addw(0xd000 + (8 >> 1)); // beq nobranch (pc+8) - cache_addw(0x4800 + (templo1 << 8) + (4 >> 2)); // ldr templo1, [pc, #4] - cache_addw(0x4700 + (templo1 << 3)); // bx templo1 - cache_addw(0x46c0); // nop + cache_addw( BEQ_FWD(8) ); // beq nobranch (pc+8) + cache_addw( LDR_PC_IMM(templo1, 4) ); // ldr templo1, [pc, #4] + cache_addw( BX(templo1) ); // bx templo1 + cache_addw( NOP ); // nop } else { - cache_addw(0xd000 + (6 >> 1)); // beq nobranch (pc+6) - cache_addw(0x4800 + (templo1 << 8)); // ldr templo1, [pc, #0] - cache_addw(0x4700 + (templo1 << 3)); // bx templo1 + cache_addw( BEQ_FWD(6) ); // beq nobranch (pc+6) + cache_addw( LDR_PC_IMM(templo1, 0) ); // ldr templo1, [pc, #0] + cache_addw( BX(templo1) ); // bx templo1 } cache_addd(0); // fill j // nobranch: @@ -555,16 +647,16 @@ static Bit32u gen_create_branch_long_nonzero(HostReg reg,bool isdword) { // compare 32bit-register against zero and jump if value less/equal than zero static Bit32u gen_create_branch_long_leqzero(HostReg reg) { - cache_addw(0x2800 + (reg << 8)); // cmp reg, #0 + cache_addw( CMP_IMM(reg, 0) ); // cmp reg, #0 if (((Bit32u)cache.pos & 0x03) == 0) { - cache_addw(0xdc00 + (8 >> 1)); // bgt nobranch (pc+8) - cache_addw(0x4800 + (templo1 << 8) + (4 >> 2)); // ldr templo1, [pc, #4] - cache_addw(0x4700 + (templo1 << 3)); // bx templo1 - cache_addw(0x46c0); // nop + cache_addw( BGT_FWD(8) ); // bgt nobranch (pc+8) + cache_addw( LDR_PC_IMM(templo1, 4) ); // ldr templo1, [pc, #4] + cache_addw( BX(templo1) ); // bx templo1 + cache_addw( NOP ); // nop } else { - cache_addw(0xdc00 + (6 >> 1)); // bgt nobranch (pc+6) - cache_addw(0x4800 + (templo1 << 8)); // ldr templo1, [pc, #0] - cache_addw(0x4700 + (templo1 << 3)); // bx templo1 + cache_addw( BGT_FWD(6) ); // bgt nobranch (pc+6) + cache_addw( LDR_PC_IMM(templo1, 0) ); // ldr templo1, [pc, #0] + cache_addw( BX(templo1) ); // bx templo1 } cache_addd(0); // fill j // nobranch: @@ -584,39 +676,39 @@ static void gen_run_code(void) { // thumb state from now on cache_addw(0xb500); // push {lr} - cache_addw(0x4640 + HOST_r3 + ((FC_SEGS_ADDR - HOST_r8) << 3)); // mov r3, FC_SEGS_ADDR - cache_addw(0x4640 + HOST_r2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov r2, FC_REGS_ADDR + cache_addw( MOV_LO_HI(HOST_r3, FC_SEGS_ADDR) ); // mov r3, FC_SEGS_ADDR + cache_addw( MOV_LO_HI(HOST_r2, FC_REGS_ADDR) ); // mov r2, FC_REGS_ADDR cache_addw(0xb4fc); // push {r2,r3,v1-v4} // adr: 16 - cache_addw(0x4800 + (HOST_r3 << 8) + ((64 - (16 + 4)) >> 2)); // ldr r3, [pc, #(&Segs)] + cache_addw( LDR_PC_IMM(HOST_r3, 64 - (16 + 4)) ); // ldr r3, [pc, #(&Segs)] // adr: 18 - cache_addw(0x4800 + (HOST_r2 << 8) + ((68 - (18 + 2)) >> 2)); // ldr r2, [pc, #(&cpu_regs)] - cache_addw(0x4680 + (FC_SEGS_ADDR - HOST_r8) + (HOST_r3 << 3)); // mov FC_SEGS_ADDR, r3 - cache_addw(0x4680 + (FC_REGS_ADDR - HOST_r8) + (HOST_r2 << 3)); // mov FC_REGS_ADDR, r2 + cache_addw( LDR_PC_IMM(HOST_r2, 68 - (18 + 2)) ); // ldr r2, [pc, #(&cpu_regs)] + cache_addw( MOV_HI_LO(FC_SEGS_ADDR, HOST_r3) ); // mov FC_SEGS_ADDR, r3 + cache_addw( MOV_HI_LO(FC_REGS_ADDR, HOST_r2) ); // mov FC_REGS_ADDR, r2 // align 4 - - cache_addw(0xa302); // add r3, pc, #8 - cache_addw(0x3001); // add r0, #1 - cache_addw(0x3301); // add r3, #1 + cache_addw( ADD_LO_PC_IMM(HOST_r3, 8) ); // add r3, pc, #8 + cache_addw( ADD_IMM8(HOST_r0, 1) ); // add r0, #1 + cache_addw( ADD_IMM8(HOST_r3, 1) ); // add r3, #1 cache_addw(0xb408); // push {r3} - cache_addw(0x4700); // bx r0 - cache_addw(0x46c0); // nop + cache_addw( BX(HOST_r0) ); // bx r0 + cache_addw( NOP ); // nop // align 4 cache_addw(0xbcfc); // pop {r2,r3,v1-v4} - cache_addw(0x4680 + (FC_SEGS_ADDR - HOST_r8) + (HOST_r3 << 3)); // mov FC_SEGS_ADDR, r3 - cache_addw(0x4680 + (FC_REGS_ADDR - HOST_r8) + (HOST_r2 << 3)); // mov FC_REGS_ADDR, r2 + cache_addw( MOV_HI_LO(FC_SEGS_ADDR, HOST_r3) ); // mov FC_SEGS_ADDR, r3 + cache_addw( MOV_HI_LO(FC_REGS_ADDR, HOST_r2) ); // mov FC_REGS_ADDR, r2 cache_addw(0xbc08); // pop {r3} - cache_addw(0x4718); // bx r3 + cache_addw( BX(HOST_r3) ); // bx r3 + // fill up to 64 bytes - cache_addw(0x46c0); // nop - cache_addd(0x46c046c0); // nop, nop - cache_addd(0x46c046c0); // nop, nop - cache_addd(0x46c046c0); // nop, nop - cache_addd(0x46c046c0); // nop, nop + cache_addw( NOP ); // nop + cache_addd( NOP | (NOP << 16) ); // nop, nop + cache_addd( NOP | (NOP << 16) ); // nop, nop + cache_addd( NOP | (NOP << 16) ); // nop, nop + cache_addd( NOP | (NOP << 16) ); // nop, nop // adr: 64 cache_addd((Bit32u)&Segs); // address of "Segs" @@ -626,9 +718,9 @@ static void gen_run_code(void) { // return from a function static void gen_return_function(void) { - cache_addw(0x1c00 + HOST_a1 + (FC_RETOP << 3)); // mov a1, FC_RETOP + cache_addw( MOV_REG(HOST_a1, FC_RETOP) ); // mov a1, FC_RETOP cache_addw(0xbc08); // pop {r3} - cache_addw(0x4718); // bx r3 + cache_addw( BX(HOST_r3) ); // bx r3 } #ifdef DRC_FLAGS_INVALIDATION @@ -644,35 +736,35 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { case t_ADDb: case t_ADDw: case t_ADDd: - *(Bit16u*)pos=0x1800 + FC_RETOP + (HOST_a1 << 3) + (HOST_a2 << 6); // add FC_RETOP, a1, a2 - *(Bit16u*)(pos+2)=0xe000 + (16 >> 1); // b after_call (pc+16) + *(Bit16u*)pos=ADD_REG(FC_RETOP, HOST_a1, HOST_a2); // add FC_RETOP, a1, a2 + *(Bit16u*)(pos+2)=B_FWD(16); // b after_call (pc+16) break; case t_ORb: case t_ORw: case t_ORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4300 + FC_RETOP + (HOST_a2 << 3); // orr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ORR(FC_RETOP, HOST_a2); // orr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(14); // b after_call (pc+14) break; case t_ANDb: case t_ANDw: case t_ANDd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4000 + FC_RETOP + (HOST_a2 << 3); // and FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=AND(FC_RETOP, HOST_a2); // and FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(14); // b after_call (pc+14) break; case t_SUBb: case t_SUBw: case t_SUBd: - *(Bit16u*)pos=0x1a00 + FC_RETOP + (HOST_a1 << 3) + (HOST_a2 << 6); // sub FC_RETOP, a1, a2 - *(Bit16u*)(pos+2)=0xe000 + (16 >> 1); // b after_call (pc+16) + *(Bit16u*)pos=SUB_REG(FC_RETOP, HOST_a1, HOST_a2); // sub FC_RETOP, a1, a2 + *(Bit16u*)(pos+2)=B_FWD(16); // b after_call (pc+16) break; case t_XORb: case t_XORw: case t_XORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4040 + FC_RETOP + (HOST_a2 << 3); // eor FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=EOR(FC_RETOP, HOST_a2); // eor FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(14); // b after_call (pc+14) break; case t_CMPb: case t_CMPw: @@ -680,116 +772,116 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { case t_TESTb: case t_TESTw: case t_TESTd: - *(Bit16u*)pos=0xe000 + (18 >> 1); // b after_call (pc+18) + *(Bit16u*)pos=B_FWD(18); // b after_call (pc+18) break; case t_INCb: case t_INCw: case t_INCd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3) + (1 << 6); // add FC_RETOP, a1, #1 - *(Bit16u*)(pos+2)=0xe000 + (16 >> 1); // b after_call (pc+16) + *(Bit16u*)pos=ADD_IMM3(FC_RETOP, HOST_a1, 1); // add FC_RETOP, a1, #1 + *(Bit16u*)(pos+2)=B_FWD(16); // b after_call (pc+16) break; case t_DECb: case t_DECw: case t_DECd: - *(Bit16u*)pos=0x1e00 + FC_RETOP + (HOST_a1 << 3) + (1 << 6); // sub FC_RETOP, a1, #1 - *(Bit16u*)(pos+2)=0xe000 + (16 >> 1); // b after_call (pc+16) + *(Bit16u*)pos=SUB_IMM3(FC_RETOP, HOST_a1, 1); // sub FC_RETOP, a1, #1 + *(Bit16u*)(pos+2)=B_FWD(16); // b after_call (pc+16) break; case t_SHLb: case t_SHLw: case t_SHLd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4080 + FC_RETOP + (HOST_a2 << 3); // lsl FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=LSL_REG(FC_RETOP, HOST_a2); // lsl FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(14); // b after_call (pc+14) break; case t_SHRb: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (24 << 6); // lsl FC_RETOP, a1, #24 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (FC_RETOP << 3) + (24 << 6); // lsr FC_RETOP, FC_RETOP, #24 - *(Bit16u*)(pos+4)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 24); // lsl FC_RETOP, a1, #24 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, FC_RETOP, 24); // lsr FC_RETOP, FC_RETOP, #24 + *(Bit16u*)(pos+4)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(12); // b after_call (pc+12) break; case t_SHRw: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsl FC_RETOP, a1, #16 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (FC_RETOP << 3) + (16 << 6); // lsr FC_RETOP, FC_RETOP, #16 - *(Bit16u*)(pos+4)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 16); // lsl FC_RETOP, a1, #16 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, FC_RETOP, 16); // lsr FC_RETOP, FC_RETOP, #16 + *(Bit16u*)(pos+4)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(12); // b after_call (pc+12) break; case t_SHRd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(14); // b after_call (pc+14) break; case t_SARb: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (24 << 6); // lsl FC_RETOP, a1, #24 - *(Bit16u*)(pos+2)=0x1000 + FC_RETOP + (FC_RETOP << 3) + (24 << 6); // asr FC_RETOP, FC_RETOP, #24 - *(Bit16u*)(pos+4)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 24); // lsl FC_RETOP, a1, #24 + *(Bit16u*)(pos+2)=ASR_IMM(FC_RETOP, FC_RETOP, 24); // asr FC_RETOP, FC_RETOP, #24 + *(Bit16u*)(pos+4)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(12); // b after_call (pc+12) break; case t_SARw: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsl FC_RETOP, a1, #16 - *(Bit16u*)(pos+2)=0x1000 + FC_RETOP + (FC_RETOP << 3) + (16 << 6); // asr FC_RETOP, FC_RETOP, #16 - *(Bit16u*)(pos+4)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 16); // lsl FC_RETOP, a1, #16 + *(Bit16u*)(pos+2)=ASR_IMM(FC_RETOP, FC_RETOP, 16); // asr FC_RETOP, FC_RETOP, #16 + *(Bit16u*)(pos+4)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(12); // b after_call (pc+12) break; case t_SARd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(14); // b after_call (pc+14) break; case t_RORb: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (24 << 6); // lsl a1, a1, #24 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (8 << 6); // lsr FC_RETOP, a1, #8 - *(Bit16u*)(pos+4)=0x4300 + HOST_a1 + (FC_RETOP << 3); // orr a1, FC_RETOP - *(Bit16u*)(pos+6)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+8)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+10)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 - *(Bit16u*)(pos+12)=0xe000 + (6 >> 1); // b after_call (pc+6) + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 24); // lsl a1, a1, #24 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, HOST_a1, 8); // lsr FC_RETOP, a1, #8 + *(Bit16u*)(pos+4)=ORR(HOST_a1, FC_RETOP); // orr a1, FC_RETOP + *(Bit16u*)(pos+6)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+8)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+10)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 + *(Bit16u*)(pos+12)=B_FWD(6); // b after_call (pc+6) break; case t_RORw: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (16 << 6); // lsl a1, a1, #16 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+4)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+6)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 - *(Bit16u*)(pos+8)=0xe000 + (10 >> 1); // b after_call (pc+10) + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 16); // lsl a1, a1, #16 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+4)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+6)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 + *(Bit16u*)(pos+8)=B_FWD(10); // b after_call (pc+10) break; case t_RORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(14); // b after_call (pc+14) break; case t_ROLb: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (24 << 6); // lsl a1, a1, #24 - *(Bit16u*)(pos+2)=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+4)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (8 << 6); // lsr FC_RETOP, a1, #8 - *(Bit16u*)(pos+6)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+8)=0x4300 + HOST_a1 + (FC_RETOP << 3); // orr a1, FC_RETOP - *(Bit16u*)(pos+10)=0x46c0; // nop - *(Bit16u*)(pos+12)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+14)=0x46c0; // nop - *(Bit16u*)(pos+16)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+18)=0x46c0; // nop - *(Bit16u*)(pos+20)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 24); // lsl a1, a1, #24 + *(Bit16u*)(pos+2)=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+4)=LSR_IMM(FC_RETOP, HOST_a1, 8); // lsr FC_RETOP, a1, #8 + *(Bit16u*)(pos+6)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+8)=ORR(HOST_a1, FC_RETOP); // orr a1, FC_RETOP + *(Bit16u*)(pos+10)=NOP; // nop + *(Bit16u*)(pos+12)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+14)=NOP; // nop + *(Bit16u*)(pos+16)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+18)=NOP; // nop + *(Bit16u*)(pos+20)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 break; case t_ROLw: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (16 << 6); // lsl a1, a1, #16 - *(Bit16u*)(pos+2)=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+4)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+6)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+8)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+10)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 - *(Bit16u*)(pos+12)=0xe000 + (6 >> 1); // b after_call (pc+6) + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 16); // lsl a1, a1, #16 + *(Bit16u*)(pos+2)=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+4)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+6)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+8)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+10)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 + *(Bit16u*)(pos+12)=B_FWD(6); // b after_call (pc+6) break; case t_ROLd: - *(Bit16u*)pos=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+2)=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+4)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+6)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 - *(Bit16u*)(pos+8)=0xe000 + (10 >> 1); // b after_call (pc+10) + *(Bit16u*)pos=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+2)=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+4)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+6)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 + *(Bit16u*)(pos+8)=B_FWD(10); // b after_call (pc+10) break; case t_NEGb: case t_NEGw: case t_NEGd: - *(Bit16u*)pos=0x4240 + FC_RETOP + (HOST_a1 << 3); // neg FC_RETOP, a1 - *(Bit16u*)(pos+2)=0xe000 + (16 >> 1); // b after_call (pc+16) + *(Bit16u*)pos=NEG(FC_RETOP, HOST_a1); // neg FC_RETOP, a1 + *(Bit16u*)(pos+2)=B_FWD(16); // b after_call (pc+16) break; default: *(Bit32u*)(pos+8)=(Bit32u)fct_ptr; // simple_func @@ -803,35 +895,35 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { case t_ADDb: case t_ADDw: case t_ADDd: - *(Bit16u*)pos=0x1800 + FC_RETOP + (HOST_a1 << 3) + (HOST_a2 << 6); // add FC_RETOP, a1, a2 - *(Bit16u*)(pos+2)=0xe000 + (18 >> 1); // b after_call (pc+18) + *(Bit16u*)pos=ADD_REG(FC_RETOP, HOST_a1, HOST_a2); // add FC_RETOP, a1, a2 + *(Bit16u*)(pos+2)=B_FWD(18); // b after_call (pc+18) break; case t_ORb: case t_ORw: case t_ORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4300 + FC_RETOP + (HOST_a2 << 3); // orr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (16 >> 1); // b after_call (pc+16) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ORR(FC_RETOP, HOST_a2); // orr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(16); // b after_call (pc+16) break; case t_ANDb: case t_ANDw: case t_ANDd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4000 + FC_RETOP + (HOST_a2 << 3); // and FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (16 >> 1); // b after_call (pc+16) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=AND(FC_RETOP, HOST_a2); // and FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(16); // b after_call (pc+16) break; case t_SUBb: case t_SUBw: case t_SUBd: - *(Bit16u*)pos=0x1a00 + FC_RETOP + (HOST_a1 << 3) + (HOST_a2 << 6); // sub FC_RETOP, a1, a2 - *(Bit16u*)(pos+2)=0xe000 + (18 >> 1); // b after_call (pc+18) + *(Bit16u*)pos=SUB_REG(FC_RETOP, HOST_a1, HOST_a2); // sub FC_RETOP, a1, a2 + *(Bit16u*)(pos+2)=B_FWD(18); // b after_call (pc+18) break; case t_XORb: case t_XORw: case t_XORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4040 + FC_RETOP + (HOST_a2 << 3); // eor FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (16 >> 1); // b after_call (pc+16) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=EOR(FC_RETOP, HOST_a2); // eor FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(16); // b after_call (pc+16) break; case t_CMPb: case t_CMPw: @@ -839,114 +931,114 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { case t_TESTb: case t_TESTw: case t_TESTd: - *(Bit16u*)pos=0xe000 + (20 >> 1); // b after_call (pc+20) + *(Bit16u*)pos=B_FWD(20); // b after_call (pc+20) break; case t_INCb: case t_INCw: case t_INCd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3) + (1 << 6); // add FC_RETOP, a1, #1 - *(Bit16u*)(pos+2)=0xe000 + (18 >> 1); // b after_call (pc+18) + *(Bit16u*)pos=ADD_IMM3(FC_RETOP, HOST_a1, 1); // add FC_RETOP, a1, #1 + *(Bit16u*)(pos+2)=B_FWD(18); // b after_call (pc+18) break; case t_DECb: case t_DECw: case t_DECd: - *(Bit16u*)pos=0x1e00 + FC_RETOP + (HOST_a1 << 3) + (1 << 6); // sub FC_RETOP, a1, #1 - *(Bit16u*)(pos+2)=0xe000 + (18 >> 1); // b after_call (pc+18) + *(Bit16u*)pos=SUB_IMM3(FC_RETOP, HOST_a1, 1); // sub FC_RETOP, a1, #1 + *(Bit16u*)(pos+2)=B_FWD(18); // b after_call (pc+18) break; case t_SHLb: case t_SHLw: case t_SHLd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4080 + FC_RETOP + (HOST_a2 << 3); // lsl FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (16 >> 1); // b after_call (pc+16) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=LSL_REG(FC_RETOP, HOST_a2); // lsl FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(16); // b after_call (pc+16) break; case t_SHRb: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (24 << 6); // lsl FC_RETOP, a1, #24 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (FC_RETOP << 3) + (24 << 6); // lsr FC_RETOP, FC_RETOP, #24 - *(Bit16u*)(pos+4)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 24); // lsl FC_RETOP, a1, #24 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, FC_RETOP, 24); // lsr FC_RETOP, FC_RETOP, #24 + *(Bit16u*)(pos+4)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(14); // b after_call (pc+14) break; case t_SHRw: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsl FC_RETOP, a1, #16 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (FC_RETOP << 3) + (16 << 6); // lsr FC_RETOP, FC_RETOP, #16 - *(Bit16u*)(pos+4)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 16); // lsl FC_RETOP, a1, #16 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, FC_RETOP, 16); // lsr FC_RETOP, FC_RETOP, #16 + *(Bit16u*)(pos+4)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(14); // b after_call (pc+14) break; case t_SHRd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x40c0 + FC_RETOP + (HOST_a2 << 3); // lsr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (16 >> 1); // b after_call (pc+16) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=LSR_REG(FC_RETOP, HOST_a2); // lsr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(16); // b after_call (pc+16) break; case t_SARb: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (24 << 6); // lsl FC_RETOP, a1, #24 - *(Bit16u*)(pos+2)=0x1000 + FC_RETOP + (FC_RETOP << 3) + (24 << 6); // asr FC_RETOP, FC_RETOP, #24 - *(Bit16u*)(pos+4)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 24); // lsl FC_RETOP, a1, #24 + *(Bit16u*)(pos+2)=ASR_IMM(FC_RETOP, FC_RETOP, 24); // asr FC_RETOP, FC_RETOP, #24 + *(Bit16u*)(pos+4)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(14); // b after_call (pc+14) break; case t_SARw: - *(Bit16u*)pos=0x0000 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsl FC_RETOP, a1, #16 - *(Bit16u*)(pos+2)=0x1000 + FC_RETOP + (FC_RETOP << 3) + (16 << 6); // asr FC_RETOP, FC_RETOP, #16 - *(Bit16u*)(pos+4)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+6)=0xe000 + (14 >> 1); // b after_call (pc+14) + *(Bit16u*)pos=LSL_IMM(FC_RETOP, HOST_a1, 16); // lsl FC_RETOP, a1, #16 + *(Bit16u*)(pos+2)=ASR_IMM(FC_RETOP, FC_RETOP, 16); // asr FC_RETOP, FC_RETOP, #16 + *(Bit16u*)(pos+4)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+6)=B_FWD(14); // b after_call (pc+14) break; case t_SARd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x4100 + FC_RETOP + (HOST_a2 << 3); // asr FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (16 >> 1); // b after_call (pc+16) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ASR_REG(FC_RETOP, HOST_a2); // asr FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(16); // b after_call (pc+16) break; case t_RORb: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (24 << 6); // lsl a1, a1, #24 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (8 << 6); // lsr FC_RETOP, a1, #8 - *(Bit16u*)(pos+4)=0x4300 + HOST_a1 + (FC_RETOP << 3); // orr a1, FC_RETOP - *(Bit16u*)(pos+6)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+8)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+10)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 - *(Bit16u*)(pos+12)=0xe000 + (8 >> 1); // b after_call (pc+8) + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 24); // lsl a1, a1, #24 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, HOST_a1, 8); // lsr FC_RETOP, a1, #8 + *(Bit16u*)(pos+4)=ORR(HOST_a1, FC_RETOP); // orr a1, FC_RETOP + *(Bit16u*)(pos+6)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+8)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+10)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 + *(Bit16u*)(pos+12)=B_FWD(8); // b after_call (pc+8) break; case t_RORw: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (16 << 6); // lsl a1, a1, #16 - *(Bit16u*)(pos+2)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+4)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+6)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 - *(Bit16u*)(pos+8)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 16); // lsl a1, a1, #16 + *(Bit16u*)(pos+2)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+4)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+6)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 + *(Bit16u*)(pos+8)=B_FWD(12); // b after_call (pc+12) break; case t_RORd: - *(Bit16u*)pos=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+2)=0x41c0 + FC_RETOP + (HOST_a2 << 3); // ror FC_RETOP, a2 - *(Bit16u*)(pos+4)=0xe000 + (16 >> 1); // b after_call (pc+16) + *(Bit16u*)pos=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+2)=ROR_REG(FC_RETOP, HOST_a2); // ror FC_RETOP, a2 + *(Bit16u*)(pos+4)=B_FWD(16); // b after_call (pc+16) break; case t_ROLb: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (24 << 6); // lsl a1, a1, #24 - *(Bit16u*)(pos+2)=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+4)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (8 << 6); // lsr FC_RETOP, a1, #8 - *(Bit16u*)(pos+6)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+8)=0x4300 + HOST_a1 + (FC_RETOP << 3); // orr a1, FC_RETOP - *(Bit16u*)(pos+10)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+12)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+14)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 - *(Bit16u*)(pos+16)=0xe000 + (4 >> 1); // b after_call (pc+4) + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 24); // lsl a1, a1, #24 + *(Bit16u*)(pos+2)=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+4)=LSR_IMM(FC_RETOP, HOST_a1, 8); // lsr FC_RETOP, a1, #8 + *(Bit16u*)(pos+6)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+8)=ORR(HOST_a1, FC_RETOP); // orr a1, FC_RETOP + *(Bit16u*)(pos+10)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+12)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+14)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 + *(Bit16u*)(pos+16)=B_FWD(4); // b after_call (pc+4) break; case t_ROLw: - *(Bit16u*)pos=0x0000 + HOST_a1 + (HOST_a1 << 3) + (16 << 6); // lsl a1, a1, #16 - *(Bit16u*)(pos+2)=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+4)=0x0800 + FC_RETOP + (HOST_a1 << 3) + (16 << 6); // lsr FC_RETOP, a1, #16 - *(Bit16u*)(pos+6)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+8)=0x4300 + FC_RETOP + (HOST_a1 << 3); // orr FC_RETOP, a1 - *(Bit16u*)(pos+10)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 - *(Bit16u*)(pos+12)=0xe000 + (8 >> 1); // b after_call (pc+8) + *(Bit16u*)pos=LSL_IMM(HOST_a1, HOST_a1, 16); // lsl a1, a1, #16 + *(Bit16u*)(pos+2)=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+4)=LSR_IMM(FC_RETOP, HOST_a1, 16); // lsr FC_RETOP, a1, #16 + *(Bit16u*)(pos+6)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+8)=ORR(FC_RETOP, HOST_a1); // orr FC_RETOP, a1 + *(Bit16u*)(pos+10)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 + *(Bit16u*)(pos+12)=B_FWD(8); // b after_call (pc+8) break; case t_ROLd: - *(Bit16u*)pos=0x4240 + templo1 + (HOST_a2 << 3); // neg templo1, a2 - *(Bit16u*)(pos+2)=0x1c00 + FC_RETOP + (HOST_a1 << 3); // mov FC_RETOP, a1 - *(Bit16u*)(pos+4)=0x3000 + (templo1 << 8) + (32); // add templo1, #32 - *(Bit16u*)(pos+6)=0x41c0 + FC_RETOP + (templo1 << 3); // ror FC_RETOP, templo1 - *(Bit16u*)(pos+8)=0xe000 + (12 >> 1); // b after_call (pc+12) + *(Bit16u*)pos=NEG(templo1, HOST_a2); // neg templo1, a2 + *(Bit16u*)(pos+2)=MOV_REG(FC_RETOP, HOST_a1); // mov FC_RETOP, a1 + *(Bit16u*)(pos+4)=ADD_IMM8(templo1, 32); // add templo1, #32 + *(Bit16u*)(pos+6)=ROR_REG(FC_RETOP, templo1); // ror FC_RETOP, templo1 + *(Bit16u*)(pos+8)=B_FWD(12); // b after_call (pc+12) break; case t_NEGb: case t_NEGw: case t_NEGd: - *(Bit16u*)pos=0x4240 + FC_RETOP + (HOST_a1 << 3); // neg FC_RETOP, a1 - *(Bit16u*)(pos+2)=0xe000 + (18 >> 1); // b after_call (pc+18) + *(Bit16u*)pos=NEG(FC_RETOP, HOST_a1); // neg FC_RETOP, a1 + *(Bit16u*)(pos+2)=B_FWD(18); // b after_call (pc+18) break; default: *(Bit32u*)(pos+10)=(Bit32u)fct_ptr; // simple_func @@ -969,27 +1061,26 @@ static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) { static void cache_block_before_close(void) { } - #ifdef DRC_USE_SEGS_ADDR // mov 16bit value from Segs[index] into dest_reg using FC_SEGS_ADDR (index modulo 2 must be zero) // 16bit moves may destroy the upper 16bit of the destination register static void gen_mov_seg16_to_reg(HostReg dest_reg,Bitu index) { - cache_addw(0x4640 + templo1 + ((FC_SEGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_SEGS_ADDR - cache_addw(0x8800 + dest_reg + (templo1 << 3) + (index << 5)); // ldrh dest_reg, [templo1, #index] + cache_addw( MOV_LO_HI(templo1, FC_SEGS_ADDR) ); // mov templo1, FC_SEGS_ADDR + cache_addw( LDRH_IMM(dest_reg, templo1, index) ); // ldrh dest_reg, [templo1, #index] } // mov 32bit value from Segs[index] into dest_reg using FC_SEGS_ADDR (index modulo 4 must be zero) static void gen_mov_seg32_to_reg(HostReg dest_reg,Bitu index) { - cache_addw(0x4640 + templo1 + ((FC_SEGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_SEGS_ADDR - cache_addw(0x6800 + dest_reg + (templo1 << 3) + (index << 4)); // ldr dest_reg, [templo1, #index] + cache_addw( MOV_LO_HI(templo1, FC_SEGS_ADDR) ); // mov templo1, FC_SEGS_ADDR + cache_addw( LDR_IMM(dest_reg, templo1, index) ); // ldr dest_reg, [templo1, #index] } // add a 32bit value from Segs[index] to a full register using FC_SEGS_ADDR (index modulo 4 must be zero) static void gen_add_seg32_to_reg(HostReg reg,Bitu index) { - cache_addw(0x4640 + templo1 + ((FC_SEGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_SEGS_ADDR - cache_addw(0x6800 + templo2 + (templo1 << 3) + (index << 4)); // ldr templo2, [templo1, #index] - cache_addw(0x1800 + reg + (reg << 3) + (templo2 << 6)); // add reg, reg, templo2 + cache_addw( MOV_LO_HI(templo1, FC_SEGS_ADDR) ); // mov templo1, FC_SEGS_ADDR + cache_addw( LDR_IMM(templo2, templo1, index) ); // ldr templo2, [templo1, #index] + cache_addw( ADD_REG(reg, reg, templo2) ); // add reg, reg, templo2 } #endif @@ -999,24 +1090,24 @@ static void gen_add_seg32_to_reg(HostReg reg,Bitu index) { // mov 16bit value from cpu_regs[index] into dest_reg using FC_REGS_ADDR (index modulo 2 must be zero) // 16bit moves may destroy the upper 16bit of the destination register static void gen_mov_regval16_to_reg(HostReg dest_reg,Bitu index) { - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR - cache_addw(0x8800 + dest_reg + (templo2 << 3) + (index << 5)); // ldrh dest_reg, [templo2, #index] + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR + cache_addw( LDRH_IMM(dest_reg, templo2, index) ); // ldrh dest_reg, [templo2, #index] } // mov 32bit value from cpu_regs[index] into dest_reg using FC_REGS_ADDR (index modulo 4 must be zero) static void gen_mov_regval32_to_reg(HostReg dest_reg,Bitu index) { - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR - cache_addw(0x6800 + dest_reg + (templo2 << 3) + (index << 4)); // ldr dest_reg, [templo2, #index] + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR + cache_addw( LDR_IMM(dest_reg, templo2, index) ); // ldr dest_reg, [templo2, #index] } // move a 32bit (dword==true) or 16bit (dword==false) value from cpu_regs[index] into dest_reg using FC_REGS_ADDR (if dword==true index modulo 4 must be zero) (if dword==false index modulo 2 must be zero) // 16bit moves may destroy the upper 16bit of the destination register static void gen_mov_regword_to_reg(HostReg dest_reg,Bitu index,bool dword) { - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR if (dword) { - cache_addw(0x6800 + dest_reg + (templo2 << 3) + (index << 4)); // ldr dest_reg, [templo2, #index] + cache_addw( LDR_IMM(dest_reg, templo2, index) ); // ldr dest_reg, [templo2, #index] } else { - cache_addw(0x8800 + dest_reg + (templo2 << 3) + (index << 5)); // ldrh dest_reg, [templo2, #index] + cache_addw( LDRH_IMM(dest_reg, templo2, index) ); // ldrh dest_reg, [templo2, #index] } } @@ -1025,8 +1116,8 @@ static void gen_mov_regword_to_reg(HostReg dest_reg,Bitu index,bool dword) { // this function does not use FC_OP1/FC_OP2 as dest_reg as these // registers might not be directly byte-accessible on some architectures static void gen_mov_regbyte_to_reg_low(HostReg dest_reg,Bitu index) { - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR - cache_addw(0x7800 + dest_reg + (templo2 << 3) + (index << 6)); // ldrb dest_reg, [templo2, #index] + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR + cache_addw( LDRB_IMM(dest_reg, templo2, index) ); // ldrb dest_reg, [templo2, #index] } // move an 8bit value from cpu_regs[index] into dest_reg using FC_REGS_ADDR @@ -1034,45 +1125,45 @@ static void gen_mov_regbyte_to_reg_low(HostReg dest_reg,Bitu index) { // this function can use FC_OP1/FC_OP2 as dest_reg which are // not directly byte-accessible on some architectures static void INLINE gen_mov_regbyte_to_reg_low_canuseword(HostReg dest_reg,Bitu index) { - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR - cache_addw(0x7800 + dest_reg + (templo2 << 3) + (index << 6)); // ldrb dest_reg, [templo2, #index] + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR + cache_addw( LDRB_IMM(dest_reg, templo2, index) ); // ldrb dest_reg, [templo2, #index] } // add a 32bit value from cpu_regs[index] to a full register using FC_REGS_ADDR (index modulo 4 must be zero) static void gen_add_regval32_to_reg(HostReg reg,Bitu index) { - cache_addw(0x4640 + templo2 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo2, FC_REGS_ADDR - cache_addw(0x6800 + templo1 + (templo2 << 3) + (index << 4)); // ldr templo1, [templo2, #index] - cache_addw(0x1800 + reg + (reg << 3) + (templo1 << 6)); // add reg, reg, templo1 + cache_addw( MOV_LO_HI(templo2, FC_REGS_ADDR) ); // mov templo2, FC_REGS_ADDR + cache_addw( LDR_IMM(templo1, templo2, index) ); // ldr templo1, [templo2, #index] + cache_addw( ADD_REG(reg, reg, templo1) ); // add reg, reg, templo1 } // move 16bit of register into cpu_regs[index] using FC_REGS_ADDR (index modulo 2 must be zero) static void gen_mov_regval16_from_reg(HostReg src_reg,Bitu index) { - cache_addw(0x4640 + templo1 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_REGS_ADDR - cache_addw(0x8000 + src_reg + (templo1 << 3) + (index << 5)); // strh src_reg, [templo1, #index] + cache_addw( MOV_LO_HI(templo1, FC_REGS_ADDR) ); // mov templo1, FC_REGS_ADDR + cache_addw( STRH_IMM(src_reg, templo1, index) ); // strh src_reg, [templo1, #index] } // move 32bit of register into cpu_regs[index] using FC_REGS_ADDR (index modulo 4 must be zero) static void gen_mov_regval32_from_reg(HostReg src_reg,Bitu index) { - cache_addw(0x4640 + templo1 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_REGS_ADDR - cache_addw(0x6000 + src_reg + (templo1 << 3) + (index << 4)); // str src_reg, [templo1, #index] + cache_addw( MOV_LO_HI(templo1, FC_REGS_ADDR) ); // mov templo1, FC_REGS_ADDR + cache_addw( STR_IMM(src_reg, templo1, index) ); // str src_reg, [templo1, #index] } // move 32bit (dword==true) or 16bit (dword==false) of a register into cpu_regs[index] using FC_REGS_ADDR (if dword==true index modulo 4 must be zero) (if dword==false index modulo 2 must be zero) static void gen_mov_regword_from_reg(HostReg src_reg,Bitu index,bool dword) { - cache_addw(0x4640 + templo1 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_REGS_ADDR + cache_addw( MOV_LO_HI(templo1, FC_REGS_ADDR) ); // mov templo1, FC_REGS_ADDR if (dword) { - cache_addw(0x6000 + src_reg + (templo1 << 3) + (index << 4)); // str src_reg, [templo1, #index] + cache_addw( STR_IMM(src_reg, templo1, index) ); // str src_reg, [templo1, #index] } else { - cache_addw(0x8000 + src_reg + (templo1 << 3) + (index << 5)); // strh src_reg, [templo1, #index] + cache_addw( STRH_IMM(src_reg, templo1, index) ); // strh src_reg, [templo1, #index] } } // move the lowest 8bit of a register into cpu_regs[index] using FC_REGS_ADDR static void gen_mov_regbyte_from_reg_low(HostReg src_reg,Bitu index) { - cache_addw(0x4640 + templo1 + ((FC_REGS_ADDR - HOST_r8) << 3)); // mov templo1, FC_REGS_ADDR - cache_addw(0x7000 + src_reg + (templo1 << 3) + (index << 6)); // strb src_reg, [templo1, #index] + cache_addw( MOV_LO_HI(templo1, FC_REGS_ADDR) ); // mov templo1, FC_REGS_ADDR + cache_addw( STRB_IMM(src_reg, templo1, index) ); // strb src_reg, [templo1, #index] } #endif diff --git a/src/debug/debug_win32.cpp b/src/debug/debug_win32.cpp index ee58add..15fe8a7 100644 --- a/src/debug/debug_win32.cpp +++ b/src/debug/debug_win32.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2002-2007 The DOSBox Team + * Copyright (C) 2002-2009 The DOSBox Team * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +22,10 @@ #include #include +#ifndef min +#define min(a,b) ((a)<(b)?(a):(b)) +#endif + /* Have to remember where i ripped this code sometime ago.