mirror of
https://github.com/retro100/dosbox-wii.git
synced 2024-06-28 23:26:09 +02:00
219 lines
6.3 KiB
C++
219 lines
6.3 KiB
C++
/*
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* Copyright (C) 2002-2019 The DOSBox Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include "dosbox.h"
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#include "inout.h"
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#include "render.h"
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#include "vga.h"
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/*
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3C6h (R/W): PEL Mask
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bit 0-7 This register is anded with the palette index sent for each dot.
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Should be set to FFh.
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3C7h (R): DAC State Register
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bit 0-1 0 indicates the DAC is in Write Mode and 3 indicates Read mode.
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3C7h (W): PEL Address Read Mode
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bit 0-7 The PEL data register (0..255) to be read from 3C9h.
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Note: After reading the 3 bytes at 3C9h this register will increment,
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pointing to the next data register.
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3C8h (R/W): PEL Address Write Mode
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bit 0-7 The PEL data register (0..255) to be written to 3C9h.
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Note: After writing the 3 bytes at 3C9h this register will increment, pointing
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to the next data register.
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3C9h (R/W): PEL Data Register
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bit 0-5 Color value
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Note: Each read or write of this register will cycle through first the
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registers for Red, Blue and Green, then increment the appropriate
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address register, thus the entire palette can be loaded by writing 0 to
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the PEL Address Write Mode register 3C8h and then writing all 768 bytes
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of the palette to this register.
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*/
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enum {DAC_READ,DAC_WRITE};
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static void VGA_DAC_SendColor( Bitu index, Bitu src ) {
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const Bit8u red = vga.dac.rgb[src].red;
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const Bit8u green = vga.dac.rgb[src].green;
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const Bit8u blue = vga.dac.rgb[src].blue;
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//Set entry in 16bit output lookup table
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vga.dac.xlat16[index] = ((blue>>1)&0x1f) | (((green)&0x3f)<<5) | (((red>>1)&0x1f) << 11);
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RENDER_SetPal( index, (red << 2) | ( red >> 4 ), (green << 2) | ( green >> 4 ), (blue << 2) | ( blue >> 4 ) );
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}
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static void VGA_DAC_UpdateColor( Bitu index ) {
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Bitu maskIndex = index & vga.dac.pel_mask;
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VGA_DAC_SendColor( index, maskIndex );
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}
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static void write_p3c6(Bitu port,Bitu val,Bitu iolen) {
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if ( vga.dac.pel_mask != val ) {
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LOG(LOG_VGAMISC,LOG_NORMAL)("VGA:DCA:Pel Mask set to %X", val);
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vga.dac.pel_mask = val;
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for ( Bitu i = 0;i<256;i++)
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VGA_DAC_UpdateColor( i );
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}
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}
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static Bitu read_p3c6(Bitu port,Bitu iolen) {
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return vga.dac.pel_mask;
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}
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static void write_p3c7(Bitu port,Bitu val,Bitu iolen) {
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vga.dac.read_index=val;
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vga.dac.pel_index=0;
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vga.dac.state=DAC_READ;
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vga.dac.write_index= val + 1;
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}
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static Bitu read_p3c7(Bitu port,Bitu iolen) {
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if (vga.dac.state==DAC_READ) return 0x3;
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else return 0x0;
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}
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static void write_p3c8(Bitu port,Bitu val,Bitu iolen) {
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vga.dac.write_index=val;
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vga.dac.pel_index=0;
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vga.dac.state=DAC_WRITE;
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vga.dac.read_index= val - 1;
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}
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static Bitu read_p3c8(Bitu port, Bitu iolen){
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return vga.dac.write_index;
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}
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static void write_p3c9(Bitu port,Bitu val,Bitu iolen) {
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val&=0x3f;
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switch (vga.dac.pel_index) {
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case 0:
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vga.dac.rgb[vga.dac.write_index].red=val;
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vga.dac.pel_index=1;
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break;
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case 1:
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vga.dac.rgb[vga.dac.write_index].green=val;
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vga.dac.pel_index=2;
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break;
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case 2:
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vga.dac.rgb[vga.dac.write_index].blue=val;
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switch (vga.mode) {
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case M_VGA:
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case M_LIN8:
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VGA_DAC_UpdateColor( vga.dac.write_index );
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if ( GCC_UNLIKELY( vga.dac.pel_mask != 0xff)) {
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Bitu index = vga.dac.write_index;
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if ( (index & vga.dac.pel_mask) == index ) {
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for ( Bitu i = index+1;i<256;i++)
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if ( (i & vga.dac.pel_mask) == index )
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VGA_DAC_UpdateColor( i );
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}
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}
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break;
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default:
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/* Check for attributes and DAC entry link */
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for (Bitu i=0;i<16;i++) {
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if (vga.dac.combine[i]==vga.dac.write_index) {
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VGA_DAC_SendColor( i, vga.dac.write_index );
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}
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}
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}
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vga.dac.write_index++;
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// vga.dac.read_index = vga.dac.write_index - 1;//disabled as it breaks Wari
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vga.dac.pel_index=0;
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break;
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default:
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LOG(LOG_VGAGFX,LOG_NORMAL)("VGA:DAC:Illegal Pel Index"); //If this can actually happen that will be the day
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break;
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};
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}
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static Bitu read_p3c9(Bitu port,Bitu iolen) {
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Bit8u ret;
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switch (vga.dac.pel_index) {
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case 0:
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ret=vga.dac.rgb[vga.dac.read_index].red;
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vga.dac.pel_index=1;
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break;
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case 1:
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ret=vga.dac.rgb[vga.dac.read_index].green;
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vga.dac.pel_index=2;
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break;
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case 2:
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ret=vga.dac.rgb[vga.dac.read_index].blue;
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vga.dac.read_index++;
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vga.dac.pel_index=0;
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// vga.dac.write_index=vga.dac.read_index+1;//disabled as it breaks wari
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break;
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default:
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LOG(LOG_VGAMISC,LOG_NORMAL)("VGA:DAC:Illegal Pel Index"); //If this can actually happen that will be the day
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ret=0;
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break;
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}
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return ret;
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}
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void VGA_DAC_CombineColor(Bit8u attr,Bit8u pal) {
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/* Check if this is a new color */
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vga.dac.combine[attr]=pal;
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switch (vga.mode) {
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case M_LIN8:
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break;
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case M_VGA:
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// used by copper demo; almost no video card seems to suport it
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if(!IS_VGA_ARCH || (svgaCard!=SVGA_None)) break;
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default:
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VGA_DAC_SendColor( attr, pal );
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}
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}
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void VGA_DAC_SetEntry(Bitu entry,Bit8u red,Bit8u green,Bit8u blue) {
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//Should only be called in machine != vga
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vga.dac.rgb[entry].red=red;
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vga.dac.rgb[entry].green=green;
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vga.dac.rgb[entry].blue=blue;
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for (Bitu i=0;i<16;i++)
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if (vga.dac.combine[i]==entry)
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VGA_DAC_SendColor( i, i );
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}
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void VGA_SetupDAC(void) {
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vga.dac.first_changed=256;
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vga.dac.bits=6;
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vga.dac.pel_mask=0xff;
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vga.dac.pel_index=0;
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vga.dac.state=DAC_READ;
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vga.dac.read_index=0;
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vga.dac.write_index=0;
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if (IS_VGA_ARCH) {
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/* Setup the DAC IO port Handlers */
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IO_RegisterWriteHandler(0x3c6,write_p3c6,IO_MB);
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IO_RegisterReadHandler(0x3c6,read_p3c6,IO_MB);
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IO_RegisterWriteHandler(0x3c7,write_p3c7,IO_MB);
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IO_RegisterReadHandler(0x3c7,read_p3c7,IO_MB);
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IO_RegisterWriteHandler(0x3c8,write_p3c8,IO_MB);
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IO_RegisterReadHandler(0x3c8,read_p3c8,IO_MB);
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IO_RegisterWriteHandler(0x3c9,write_p3c9,IO_MB);
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IO_RegisterReadHandler(0x3c9,read_p3c9,IO_MB);
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}
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}
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