mirror of
https://github.com/retro100/dosbox-wii.git
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708 lines
21 KiB
C
708 lines
21 KiB
C
/*
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* Copyright (C) 2002-2019 The DOSBox Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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// some configuring defines that specify the capabilities of this architecture
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// or aspects of the recompiling
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// protect FC_ADDR over function calls if necessaray
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// #define DRC_PROTECT_ADDR_REG
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// try to use non-flags generating functions if possible
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#define DRC_FLAGS_INVALIDATION
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// try to replace _simple functions by code
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#define DRC_FLAGS_INVALIDATION_DCODE
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// type with the same size as a pointer
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#define DRC_PTR_SIZE_IM Bit64u
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// calling convention modifier
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#define DRC_CALL_CONV /* nothing */
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#define DRC_FC /* nothing */
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// register mapping
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typedef Bit8u HostReg;
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#define HOST_EAX 0
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#define HOST_ECX 1
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#define HOST_EDX 2
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#define HOST_EBX 3
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#define HOST_ESI 6
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#define HOST_EDI 7
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// register that holds function return values
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#define FC_RETOP HOST_EAX
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// register used for address calculations, if the ABI does not
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// state that this register is preserved across function calls
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// then define DRC_PROTECT_ADDR_REG above
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#define FC_ADDR HOST_EBX
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#if defined (_WIN64)
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#define FC_OP1 HOST_ECX
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#define FC_OP2 HOST_EDX
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#else
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// register that holds the first parameter
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#define FC_OP1 HOST_EDI
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// register that holds the second parameter
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#define FC_OP2 HOST_ESI
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#endif
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// special register that holds the third parameter for _R3 calls (byte accessible)
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#define FC_OP3 HOST_EAX
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// register that holds byte-accessible temporary values
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#define FC_TMP_BA1 HOST_ECX
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// register that holds byte-accessible temporary values
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#define FC_TMP_BA2 HOST_EDX
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// temporary register for LEA
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#define TEMP_REG_DRC HOST_ESI
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// move a full register from reg_src to reg_dst
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static void gen_mov_regs(HostReg reg_dst,HostReg reg_src) {
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if (reg_dst==reg_src) return;
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cache_addb(0x8b); // mov reg_dst,reg_src
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cache_addb(0xc0+(reg_dst<<3)+reg_src);
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}
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static void gen_mov_reg_qword(HostReg dest_reg,Bit64u imm);
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// This function generates an instruction with register addressing and a memory location
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static INLINE void gen_reg_memaddr(HostReg reg,void* data,Bit8u op,Bit8u prefix=0) {
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Bit64s diff = (Bit64s)data-((Bit64s)cache.pos+(prefix?7:6));
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// if ((diff<0x80000000LL) && (diff>-0x80000000LL)) { //clang messes itself up on this...
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if ( (diff>>63) == (diff>>31) ) { //signed bit extend, test to see if value fits in a Bit32s
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// mov reg,[rip+diff] (or similar, depending on the op) to fetch *data
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if(prefix) cache_addb(prefix);
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cache_addb(op);
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cache_addb(0x05+(reg<<3));
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// RIP-relative addressing is offset after the instruction
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cache_addd((Bit32u)(((Bit64u)diff)&0xffffffffLL));
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} else if ((Bit64u)data<0x100000000LL) {
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// mov reg,[data] (or similar, depending on the op) when absolute address of data is <4GB
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if(prefix) cache_addb(prefix);
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cache_addb(op);
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cache_addw(0x2504+(reg<<3));
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cache_addd((Bit32u)(((Bit64u)data)&0xffffffffLL));
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} else {
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// load 64-bit data into tmp_reg and do mov reg,[tmp_reg] (or similar, depending on the op)
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HostReg tmp_reg = HOST_EAX;
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if(reg == HOST_EAX) tmp_reg = HOST_ECX;
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cache_addb(0x50+tmp_reg); // push rax/rcx
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gen_mov_reg_qword(tmp_reg,(Bit64u)data);
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if(prefix) cache_addb(prefix);
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cache_addb(op);
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cache_addb(tmp_reg+(reg<<3));
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cache_addb(0x58+tmp_reg); // pop rax/rcx
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}
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}
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// Same as above, but with immediate addressing and a memory location
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static INLINE void gen_memaddr(Bitu modreg,void* data,Bitu off,Bitu imm,Bit8u op,Bit8u prefix=0) {
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Bit64s diff = (Bit64s)data-((Bit64s)cache.pos+off+(prefix?7:6));
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// if ((diff<0x80000000LL) && (diff>-0x80000000LL)) {
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if ( (diff>>63) == (diff>>31) ) {
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// RIP-relative addressing is offset after the instruction
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if(prefix) cache_addb(prefix);
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cache_addw(op+((modreg+1)<<8));
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cache_addd((Bit32u)(((Bit64u)diff)&0xffffffffLL));
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switch(off) {
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case 1: cache_addb(((Bit8u)imm&0xff)); break;
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case 2: cache_addw(((Bit16u)imm&0xffff)); break;
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case 4: cache_addd(((Bit32u)imm&0xffffffff)); break;
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}
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} else if ((Bit64u)data<0x100000000LL) {
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if(prefix) cache_addb(prefix);
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cache_addw(op+(modreg<<8));
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cache_addb(0x25);
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cache_addd((Bit32u)(((Bit64u)data)&0xffffffffLL));
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switch(off) {
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case 1: cache_addb(((Bit8u)imm&0xff)); break;
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case 2: cache_addw(((Bit16u)imm&0xffff)); break;
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case 4: cache_addd(((Bit32u)imm&0xffffffff)); break;
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}
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} else {
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HostReg tmp_reg = HOST_EAX;
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cache_addb(0x50+tmp_reg); // push rax
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gen_mov_reg_qword(tmp_reg,(Bit64u)data);
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if(prefix) cache_addb(prefix);
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cache_addw(op+((modreg-4+tmp_reg)<<8));
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switch(off) {
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case 1: cache_addb(((Bit8u)imm&0xff)); break;
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case 2: cache_addw(((Bit16u)imm&0xffff)); break;
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case 4: cache_addd(((Bit32u)imm&0xffffffff)); break;
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}
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cache_addb(0x58+tmp_reg); // pop rax
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}
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}
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// move a 32bit (dword==true) or 16bit (dword==false) value from memory into dest_reg
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// 16bit moves may destroy the upper 16bit of the destination register
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static void gen_mov_word_to_reg(HostReg dest_reg,void* data,bool dword,Bit8u prefix=0) {
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if (!dword) gen_reg_memaddr(dest_reg,data,0xb7,0x0f); // movzx reg,[data] - zero extend data, fixes LLVM compile where the called function does not extend the parameters
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else gen_reg_memaddr(dest_reg,data,0x8b,prefix); // mov reg,[data]
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}
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// move a 16bit constant value into dest_reg
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// the upper 16bit of the destination register may be destroyed
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static void gen_mov_word_to_reg_imm(HostReg dest_reg,Bit16u imm) {
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cache_addb(0xb8+dest_reg); // mov reg,imm
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cache_addd((Bit32u)imm);
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}
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// move a 32bit constant value into dest_reg
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static void gen_mov_dword_to_reg_imm(HostReg dest_reg,Bit32u imm) {
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cache_addb(0xb8+dest_reg); // mov reg,imm
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cache_addd(imm);
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}
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// move a 64bit constant value into a full register
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static void gen_mov_reg_qword(HostReg dest_reg,Bit64u imm) {
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if (imm==(Bit32u)imm) {
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gen_mov_dword_to_reg_imm(dest_reg, (Bit32u)imm);
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return;
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}
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cache_addb(0x48);
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cache_addb(0xb8+dest_reg); // mov dest_reg,imm
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cache_addq(imm);
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}
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// move 32bit (dword==true) or 16bit (dword==false) of a register into memory
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static void gen_mov_word_from_reg(HostReg src_reg,void* dest,bool dword,Bit8u prefix=0) {
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gen_reg_memaddr(src_reg,dest,0x89,(dword?prefix:0x66)); // mov [data],reg
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}
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// move an 8bit value from memory into dest_reg
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// the upper 24bit of the destination register can be destroyed
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// this function does not use FC_OP1/FC_OP2 as dest_reg as these
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// registers might not be directly byte-accessible on some architectures
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static void gen_mov_byte_to_reg_low(HostReg dest_reg,void* data) {
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gen_reg_memaddr(dest_reg,data,0xb6,0x0f); // movzx reg,[data]
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}
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// move an 8bit value from memory into dest_reg
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// the upper 24bit of the destination register can be destroyed
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// this function can use FC_OP1/FC_OP2 as dest_reg which are
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// not directly byte-accessible on some architectures
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static void gen_mov_byte_to_reg_low_canuseword(HostReg dest_reg,void* data) {
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gen_reg_memaddr(dest_reg,data,0xb6,0x0f); // movzx reg,[data]
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}
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// move an 8bit constant value into dest_reg
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// the upper 24bit of the destination register can be destroyed
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// this function does not use FC_OP1/FC_OP2 as dest_reg as these
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// registers might not be directly byte-accessible on some architectures
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static void gen_mov_byte_to_reg_low_imm(HostReg dest_reg,Bit8u imm) {
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cache_addb(0xb8+dest_reg); // mov reg,imm
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cache_addd((Bit32u)imm);
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}
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// move an 8bit constant value into dest_reg
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// the upper 24bit of the destination register can be destroyed
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// this function can use FC_OP1/FC_OP2 as dest_reg which are
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// not directly byte-accessible on some architectures
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static void gen_mov_byte_to_reg_low_imm_canuseword(HostReg dest_reg,Bit8u imm) {
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cache_addb(0xb8+dest_reg); // mov reg,imm
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cache_addd((Bit32u)imm);
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}
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// move the lowest 8bit of a register into memory
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static void gen_mov_byte_from_reg_low(HostReg src_reg,void* dest) {
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gen_reg_memaddr(src_reg,dest,0x88); // mov byte [data],reg
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}
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// convert an 8bit word to a 32bit dword
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// the register is zero-extended (sign==false) or sign-extended (sign==true)
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static void gen_extend_byte(bool sign,HostReg reg) {
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cache_addw(0xb60f+(sign?0x800:0)); // movsx/movzx
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cache_addb(0xc0+(reg<<3)+reg);
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}
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// convert a 16bit word to a 32bit dword
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// the register is zero-extended (sign==false) or sign-extended (sign==true)
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static void gen_extend_word(bool sign,HostReg reg) {
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cache_addw(0xb70f+(sign?0x800:0)); // movsx/movzx
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cache_addb(0xc0+(reg<<3)+reg);
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}
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// add a 32bit value from memory to a full register
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static void gen_add(HostReg reg,void* op) {
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gen_reg_memaddr(reg,op,0x03); // add reg,[data]
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}
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// add a 32bit constant value to a full register
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static void gen_add_imm(HostReg reg,Bit32u imm) {
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if (!imm) return;
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cache_addw(0xc081+(reg<<8)); // add reg,imm
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cache_addd(imm);
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}
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// and a 32bit constant value with a full register
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static void gen_and_imm(HostReg reg,Bit32u imm) {
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cache_addw(0xe081+(reg<<8)); // and reg,imm
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cache_addd(imm);
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}
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// move a 32bit constant value into memory
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static void gen_mov_direct_dword(void* dest,Bit32u imm) {
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gen_memaddr(0x4,dest,4,imm,0xc7); // mov [data],imm
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}
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// move an address into memory
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static void INLINE gen_mov_direct_ptr(void* dest,DRC_PTR_SIZE_IM imm) {
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gen_mov_reg_qword(HOST_EAX,imm);
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gen_mov_word_from_reg(HOST_EAX,dest,true,0x48); // 0x48 prefixes full 64-bit mov
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}
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// add an 8bit constant value to a memory value
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static void gen_add_direct_byte(void* dest,Bit8s imm) {
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if (!imm) return;
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gen_memaddr(0x4,dest,1,imm,0x83); // add [data],imm
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}
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// add a 32bit (dword==true) or 16bit (dword==false) constant value to a memory value
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static void gen_add_direct_word(void* dest,Bit32u imm,bool dword) {
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if (!imm) return;
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if ((imm<128) && dword) {
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gen_add_direct_byte(dest,(Bit8s)imm);
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return;
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}
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gen_memaddr(0x4,dest,(dword?4:2),imm,0x81,(dword?0:0x66)); // add [data],imm
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}
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// subtract an 8bit constant value from a memory value
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static void gen_sub_direct_byte(void* dest,Bit8s imm) {
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if (!imm) return;
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gen_memaddr(0x2c,dest,1,imm,0x83);
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}
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// subtract a 32bit (dword==true) or 16bit (dword==false) constant value from a memory value
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static void gen_sub_direct_word(void* dest,Bit32u imm,bool dword) {
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if (!imm) return;
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if ((imm<128) && dword) {
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gen_sub_direct_byte(dest,(Bit8s)imm);
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return;
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}
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gen_memaddr(0x2c,dest,(dword?4:2),imm,0x81,(dword?0:0x66)); // sub [data],imm
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}
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// effective address calculation, destination is dest_reg
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// scale_reg is scaled by scale (scale_reg*(2^scale)) and
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// added to dest_reg, then the immediate value is added
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static INLINE void gen_lea(HostReg dest_reg,HostReg scale_reg,Bitu scale,Bits imm) {
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Bit8u rm_base;
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Bitu imm_size;
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if (!imm) {
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imm_size=0; rm_base=0x0; //no imm
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} else if ((imm>=-128 && imm<=127)) {
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imm_size=1; rm_base=0x40; //Signed byte imm
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} else {
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imm_size=4; rm_base=0x80; //Signed dword imm
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}
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// ea_reg := ea_reg+scale_reg*(2^scale)+imm
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cache_addb(0x48);
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cache_addb(0x8d); //LEA
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cache_addb(0x04+(dest_reg << 3)+rm_base); //The sib indicator
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cache_addb(dest_reg+(scale_reg<<3)+(scale<<6));
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switch (imm_size) {
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case 0: break;
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case 1:cache_addb(imm);break;
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case 4:cache_addd(imm);break;
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}
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}
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// effective address calculation, destination is dest_reg
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// dest_reg is scaled by scale (dest_reg*(2^scale)),
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// then the immediate value is added
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static INLINE void gen_lea(HostReg dest_reg,Bitu scale,Bits imm) {
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// ea_reg := ea_reg*(2^scale)+imm
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// ea_reg := op2 *(2^scale)+imm
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cache_addb(0x48);
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cache_addb(0x8d); //LEA
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cache_addb(0x04+(dest_reg<<3));
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cache_addb(0x05+(dest_reg<<3)+(scale<<6));
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cache_addd(imm); // always add dword immediate
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}
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// generate a call to a parameterless function
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static void INLINE gen_call_function_raw(void * func) {
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cache_addw(0xb848);
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cache_addq((Bit64u)func);
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cache_addw(0xd0ff);
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}
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// generate a call to a function with paramcount parameters
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// note: the parameters are loaded in the architecture specific way
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// using the gen_load_param_ functions below
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static Bit64u INLINE gen_call_function_setup(void * func,Bitu paramcount,bool fastcall=false) {
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Bit64u proc_addr = (Bit64u)cache.pos;
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gen_call_function_raw(func);
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return proc_addr;
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}
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// load an immediate value as param'th function parameter
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static void INLINE gen_load_param_imm(Bitu imm,Bitu param) {
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// move an immediate 32bit value into a 64bit param reg
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switch (param) {
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case 0: // mov param1,imm32
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gen_mov_dword_to_reg_imm(FC_OP1,(Bit32u)imm);
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break;
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case 1: // mov param2,imm32
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gen_mov_dword_to_reg_imm(FC_OP2,(Bit32u)imm);
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break;
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#if defined (_WIN64)
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case 2: // mov r8d,imm32
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cache_addw(0xb841);
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cache_addd((Bit32u)imm);
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break;
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case 3: // mov r9d,imm32
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cache_addw(0xb941);
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cache_addd((Bit32u)imm);
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break;
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#else
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case 2: // mov rdx,imm32
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gen_mov_dword_to_reg_imm(HOST_EDX,(Bit32u)imm);
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break;
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case 3: // mov rcx,imm32
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gen_mov_dword_to_reg_imm(HOST_ECX,(Bit32u)imm);
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break;
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#endif
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default:
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E_Exit("I(mm) >4 params unsupported");
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break;
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}
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}
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// load an address as param'th function parameter
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static void INLINE gen_load_param_addr(DRC_PTR_SIZE_IM addr,Bitu param) {
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// move an immediate 64bit value into a 64bit param reg
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switch (param) {
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case 0: // mov param1,addr64
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gen_mov_reg_qword(FC_OP1,addr);
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break;
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case 1: // mov param2,addr64
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gen_mov_reg_qword(FC_OP2,addr);
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break;
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#if defined (_WIN64)
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case 2: // mov r8,addr64
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cache_addw(0xb849);
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cache_addq(addr);
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break;
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case 3: // mov r9,addr64
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cache_addw(0xb949);
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cache_addq(addr);
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break;
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#else
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case 2: // mov rdx,addr64
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gen_mov_reg_qword(HOST_EDX,addr);
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break;
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case 3: // mov rcx,addr64
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gen_mov_reg_qword(HOST_ECX,addr);
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break;
|
|
#endif
|
|
default:
|
|
E_Exit("A(ddr) >4 params unsupported");
|
|
break;
|
|
}
|
|
}
|
|
|
|
// load a host-register as param'th function parameter
|
|
static void INLINE gen_load_param_reg(Bitu reg,Bitu param) {
|
|
// move a register into a 64bit param reg, {inputregs}!={outputregs}
|
|
switch (param) {
|
|
case 0: // mov param1,reg&7
|
|
gen_mov_regs(FC_OP1,reg&7);
|
|
break;
|
|
case 1: // mov param2,reg&7
|
|
gen_mov_regs(FC_OP2,reg&7);
|
|
break;
|
|
#if defined (_WIN64)
|
|
case 2: // mov r8,reg&7
|
|
cache_addw(0x8949);
|
|
cache_addb(0xc0 + ((reg & 7) << 3));
|
|
break;
|
|
case 3: // mov r9,reg&7
|
|
cache_addw(0x8949);
|
|
cache_addb(0xc1 + ((reg & 7) << 3));
|
|
break;
|
|
#else
|
|
case 2: // mov rdx,reg&7
|
|
gen_mov_regs(HOST_EDX,reg&7);
|
|
break;
|
|
case 3: // mov rcx,reg&7
|
|
gen_mov_regs(HOST_ECX,reg&7);
|
|
break;
|
|
#endif
|
|
default:
|
|
E_Exit("R(eg) >4 params unsupported");
|
|
break;
|
|
}
|
|
}
|
|
|
|
// load a value from memory as param'th function parameter
|
|
static void INLINE gen_load_param_mem(Bitu mem,Bitu param) {
|
|
// move memory content into a 64bit param reg
|
|
switch (param) {
|
|
case 0: // mov param1,[mem]
|
|
gen_mov_word_to_reg(FC_OP1,(void*)mem,true);
|
|
break;
|
|
case 1: // mov param2,[mem]
|
|
gen_mov_word_to_reg(FC_OP2,(void*)mem,true);
|
|
break;
|
|
#if defined (_WIN64)
|
|
case 2: // mov r8d,[mem]
|
|
gen_mov_word_to_reg(0,(void*)mem,true,0x44); // 0x44, use x64 rXd regs
|
|
break;
|
|
case 3: // mov r9d,[mem]
|
|
gen_mov_word_to_reg(1,(void*)mem,true,0x44); // 0x44, use x64 rXd regs
|
|
break;
|
|
#else
|
|
case 2: // mov edx,[mem]
|
|
gen_mov_word_to_reg(HOST_EDX,(void*)mem,true);
|
|
break;
|
|
case 3: // mov ecx,[mem]
|
|
gen_mov_word_to_reg(HOST_ECX,(void*)mem,true);
|
|
break;
|
|
#endif
|
|
default:
|
|
E_Exit("R(eg) >4 params unsupported");
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
// jump to an address pointed at by ptr, offset is in imm
|
|
static void gen_jmp_ptr(void * ptr,Bits imm=0) {
|
|
cache_addw(0xa148); // mov rax,[data]
|
|
cache_addq((Bit64u)ptr);
|
|
|
|
cache_addb(0xff); // jmp [rax+imm]
|
|
if (!imm) {
|
|
cache_addb(0x20);
|
|
} else if ((imm>=-128 && imm<=127)) {
|
|
cache_addb(0x60);
|
|
cache_addb(imm);
|
|
} else {
|
|
cache_addb(0xa0);
|
|
cache_addd(imm);
|
|
}
|
|
}
|
|
|
|
|
|
// short conditional jump (+-127 bytes) if register is zero
|
|
// the destination is set by gen_fill_branch() later
|
|
static Bit64u gen_create_branch_on_zero(HostReg reg,bool dword) {
|
|
if (!dword) cache_addb(0x66);
|
|
cache_addb(0x0b); // or reg,reg
|
|
cache_addb(0xc0+reg+(reg<<3));
|
|
|
|
cache_addw(0x0074); // jz addr
|
|
return ((Bit64u)cache.pos-1);
|
|
}
|
|
|
|
// short conditional jump (+-127 bytes) if register is nonzero
|
|
// the destination is set by gen_fill_branch() later
|
|
static Bit64u gen_create_branch_on_nonzero(HostReg reg,bool dword) {
|
|
if (!dword) cache_addb(0x66);
|
|
cache_addb(0x0b); // or reg,reg
|
|
cache_addb(0xc0+reg+(reg<<3));
|
|
|
|
cache_addw(0x0075); // jnz addr
|
|
return ((Bit64u)cache.pos-1);
|
|
}
|
|
|
|
// calculate relative offset and fill it into the location pointed to by data
|
|
static void gen_fill_branch(DRC_PTR_SIZE_IM data) {
|
|
#if C_DEBUG
|
|
Bit64s len=(Bit64u)cache.pos-data;
|
|
if (len<0) len=-len;
|
|
if (len>126) LOG_MSG("Big jump %d",len);
|
|
#endif
|
|
*(Bit8u*)data=(Bit8u)((Bit64u)cache.pos-data-1);
|
|
}
|
|
|
|
// conditional jump if register is nonzero
|
|
// for isdword==true the 32bit of the register are tested
|
|
// for isdword==false the lowest 8bit of the register are tested
|
|
static Bit64u gen_create_branch_long_nonzero(HostReg reg,bool isdword) {
|
|
// isdword: cmp reg32,0
|
|
// not isdword: cmp reg8,0
|
|
cache_addb(0x0a+(isdword?1:0)); // or reg,reg
|
|
cache_addb(0xc0+reg+(reg<<3));
|
|
|
|
cache_addw(0x850f); // jnz
|
|
cache_addd(0);
|
|
return ((Bit64u)cache.pos-4);
|
|
}
|
|
|
|
// compare 32bit-register against zero and jump if value less/equal than zero
|
|
static Bit64u gen_create_branch_long_leqzero(HostReg reg) {
|
|
cache_addw(0xf883+(reg<<8));
|
|
cache_addb(0x00); // cmp reg,0
|
|
|
|
cache_addw(0x8e0f); // jle
|
|
cache_addd(0);
|
|
return ((Bit64u)cache.pos-4);
|
|
}
|
|
|
|
// calculate long relative offset and fill it into the location pointed to by data
|
|
static void gen_fill_branch_long(Bit64u data) {
|
|
*(Bit32u*)data=(Bit32u)((Bit64u)cache.pos-data-4);
|
|
}
|
|
|
|
static void gen_run_code(void) {
|
|
cache_addw(0x5355); // push rbp,rbx
|
|
cache_addb(0x56); // push rsi
|
|
cache_addd(0x20EC8348); // sub rsp, 32
|
|
cache_addb(0x48);cache_addw(0x2D8D);cache_addd(2); // lea rbp, [rip+2]
|
|
cache_addw(0xE0FF+(FC_OP1<<8)); // jmp FC_OP1
|
|
cache_addd(0x20C48348); // add rsp, 32
|
|
cache_addd(0xC35D5B5E); // pop rsi,rbx,rbp;ret
|
|
}
|
|
|
|
// return from a function
|
|
static void gen_return_function(void) {
|
|
cache_addw(0xE5FF); // jmp rbp
|
|
}
|
|
|
|
#ifdef DRC_FLAGS_INVALIDATION
|
|
// called when a call to a function can be replaced by a
|
|
// call to a simpler function
|
|
// check gen_call_function_raw and gen_call_function_setup
|
|
// for the targeted code
|
|
static void gen_fill_function_ptr(Bit8u * pos,void* fct_ptr,Bitu flags_type) {
|
|
#ifdef DRC_FLAGS_INVALIDATION_DCODE
|
|
// try to avoid function calls but rather directly fill in code
|
|
switch (flags_type) {
|
|
case t_ADDb:
|
|
case t_ADDw:
|
|
case t_ADDd:
|
|
// mov eax,FC_OP1; add eax,FC_OP2
|
|
*(Bit32u*)(pos+0)=0xc001c089+(FC_OP1<<11)+(FC_OP2<<27);
|
|
*(Bit32u*)(pos+4)=0x909006eb; // skip
|
|
*(Bit32u*)(pos+8)=0x90909090;
|
|
return;
|
|
case t_ORb:
|
|
case t_ORw:
|
|
case t_ORd:
|
|
// mov eax,FC_OP1; or eax,FC_OP2
|
|
*(Bit32u*)(pos+0)=0xc009c089+(FC_OP1<<11)+(FC_OP2<<27);
|
|
*(Bit32u*)(pos+4)=0x909006eb; // skip
|
|
*(Bit32u*)(pos+8)=0x90909090;
|
|
return;
|
|
case t_ANDb:
|
|
case t_ANDw:
|
|
case t_ANDd:
|
|
// mov eax,FC_OP1; and eax,FC_OP2
|
|
*(Bit32u*)(pos+0)=0xc021c089+(FC_OP1<<11)+(FC_OP2<<27);
|
|
*(Bit32u*)(pos+4)=0x909006eb; // skip
|
|
*(Bit32u*)(pos+8)=0x90909090;
|
|
return;
|
|
case t_SUBb:
|
|
case t_SUBw:
|
|
case t_SUBd:
|
|
// mov eax,FC_OP1; sub eax,FC_OP2
|
|
*(Bit32u*)(pos+0)=0xc029c089+(FC_OP1<<11)+(FC_OP2<<27);
|
|
*(Bit32u*)(pos+4)=0x909006eb; // skip
|
|
*(Bit32u*)(pos+8)=0x90909090;
|
|
return;
|
|
case t_XORb:
|
|
case t_XORw:
|
|
case t_XORd:
|
|
// mov eax,FC_OP1; xor eax,FC_OP2
|
|
*(Bit32u*)(pos+0)=0xc031c089+(FC_OP1<<11)+(FC_OP2<<27);
|
|
*(Bit32u*)(pos+4)=0x909006eb; // skip
|
|
*(Bit32u*)(pos+8)=0x90909090;
|
|
return;
|
|
case t_CMPb:
|
|
case t_CMPw:
|
|
case t_CMPd:
|
|
case t_TESTb:
|
|
case t_TESTw:
|
|
case t_TESTd:
|
|
*(Bit32u*)(pos+0)=0x90900aeb; // skip
|
|
*(Bit32u*)(pos+4)=0x90909090;
|
|
*(Bit32u*)(pos+8)=0x90909090;
|
|
return;
|
|
case t_INCb:
|
|
case t_INCw:
|
|
case t_INCd:
|
|
*(Bit32u*)(pos+0)=0xc0ffc089+(FC_OP1<<11); // mov eax,ecx; inc eax
|
|
*(Bit32u*)(pos+4)=0x909006eb; // skip
|
|
*(Bit32u*)(pos+8)=0x90909090;
|
|
return;
|
|
case t_DECb:
|
|
case t_DECw:
|
|
case t_DECd:
|
|
*(Bit32u*)(pos+0)=0xc8ffc089+(FC_OP1<<11); // mov eax, FC_OP1; dec eax
|
|
*(Bit32u*)(pos+4)=0x909006eb; // skip
|
|
*(Bit32u*)(pos+8)=0x90909090;
|
|
return;
|
|
case t_NEGb:
|
|
case t_NEGw:
|
|
case t_NEGd:
|
|
*(Bit32u*)(pos+0)=0xd8f7c089+(FC_OP1<<11); // mov eax, FC_OP1; neg eax
|
|
*(Bit32u*)(pos+4)=0x909006eb; // skip
|
|
*(Bit32u*)(pos+8)=0x90909090;
|
|
return;
|
|
}
|
|
#endif
|
|
*(Bit64u*)(pos+2)=(Bit64u)fct_ptr; // fill function pointer
|
|
}
|
|
#endif
|
|
|
|
static void cache_block_closing(Bit8u* block_start,Bitu block_size) { }
|
|
|
|
static void cache_block_before_close(void) { }
|