mirror of
https://github.com/retro100/dosbox-wii.git
synced 2024-11-04 17:35:10 +01:00
170 lines
4.5 KiB
C
170 lines
4.5 KiB
C
/*
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* Copyright (C) 2002-2019 The DOSBox Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef DOSBOX_REGS_H
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#define DOSBOX_REGS_H
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#ifndef DOSBOX_MEM_H
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#include "mem.h"
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#endif
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#define FLAG_CF 0x00000001
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#define FLAG_PF 0x00000004
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#define FLAG_AF 0x00000010
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#define FLAG_ZF 0x00000040
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#define FLAG_SF 0x00000080
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#define FLAG_OF 0x00000800
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#define FLAG_TF 0x00000100
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#define FLAG_IF 0x00000200
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#define FLAG_DF 0x00000400
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#define FLAG_IOPL 0x00003000
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#define FLAG_NT 0x00004000
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#define FLAG_VM 0x00020000
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#define FLAG_AC 0x00040000
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#define FLAG_ID 0x00200000
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#define FMASK_TEST (FLAG_CF | FLAG_PF | FLAG_AF | FLAG_ZF | FLAG_SF | FLAG_OF)
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#define FMASK_NORMAL (FMASK_TEST | FLAG_DF | FLAG_TF | FLAG_IF )
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#define FMASK_ALL (FMASK_NORMAL | FLAG_IOPL | FLAG_NT)
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#define SETFLAGBIT(TYPE,TEST) if (TEST) reg_flags|=FLAG_ ## TYPE; else reg_flags&=~FLAG_ ## TYPE
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#define GETFLAG(TYPE) (reg_flags & FLAG_ ## TYPE)
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#define GETFLAGBOOL(TYPE) ((reg_flags & FLAG_ ## TYPE) ? true : false )
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#define GETFLAG_IOPL ((reg_flags & FLAG_IOPL) >> 12)
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struct Segment {
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Bit16u val;
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PhysPt phys; /* The phyiscal address start in emulated machine */
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};
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enum SegNames { es=0,cs,ss,ds,fs,gs};
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struct Segments {
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Bit16u val[8];
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PhysPt phys[8];
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};
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union GenReg32 {
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Bit32u dword[1];
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Bit16u word[2];
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Bit8u byte[4];
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};
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#ifdef WORDS_BIGENDIAN
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#define DW_INDEX 0
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#define W_INDEX 1
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#define BH_INDEX 2
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#define BL_INDEX 3
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#else
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#define DW_INDEX 0
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#define W_INDEX 0
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#define BH_INDEX 1
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#define BL_INDEX 0
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#endif
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struct CPU_Regs {
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GenReg32 regs[8],ip;
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Bitu flags;
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};
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extern Segments Segs;
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extern CPU_Regs cpu_regs;
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static INLINE PhysPt SegPhys(SegNames index) {
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return Segs.phys[index];
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}
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static INLINE Bit16u SegValue(SegNames index) {
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return (Bit16u)Segs.val[index];
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}
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static INLINE RealPt RealMakeSeg(SegNames index,Bit16u off) {
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return RealMake(SegValue(index),off);
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}
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static INLINE void SegSet16(Bitu index,Bit16u val) {
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Segs.val[index]=val;
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Segs.phys[index]=val << 4;
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}
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enum {
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REGI_AX, REGI_CX, REGI_DX, REGI_BX,
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REGI_SP, REGI_BP, REGI_SI, REGI_DI
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};
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enum {
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REGI_AL, REGI_CL, REGI_DL, REGI_BL,
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REGI_AH, REGI_CH, REGI_DH, REGI_BH
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};
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//macros to convert a 3-bit register index to the correct register
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#define reg_8l(reg) (cpu_regs.regs[(reg)].byte[BL_INDEX])
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#define reg_8h(reg) (cpu_regs.regs[(reg)].byte[BH_INDEX])
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#define reg_8(reg) ((reg) & 4 ? reg_8h((reg) & 3) : reg_8l((reg) & 3))
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#define reg_16(reg) (cpu_regs.regs[(reg)].word[W_INDEX])
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#define reg_32(reg) (cpu_regs.regs[(reg)].dword[DW_INDEX])
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#define reg_al cpu_regs.regs[REGI_AX].byte[BL_INDEX]
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#define reg_ah cpu_regs.regs[REGI_AX].byte[BH_INDEX]
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#define reg_ax cpu_regs.regs[REGI_AX].word[W_INDEX]
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#define reg_eax cpu_regs.regs[REGI_AX].dword[DW_INDEX]
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#define reg_bl cpu_regs.regs[REGI_BX].byte[BL_INDEX]
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#define reg_bh cpu_regs.regs[REGI_BX].byte[BH_INDEX]
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#define reg_bx cpu_regs.regs[REGI_BX].word[W_INDEX]
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#define reg_ebx cpu_regs.regs[REGI_BX].dword[DW_INDEX]
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#define reg_cl cpu_regs.regs[REGI_CX].byte[BL_INDEX]
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#define reg_ch cpu_regs.regs[REGI_CX].byte[BH_INDEX]
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#define reg_cx cpu_regs.regs[REGI_CX].word[W_INDEX]
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#define reg_ecx cpu_regs.regs[REGI_CX].dword[DW_INDEX]
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#define reg_dl cpu_regs.regs[REGI_DX].byte[BL_INDEX]
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#define reg_dh cpu_regs.regs[REGI_DX].byte[BH_INDEX]
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#define reg_dx cpu_regs.regs[REGI_DX].word[W_INDEX]
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#define reg_edx cpu_regs.regs[REGI_DX].dword[DW_INDEX]
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#define reg_si cpu_regs.regs[REGI_SI].word[W_INDEX]
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#define reg_esi cpu_regs.regs[REGI_SI].dword[DW_INDEX]
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#define reg_di cpu_regs.regs[REGI_DI].word[W_INDEX]
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#define reg_edi cpu_regs.regs[REGI_DI].dword[DW_INDEX]
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#define reg_sp cpu_regs.regs[REGI_SP].word[W_INDEX]
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#define reg_esp cpu_regs.regs[REGI_SP].dword[DW_INDEX]
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#define reg_bp cpu_regs.regs[REGI_BP].word[W_INDEX]
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#define reg_ebp cpu_regs.regs[REGI_BP].dword[DW_INDEX]
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#define reg_ip cpu_regs.ip.word[W_INDEX]
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#define reg_eip cpu_regs.ip.dword[DW_INDEX]
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#define reg_flags cpu_regs.flags
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#endif
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