mirror of
https://github.com/retro100/dosbox-wii.git
synced 2024-11-17 15:49:15 +01:00
394 lines
11 KiB
C++
394 lines
11 KiB
C++
/*
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* Copyright (C) 2002-2010 The DOSBox Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include "dosbox.h"
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#include "mem.h"
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#include "inout.h"
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#include "int10.h"
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#define ACTL_MAX_REG 0x14
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static INLINE void ResetACTL(void) {
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IO_Read(real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS) + 6);
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}
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static INLINE void WriteTandyACTL(Bit8u creg,Bit8u val) {
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IO_Write(VGAREG_TDY_ADDRESS,creg);
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if (machine==MCH_TANDY) IO_Write(VGAREG_TDY_DATA,val);
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else IO_Write(VGAREG_PCJR_DATA,val);
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}
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void INT10_SetSinglePaletteRegister(Bit8u reg,Bit8u val) {
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switch (machine) {
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case MCH_PCJR:
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reg&=0xf;
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IO_Read(VGAREG_TDY_RESET);
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WriteTandyACTL(reg+0x10,val);
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IO_Write(0x3da,0x0); // palette back on
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break;
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case MCH_TANDY:
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// TODO waits for vertical retrace
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switch(vga.mode) {
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case M_TANDY2:
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if (reg >= 0x10) break;
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else if (reg==1) reg = 0x1f;
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else reg |= 0x10;
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WriteTandyACTL(reg+0x10,val);
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break;
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case M_TANDY4: {
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if (CurMode->mode!=0x0a) {
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// Palette values are kept constand by the BIOS.
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// The four colors are mapped to special palette values by hardware.
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// 3D8/3D9 registers influence this mapping. We need to figure out
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// which entry is used for the requested color.
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if (reg > 3) break;
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if (reg != 0) { // 0 is assumed to be at 0
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Bit8u color_select=real_readb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL);
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reg = reg*2+8; // Green Red Brown
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if (color_select& 0x20) reg++; // Cyan Magenta White
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}
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WriteTandyACTL(reg+0x10,val);
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}
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// 4-color high resolution mode 0x0a isn't handled specially
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else WriteTandyACTL(reg+0x10,val);
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break;
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}
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default:
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WriteTandyACTL(reg+0x10,val);
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break;
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}
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IO_Write(0x3da,0x0); // palette back on
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break;
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case EGAVGA_ARCH_CASE:
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if (!IS_VGA_ARCH) reg&=0x1f;
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if(reg<=ACTL_MAX_REG) {
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ResetACTL();
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IO_Write(VGAREG_ACTL_ADDRESS,reg);
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IO_Write(VGAREG_ACTL_WRITE_DATA,val);
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}
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IO_Write(VGAREG_ACTL_ADDRESS,32); //Enable output and protect palette
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break;
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}
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}
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void INT10_SetOverscanBorderColor(Bit8u val) {
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switch (machine) {
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case TANDY_ARCH_CASE:
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IO_Read(VGAREG_TDY_RESET);
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WriteTandyACTL(0x02,val);
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break;
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case EGAVGA_ARCH_CASE:
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ResetACTL();
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IO_Write(VGAREG_ACTL_ADDRESS,0x11);
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IO_Write(VGAREG_ACTL_WRITE_DATA,val);
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IO_Write(VGAREG_ACTL_ADDRESS,32); //Enable output and protect palette
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break;
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}
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}
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void INT10_SetAllPaletteRegisters(PhysPt data) {
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switch (machine) {
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case TANDY_ARCH_CASE:
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IO_Read(VGAREG_TDY_RESET);
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// First the colors
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for(Bit8u i=0;i<0x10;i++) {
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WriteTandyACTL(i+0x10,mem_readb(data));
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data++;
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}
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// Then the border
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WriteTandyACTL(0x02,mem_readb(data));
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break;
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case EGAVGA_ARCH_CASE:
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ResetACTL();
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// First the colors
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for(Bit8u i=0;i<0x10;i++) {
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IO_Write(VGAREG_ACTL_ADDRESS,i);
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IO_Write(VGAREG_ACTL_WRITE_DATA,mem_readb(data));
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data++;
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}
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// Then the border
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IO_Write(VGAREG_ACTL_ADDRESS,0x11);
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IO_Write(VGAREG_ACTL_WRITE_DATA,mem_readb(data));
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IO_Write(VGAREG_ACTL_ADDRESS,32); //Enable output and protect palette
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break;
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}
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}
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void INT10_ToggleBlinkingBit(Bit8u state) {
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if(IS_VGA_ARCH) {
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Bit8u value;
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// state&=0x01;
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if ((state>1) && (svgaCard==SVGA_S3Trio)) return;
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ResetACTL();
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IO_Write(VGAREG_ACTL_ADDRESS,0x10);
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value=IO_Read(VGAREG_ACTL_READ_DATA);
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if (state<=1) {
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value&=0xf7;
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value|=state<<3;
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}
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ResetACTL();
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IO_Write(VGAREG_ACTL_ADDRESS,0x10);
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IO_Write(VGAREG_ACTL_WRITE_DATA,value);
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IO_Write(VGAREG_ACTL_ADDRESS,32); //Enable output and protect palette
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if (state<=1) {
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Bit8u msrval=real_readb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR)&0xdf;
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if (state) msrval|=0x20;
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real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,msrval);
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}
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} else { // EGA
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// Usually it reads this from the mode list in ROM
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if (CurMode->type!=M_TEXT) return;
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Bit8u value = (CurMode->cwidth==9)? 0x4:0x0;
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if (state) value |= 0x8;
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ResetACTL();
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IO_Write(VGAREG_ACTL_ADDRESS,0x10);
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IO_Write(VGAREG_ACTL_WRITE_DATA,value);
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IO_Write(VGAREG_ACTL_ADDRESS,0x20);
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Bit8u msrval=real_readb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR)& ~0x20;
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if (state) msrval|=0x20;
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real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,msrval);
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}
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}
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void INT10_GetSinglePaletteRegister(Bit8u reg,Bit8u * val) {
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if(reg<=ACTL_MAX_REG) {
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ResetACTL();
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IO_Write(VGAREG_ACTL_ADDRESS,reg+32);
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*val=IO_Read(VGAREG_ACTL_READ_DATA);
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IO_Write(VGAREG_ACTL_WRITE_DATA,*val);
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}
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}
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void INT10_GetOverscanBorderColor(Bit8u * val) {
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ResetACTL();
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IO_Write(VGAREG_ACTL_ADDRESS,0x11+32);
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*val=IO_Read(VGAREG_ACTL_READ_DATA);
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IO_Write(VGAREG_ACTL_WRITE_DATA,*val);
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}
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void INT10_GetAllPaletteRegisters(PhysPt data) {
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ResetACTL();
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// First the colors
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for(Bit8u i=0;i<0x10;i++) {
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IO_Write(VGAREG_ACTL_ADDRESS,i);
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mem_writeb(data,IO_Read(VGAREG_ACTL_READ_DATA));
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ResetACTL();
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data++;
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}
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// Then the border
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IO_Write(VGAREG_ACTL_ADDRESS,0x11+32);
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mem_writeb(data,IO_Read(VGAREG_ACTL_READ_DATA));
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ResetACTL();
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}
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void INT10_SetSingleDACRegister(Bit8u index,Bit8u red,Bit8u green,Bit8u blue) {
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IO_Write(VGAREG_DAC_WRITE_ADDRESS,(Bit8u)index);
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if ((real_readb(BIOSMEM_SEG,BIOSMEM_MODESET_CTL)&0x06)==0) {
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IO_Write(VGAREG_DAC_DATA,red);
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IO_Write(VGAREG_DAC_DATA,green);
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IO_Write(VGAREG_DAC_DATA,blue);
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} else {
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/* calculate clamped intensity, taken from VGABIOS */
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Bit32u i=(( 77*red + 151*green + 28*blue ) + 0x80) >> 8;
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Bit8u ic=(i>0x3f) ? 0x3f : ((Bit8u)(i & 0xff));
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IO_Write(VGAREG_DAC_DATA,ic);
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IO_Write(VGAREG_DAC_DATA,ic);
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IO_Write(VGAREG_DAC_DATA,ic);
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}
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}
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void INT10_GetSingleDACRegister(Bit8u index,Bit8u * red,Bit8u * green,Bit8u * blue) {
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IO_Write(VGAREG_DAC_READ_ADDRESS,index);
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*red=IO_Read(VGAREG_DAC_DATA);
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*green=IO_Read(VGAREG_DAC_DATA);
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*blue=IO_Read(VGAREG_DAC_DATA);
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}
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void INT10_SetDACBlock(Bit16u index,Bit16u count,PhysPt data) {
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IO_Write(VGAREG_DAC_WRITE_ADDRESS,(Bit8u)index);
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if ((real_readb(BIOSMEM_SEG,BIOSMEM_MODESET_CTL)&0x06)==0) {
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for (;count>0;count--) {
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IO_Write(VGAREG_DAC_DATA,mem_readb(data++));
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IO_Write(VGAREG_DAC_DATA,mem_readb(data++));
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IO_Write(VGAREG_DAC_DATA,mem_readb(data++));
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}
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} else {
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for (;count>0;count--) {
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Bit8u red=mem_readb(data++);
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Bit8u green=mem_readb(data++);
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Bit8u blue=mem_readb(data++);
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/* calculate clamped intensity, taken from VGABIOS */
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Bit32u i=(( 77*red + 151*green + 28*blue ) + 0x80) >> 8;
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Bit8u ic=(i>0x3f) ? 0x3f : ((Bit8u)(i & 0xff));
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IO_Write(VGAREG_DAC_DATA,ic);
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IO_Write(VGAREG_DAC_DATA,ic);
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IO_Write(VGAREG_DAC_DATA,ic);
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}
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}
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}
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void INT10_GetDACBlock(Bit16u index,Bit16u count,PhysPt data) {
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IO_Write(VGAREG_DAC_READ_ADDRESS,(Bit8u)index);
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for (;count>0;count--) {
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mem_writeb(data++,IO_Read(VGAREG_DAC_DATA));
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mem_writeb(data++,IO_Read(VGAREG_DAC_DATA));
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mem_writeb(data++,IO_Read(VGAREG_DAC_DATA));
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}
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}
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void INT10_SelectDACPage(Bit8u function,Bit8u mode) {
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ResetACTL();
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IO_Write(VGAREG_ACTL_ADDRESS,0x10);
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Bit8u old10=IO_Read(VGAREG_ACTL_READ_DATA);
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if (!function) { //Select paging mode
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if (mode) old10|=0x80;
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else old10&=0x7f;
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//IO_Write(VGAREG_ACTL_ADDRESS,0x10);
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IO_Write(VGAREG_ACTL_WRITE_DATA,old10);
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} else { //Select page
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IO_Write(VGAREG_ACTL_WRITE_DATA,old10);
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if (!(old10 & 0x80)) mode<<=2;
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mode&=0xf;
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IO_Write(VGAREG_ACTL_ADDRESS,0x14);
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IO_Write(VGAREG_ACTL_WRITE_DATA,mode);
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}
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IO_Write(VGAREG_ACTL_ADDRESS,32); //Enable output and protect palette
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}
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void INT10_GetDACPage(Bit8u* mode,Bit8u* page) {
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ResetACTL();
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IO_Write(VGAREG_ACTL_ADDRESS,0x10);
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Bit8u reg10=IO_Read(VGAREG_ACTL_READ_DATA);
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IO_Write(VGAREG_ACTL_WRITE_DATA,reg10);
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*mode=(reg10&0x80)?0x01:0x00;
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IO_Write(VGAREG_ACTL_ADDRESS,0x14);
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*page=IO_Read(VGAREG_ACTL_READ_DATA);
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IO_Write(VGAREG_ACTL_WRITE_DATA,*page);
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if(*mode) {
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*page&=0xf;
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} else {
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*page&=0xc;
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*page>>=2;
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}
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}
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void INT10_SetPelMask(Bit8u mask) {
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IO_Write(VGAREG_PEL_MASK,mask);
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}
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void INT10_GetPelMask(Bit8u & mask) {
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mask=IO_Read(VGAREG_PEL_MASK);
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}
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void INT10_SetBackgroundBorder(Bit8u val) {
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Bit8u color_select=real_readb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL);
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color_select=(color_select & 0xe0) | (val & 0x1f);
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real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,color_select);
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if (machine == MCH_CGA || machine == MCH_TANDY)
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IO_Write(0x3d9,color_select);
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else if (machine == MCH_PCJR) {
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IO_Read(VGAREG_TDY_RESET); // reset the flipflop
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if (vga.mode!=M_TANDY_TEXT) {
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IO_Write(VGAREG_TDY_ADDRESS, 0x10);
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IO_Write(VGAREG_PCJR_DATA, color_select&0xf);
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}
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IO_Write(VGAREG_TDY_ADDRESS, 0x2); // border color
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IO_Write(VGAREG_PCJR_DATA, color_select&0xf);
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}
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else if (IS_EGAVGA_ARCH) {
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val = ((val << 1) & 0x10) | (val & 0x7);
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/* Aways set the overscan color */
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INT10_SetSinglePaletteRegister( 0x11, val );
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/* Don't set any extra colors when in text mode */
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if (CurMode->mode <= 3)
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return;
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INT10_SetSinglePaletteRegister( 0, val );
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val = (color_select & 0x10) | 2 | ((color_select & 0x20) >> 5);
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INT10_SetSinglePaletteRegister( 1, val );
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val+=2;
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INT10_SetSinglePaletteRegister( 2, val );
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val+=2;
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INT10_SetSinglePaletteRegister( 3, val );
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}
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}
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void INT10_SetColorSelect(Bit8u val) {
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Bit8u temp=real_readb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL);
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temp=(temp & 0xdf) | ((val & 1) ? 0x20 : 0x0);
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real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,temp);
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if (machine == MCH_CGA || machine==MCH_TANDY)
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IO_Write(0x3d9,temp);
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else if (machine == MCH_PCJR) {
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switch(vga.mode) {
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case M_TANDY2:
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IO_Write(VGAREG_TDY_ADDRESS, 0x11);
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IO_Write(VGAREG_PCJR_DATA, val&1? 0xf:0);
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break;
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case M_TANDY4:
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for(Bit8u i = 0x11; i < 0x14; i++) {
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const Bit8u t4_table[] = {0,2,4,6, 0,3,5,0xf};
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IO_Write(VGAREG_TDY_ADDRESS, i);
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IO_Write(VGAREG_PCJR_DATA, t4_table[(i-0x10)+(val&1? 4:0)]);
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}
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break;
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default:
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// 16-color modes: always write the same palette
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for(Bit8u i = 0x11; i < 0x20; i++) {
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IO_Write(VGAREG_TDY_ADDRESS, i);
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IO_Write(VGAREG_PCJR_DATA, i-0x10);
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}
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break;
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}
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IO_Write(VGAREG_TDY_ADDRESS, 0); // enable palette
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}
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else if (IS_EGAVGA_ARCH) {
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if (CurMode->mode <= 3) //Maybe even skip the total function!
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return;
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val = (temp & 0x10) | 2 | val;
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INT10_SetSinglePaletteRegister( 1, val );
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val+=2;
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INT10_SetSinglePaletteRegister( 2, val );
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val+=2;
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INT10_SetSinglePaletteRegister( 3, val );
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}
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}
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void INT10_PerformGrayScaleSumming(Bit16u start_reg,Bit16u count) {
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if (count>0x100) count=0x100;
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for (Bitu ct=0; ct<count; ct++) {
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IO_Write(VGAREG_DAC_READ_ADDRESS,start_reg+ct);
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Bit8u red=IO_Read(VGAREG_DAC_DATA);
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Bit8u green=IO_Read(VGAREG_DAC_DATA);
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Bit8u blue=IO_Read(VGAREG_DAC_DATA);
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/* calculate clamped intensity, taken from VGABIOS */
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Bit32u i=(( 77*red + 151*green + 28*blue ) + 0x80) >> 8;
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Bit8u ic=(i>0x3f) ? 0x3f : ((Bit8u)(i & 0xff));
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INT10_SetSingleDACRegister(start_reg+ct,ic,ic,ic);
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}
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}
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