mirror of
https://github.com/retro100/dosbox-wii.git
synced 2024-09-29 18:28:35 +02:00
264 lines
6.8 KiB
C++
264 lines
6.8 KiB
C++
/*
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* Copyright (C) 2002-2004 The DOSBox Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <string.h>
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#include "dosbox.h"
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#include "mem.h"
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#include "inout.h"
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#include "dma.h"
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#include "pic.h"
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DmaChannel *DmaChannels[8];
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DmaController *DmaControllers[2];
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static void DMA_WriteControllerReg(DmaController * cont,Bitu reg,Bitu val,Bitu len) {
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DmaChannel * chan;Bitu i;
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Bitu base=cont->chanbase;
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switch (reg) {
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case 0x0:case 0x2:case 0x4:case 0x6:
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chan=DmaChannels[base+(reg >> 1)];
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cont->flipflop=!cont->flipflop;
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if (cont->flipflop) {
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chan->baseaddr=(chan->baseaddr&0xff00)|val;
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chan->curraddr=(chan->curraddr&0xff00)|val;
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} else {
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chan->baseaddr=(chan->baseaddr&0x00ff)|(val << 8);
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chan->curraddr=(chan->curraddr&0x00ff)|(val << 8);
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}
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break;
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case 0x1:case 0x3:case 0x5:case 0x7:
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chan=DmaChannels[base+(reg >> 1)];
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cont->flipflop=!cont->flipflop;
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if (cont->flipflop) {
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chan->basecnt=(chan->basecnt&0xff00)|val;
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chan->currcnt=(chan->currcnt&0xff00)|val;
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} else {
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chan->basecnt=(chan->basecnt&0x00ff)|(val << 8);
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chan->currcnt=(chan->currcnt&0x00ff)|(val << 8);
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}
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break;
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case 0x8: /* Comand reg not used */
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break;
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case 0x9: /* Request registers, memory to memory */
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//TODO Warning?
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break;
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case 0xa: /* Mask Register */
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chan=DmaChannels[base+(val & 3 )];
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chan->SetMask((val & 0x4)>0);
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break;
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case 0xb: /* Mode Register */
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chan=DmaChannels[base+(val & 3 )];
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chan->autoinit=(val & 0x10) > 0;
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chan->increment=(val & 0x20) > 0;
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//TODO Maybe other bits?
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break;
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case 0xc: /* Clear Flip/Flip */
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cont->flipflop=false;
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break;
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case 0xd: /* Master Clear/Reset */
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for (i=0;i<4;i++) {
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DmaChannels[base+i]->SetMask(true);
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DmaChannels[base+i]->tcount=false;
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}
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cont->flipflop=false;
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break;
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case 0xe: /* Clear Mask register */
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for (i=0;i<4;i++) {
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DmaChannels[base+i]->SetMask(false);
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}
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break;
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case 0xf: /* Multiple Mask register */
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for (i=0;i<4;i++) {
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DmaChannels[base+i]->SetMask(val & 1);
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val>>=1;
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}
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break;
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}
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}
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static Bitu DMA_ReadControllerReg(DmaController * cont,Bitu reg,Bitu len) {
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DmaChannel * chan;Bitu i,ret;
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Bitu base=cont->chanbase;
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switch (reg) {
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case 0x0:case 0x2:case 0x4:case 0x6:
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chan=DmaChannels[base+(reg >> 1)];
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cont->flipflop=!cont->flipflop;
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if (cont->flipflop) {
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return chan->curraddr & 0xff;
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} else {
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return (chan->curraddr >> 8) & 0xff;
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}
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case 0x1:case 0x3:case 0x5:case 0x7:
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chan=DmaChannels[base+(reg >> 1)];
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cont->flipflop=!cont->flipflop;
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if (cont->flipflop) {
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return chan->currcnt & 0xff;
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} else {
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return (chan->currcnt >> 8) & 0xff;
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}
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case 0x8:
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ret=0;
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for (i=0;i<4;i++) {
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chan=DmaChannels[base+i];
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if (chan->tcount) ret|=1 << i;
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chan->tcount=false;
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if (chan->callback) ret|=1 << (i+4);
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}
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return ret;
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default:
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LOG_MSG("Trying to read undefined DMA Red %x",reg);
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}
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return 0xffffffff;
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}
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static void DMA_Write_Port(Bitu port,Bitu val,Bitu iolen) {
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if (port<0x10) {
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DMA_WriteControllerReg(DmaControllers[0],port,val,1);
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} else if (port>=0xc0 && port <=0xdf) {
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DMA_WriteControllerReg(DmaControllers[1],(port-0xc0) >> 1,val,1);
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} else switch (port) {
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case 0x81:DmaChannels[2]->SetPage(val);break;
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case 0x82:DmaChannels[3]->SetPage(val);break;
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case 0x83:DmaChannels[1]->SetPage(val);break;
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case 0x89:DmaChannels[6]->SetPage(val);break;
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case 0x8a:DmaChannels[7]->SetPage(val);break;
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case 0x8b:DmaChannels[5]->SetPage(val);break;
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}
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}
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static Bitu DMA_Read_Port(Bitu port,Bitu iolen) {
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if (port<0x10) {
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return DMA_ReadControllerReg(DmaControllers[0],port,iolen);
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} else if (port>=0xc0 && port <=0xdf) {
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return DMA_ReadControllerReg(DmaControllers[1],(port-0xc0) >> 1,iolen);
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} else switch (port) {
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case 0x81:return DmaChannels[2]->pagenum;
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case 0x82:return DmaChannels[3]->pagenum;
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case 0x83:return DmaChannels[1]->pagenum;
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case 0x89:return DmaChannels[6]->pagenum;
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case 0x8a:return DmaChannels[7]->pagenum;
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case 0x8b:return DmaChannels[5]->pagenum;
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}
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return 0;
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}
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DmaChannel::DmaChannel(Bit8u num, bool dma16) {
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masked = true;
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callback = NULL;
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if(num == 4) return;
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channum = num;
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DMA16 = dma16 ? 0x1 : 0x0;
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pagenum = 0;
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pagebase = 0;
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baseaddr = 0;
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curraddr = 0;
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basecnt = 0;
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currcnt = 0;
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increment = true;
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autoinit = false;
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tcount = false;
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}
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Bitu DmaChannel::Read(Bitu want, Bit8u * buffer) {
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Bitu done=0;
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again:
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Bitu left=(currcnt+1);
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if (want<left) {
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MEM_BlockRead(pagebase+(curraddr << DMA16),buffer,want << DMA16);
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done+=want;
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curraddr+=want;
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currcnt-=want;
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} else {
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MEM_BlockRead(pagebase+(curraddr << DMA16),buffer,left << DMA16);
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buffer+=left << DMA16;
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want-=left;
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done+=left;
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ReachedTC();
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if (autoinit) {
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currcnt=basecnt;
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curraddr=baseaddr;
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if (want) goto again;
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} else {
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curraddr+=left;
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currcnt=0xffff;
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masked=true;
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DoCallBack(DMA_TRANSFEREND);
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}
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}
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return done;
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}
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Bitu DmaChannel::Write(Bitu want, Bit8u * buffer) {
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Bitu done=0;
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again:
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Bitu left=(currcnt+1);
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if (want<left) {
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MEM_BlockWrite(pagebase+(curraddr << DMA16),buffer,want << DMA16);
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done+=want;
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curraddr+=want;
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currcnt-=want;
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} else {
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MEM_BlockWrite(pagebase+(curraddr << DMA16),buffer,left << DMA16);
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buffer+=left << DMA16;
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want-=left;
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done+=left;
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ReachedTC();
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if (autoinit) {
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currcnt=basecnt;
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curraddr=baseaddr;
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if (want) goto again;
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} else {
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curraddr+=left;
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currcnt=0xffff;
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masked=true;
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DoCallBack(DMA_TRANSFEREND);
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}
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}
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return done;
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}
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void DMA_Init(Section* sec) {
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Bitu i;
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DmaControllers[0] = new DmaController(0);
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DmaControllers[1] = new DmaController(1);
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for(i=0;i<8;i++) {
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DmaChannels[i] = new DmaChannel(i,i>=4);
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}
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for (i=0;i<0x10;i++) {
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Bitu mask=IO_MB;
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if (i<8) mask|=IO_MW;
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IO_RegisterWriteHandler(i,DMA_Write_Port,mask);
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IO_RegisterReadHandler(i,DMA_Read_Port,mask);
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if (machine==MCH_VGA) {
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IO_RegisterWriteHandler(0xc0+i*2,DMA_Write_Port,mask);
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IO_RegisterReadHandler(0xc0+i*2,DMA_Read_Port,mask);
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}
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}
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IO_RegisterWriteHandler(0x81,DMA_Write_Port,IO_MB,3);
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IO_RegisterWriteHandler(0x89,DMA_Write_Port,IO_MB,3);
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IO_RegisterReadHandler(0x81,DMA_Read_Port,IO_MB,3);
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IO_RegisterReadHandler(0x89,DMA_Read_Port,IO_MB,3);
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}
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