mirror of
https://github.com/retro100/dosbox-wii.git
synced 2024-09-29 18:28:35 +02:00
762 lines
16 KiB
C++
762 lines
16 KiB
C++
/*
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* Copyright (C) 2002-2004 The DOSBox Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* $Id: fpu.cpp,v 1.23 2004/10/12 16:19:45 qbix79 Exp $ */
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#include "dosbox.h"
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#if C_FPU
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#include <math.h>
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#include <float.h>
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#include "cross.h"
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#include "mem.h"
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#include "fpu.h"
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#include "cpu.h"
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typedef PhysPt EAPoint;
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#define TOP fpu.top
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#define ST(i) ( (fpu.top+ (i) ) & 7 )
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#define LoadMb(off) mem_readb(off)
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#define LoadMw(off) mem_readw(off)
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#define LoadMd(off) mem_readd(off)
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#define SaveMb(off,val) mem_writeb(off,val)
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#define SaveMw(off,val) mem_writew(off,val)
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#define SaveMd(off,val) mem_writed(off,val)
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#include "fpu_types.h"
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struct {
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FPU_Reg regs[9];
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FPU_Tag tags[9];
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Bitu cw;
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FPU_Round round;
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Bitu ex_mask;
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Bitu sw;
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Bitu top;
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} fpu;
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INLINE void FPU_SetCW(Bitu word) {
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fpu.cw = word;
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fpu.round = (FPU_Round)((word >> 10) & 3);
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// word >>8 &3 is precission
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fpu.ex_mask = word & 0x3f;
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}
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static Bit16u FPU_GetTag(void){
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Bit16u tag=0;
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for(Bitu i=0;i<8;i++)
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tag |= ( (fpu.tags[i]&3) <<(2*i));
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return tag;
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}
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static void FPU_SetTag(Bit16u tag)
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{
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for(Bitu i=0;i<8;i++)
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fpu.tags[i]= static_cast<FPU_Tag>((tag >>(2*i))&3);
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}
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INLINE Bitu FPU_GET_TOP(void){
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return (fpu.sw & 0x3800)>>11;
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}
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INLINE void FPU_SET_TOP(Bitu val){
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fpu.sw &= ~0x3800;
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fpu.sw |= (val&7)<<11;
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return;
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}
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INLINE void FPU_SET_C0(Bitu C){
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fpu.sw &= ~0x0100;
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if(C) fpu.sw |= 0x0100;
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}
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INLINE void FPU_SET_C1(Bitu C){
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fpu.sw &= ~0x0200;
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if(C) fpu.sw |= 0x0200;
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}
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INLINE void FPU_SET_C2(Bitu C){
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fpu.sw &= ~0x0400;
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if(C) fpu.sw |= 0x0400;
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}
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INLINE void FPU_SET_C3(Bitu C){
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fpu.sw &= ~0x4000;
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if(C) fpu.sw |= 0x4000;
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}
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INLINE Bitu FPU_GET_C0(void){
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return (fpu.sw & 0x0100)>>8;
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}
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INLINE Bitu FPU_GET_C1(void){
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return (fpu.sw & 0x0200)>>9;
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}
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INLINE Bitu FPU_GET_C2(void){
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return (fpu.sw & 0x0400)>>10;
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}
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INLINE Bitu FPU_GET_C3(void){
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return (fpu.sw & 0x4000)>>14;
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}
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#include "fpu_instructions.h"
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/* TODO : ESC6normal => esc4normal+pop or a define as well
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*/
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/* WATCHIT : ALWAYS UPDATE REGISTERS BEFORE AND AFTER USING THEM
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STATUS WORD => FPU_SET_TOP(TOP) BEFORE a read
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TOP=FPU_GET_TOP() after a write;
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*/
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static void EATREE(Bitu _rm){
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Bitu group=(_rm >> 3) & 7;
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/* data will allready be put in register 8 by caller */
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switch(group){
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case 0x00: /* FIADD */
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FPU_FADD(TOP, 8);
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break;
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case 0x01: /* FIMUL */
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FPU_FMUL(TOP, 8);
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break;
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case 0x02: /* FICOM */
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FPU_FCOM(TOP,8);
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break;
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case 0x03: /* FICOMP */
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FPU_FCOM(TOP,8);
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FPU_FPOP();
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break;
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case 0x04: /* FISUB */
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FPU_FSUB(TOP,8);
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break;
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case 0x05: /* FISUBR */
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FPU_FSUBR(TOP,8);
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break;
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case 0x06: /* FIDIV */
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FPU_FDIV(TOP, 8);
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break;
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case 0x07: /* FIDIVR */
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FPU_FDIVR(TOP,8);
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break;
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default:
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break;
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}
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}
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void FPU_ESC0_EA(Bitu rm,PhysPt addr) {
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/* REGULAR TREE WITH 32 BITS REALS -> float */
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union {
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float f;
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Bit32u l;
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} blah;
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blah.l = mem_readd(addr);
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fpu.regs[8].d = static_cast<double>(blah.f);
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EATREE(rm);
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}
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void FPU_ESC0_Normal(Bitu rm) {
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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switch (group){
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case 0x00: /* FADD ST,STi */
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FPU_FADD(TOP,ST(sub));
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break;
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case 0x01: /* FMUL ST,STi */
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FPU_FMUL(TOP,ST(sub));
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break;
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case 0x02: /* FCOM STi */
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FPU_FCOM(TOP,ST(sub));
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break;
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case 0x03: /* FCOMP STi */
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FPU_FCOM(TOP,ST(sub));
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FPU_FPOP();
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break;
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case 0x04: /* FSUB ST,STi */
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FPU_FSUB(TOP,ST(sub));
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break;
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case 0x05: /* FSUBR ST,STi */
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FPU_FSUBR(TOP,ST(sub));
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break;
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case 0x06: /* FDIV ST,STi */
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FPU_FDIV(TOP,ST(sub));
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break;
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case 0x07: /* FDIVR ST,STi */
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FPU_FDIVR(TOP,ST(sub));
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break;
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default:
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break;
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}
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}
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void FPU_ESC1_EA(Bitu rm,PhysPt addr) {
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// floats
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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switch(group){
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case 0x00: /* FLD float*/
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{
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union {
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float f;
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Bit32u l;
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} blah;
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blah.l = mem_readd(addr);
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FPU_PUSH(static_cast<double>(blah.f));
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}
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break;
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case 0x01: /* UNKNOWN */
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LOG(LOG_FPU,LOG_WARN)("ESC EA 1:Unhandled group %d subfunction %d",group,sub);
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break;
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case 0x02: /* FST float*/
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{
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union {
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float f;
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Bit32u l;
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} blah;
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//should depend on rounding method
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blah.f = static_cast<float>(fpu.regs[TOP].d);
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mem_writed(addr,blah.l);
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}
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break;
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case 0x03: /* FSTP float*/
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{
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union {
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float f;
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Bit32u l;
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} blah;
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blah.f = static_cast<float>(fpu.regs[TOP].d);
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mem_writed(addr,blah.l);
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}
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FPU_FPOP();
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break;
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case 0x04: /* FLDENV */
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FPU_FLDENV(addr);
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break;
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case 0x05: /* FLDCW */
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{
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Bit16u temp =mem_readw(addr);
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FPU_SetCW(temp);
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}
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break;
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case 0x06: /* FSTENV */
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FPU_FSTENV(addr);
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break;
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case 0x07: /* FNSTCW*/
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mem_writew(addr,fpu.cw);
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break;
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default:
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LOG(LOG_FPU,LOG_WARN)("ESC EA 1:Unhandled group %d subfunction %d",group,sub);
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break;
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}
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}
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void FPU_ESC1_Normal(Bitu rm) {
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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switch (group){
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case 0x00: /* FLD STi */
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FPU_PUSH(fpu.regs[ST(sub)].d);
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break;
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case 0x01: /* FXCH STi */
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FPU_FXCH(TOP,ST(sub));
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break;
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case 0x02: /* FNOP */
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FPU_FNOP();
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break;
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case 0x03: /* FSTP STi */
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FPU_FST(TOP,ST(sub));
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FPU_FPOP();
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break;
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case 0x04:
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switch(sub){
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case 0x00: /* FCHS */
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fpu.regs[TOP].d = -1.0*(fpu.regs[TOP].d);
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break;
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case 0x01: /* FABS */
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fpu.regs[TOP].d = fabs(fpu.regs[TOP].d);
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break;
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case 0x02: /* UNKNOWN */
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case 0x03: /* ILLEGAL */
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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break;
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case 0x04: /* FTST */
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fpu.regs[8].d=0.0;
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FPU_FCOM(TOP,8);
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break;
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case 0x05: /* FXAM */
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FPU_FXAM();
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break;
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case 0x06: /* FTSTP (cyrix)*/
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case 0x07: /* UNKNOWN */
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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break;
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}
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break;
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case 0x05:
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switch(sub){
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case 0x00: /* FLD1 */
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FPU_PUSH(1.0);
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break;
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case 0x01: /* FLDL2T */
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FPU_PUSH(L2T);
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break;
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case 0x02: /* FLDL2E */
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FPU_PUSH(L2E);
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break;
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case 0x03: /* FLDPI */
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FPU_PUSH(PI);
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break;
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case 0x04: /* FLDLG2 */
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FPU_PUSH(LG2);
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break;
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case 0x05: /* FLDLN2 */
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FPU_PUSH(LN2);
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break;
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case 0x06: /* FLDZ*/
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FPU_PUSH_ZERO();
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break;
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case 0x07: /* ILLEGAL */
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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break;
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}
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break;
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case 0x06:
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switch(sub){
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case 0x00: /* F2XM1 */
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FPU_F2XM1();
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break;
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case 0x01: /* FYL2X */
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FPU_FYL2X();
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break;
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case 0x02: /* FPTAN */
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FPU_FPTAN();
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break;
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case 0x03: /* FPATAN */
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FPU_FPATAN();
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break;
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case 0x04: /* FXTRACT */
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FPU_FXTRACT();
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break;
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default:
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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break;
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}
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break;
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case 0x07:
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switch(sub){
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case 0x00: /* FPREM */
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FPU_FPREM();
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break;
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case 0x02: /* FSQRT */
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FPU_FSQRT();
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break;
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case 0x03: /* FSINCOS */
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FPU_FSINCOS();
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break;
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case 0x04: /* FRNDINT */
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{
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//TODO
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Bit64s temp= static_cast<Bit64s>(FROUND(fpu.regs[TOP].d));
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fpu.regs[TOP].d=static_cast<double>(temp);
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}
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//TODO
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break;
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case 0x05: /* FSCALE */
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FPU_FSCALE();
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break;
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case 0x06: /* FSIN */
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FPU_FSIN();
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break;
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case 0x07: /* FCOS */
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FPU_FCOS();
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break;
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case 0x01: /* FYL2XP1 */
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default:
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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break;
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}
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break;
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default:
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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}
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// LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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}
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void FPU_ESC2_EA(Bitu rm,PhysPt addr) {
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/* 32 bits integer operants */
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Bit32s blah = mem_readd(addr);
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fpu.regs[8].d = static_cast<Real64>(blah);
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EATREE(rm);
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}
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void FPU_ESC2_Normal(Bitu rm) {
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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switch(group){
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case 0x05:
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switch(sub){
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case 0x01: /* FUCOMPP Almost the same as FCOMPP */
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FPU_FCOM(TOP,ST(1));
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FPU_FPOP();
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FPU_FPOP();
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break;
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default:
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LOG(LOG_FPU,LOG_WARN)("ESC 2:Unhandled group %d subfunction %d",group,sub);
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break;
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}
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break;
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default:
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LOG(LOG_FPU,LOG_WARN)("ESC 2:Unhandled group %d subfunction %d",group,sub);
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break;
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}
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}
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void FPU_ESC3_EA(Bitu rm,PhysPt addr) {
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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switch(group){
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case 0x00: /* FLD */
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{
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Bit32s blah = mem_readd(addr);
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FPU_PUSH( static_cast<double>(blah));
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}
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break;
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case 0x01: /* FISTTP */
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LOG(LOG_FPU,LOG_WARN)("ESC 3 EA:Unhandled group %d subfunction %d",group,sub);
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break;
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case 0x02: /* FIST */
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mem_writed(addr,static_cast<Bit32s>(FROUND(fpu.regs[TOP].d)));
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break;
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case 0x03: /*FISTP */
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mem_writed(addr,static_cast<Bit32s>(FROUND(fpu.regs[TOP].d)));
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FPU_FPOP();
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break;
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case 0x05: /* FLD 80 Bits Real */
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{
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Real64 val = FPU_FLD80(addr);
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FPU_PUSH(val);
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}
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break;
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case 0x07: /* FSTP 80 Bits Real */
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FPU_ST80(addr,TOP);
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FPU_FPOP();
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break;
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default:
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LOG(LOG_FPU,LOG_WARN)("ESC 3 EA:Unhandled group %d subfunction %d",group,sub);
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}
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}
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void FPU_ESC3_Normal(Bitu rm) {
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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switch (group) {
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case 0x04:
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switch (sub) {
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case 0x00: //FNENI
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case 0x01: //FNDIS
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LOG(LOG_FPU,LOG_ERROR)("8087 only fpu code used esc 3: group 4: subfuntion :%d",sub);
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break;
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case 0x02: //FNCLEX FCLEX
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FPU_FCLEX();
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break;
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case 0x03: //FNINIT FINIT
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FPU_FINIT();
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break;
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case 0x04: //FNSETPM
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case 0x05: //FRSTPM
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// LOG(LOG_FPU,LOG_ERROR)("80267 protected mode (un)set. Nothing done");
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FPU_FNOP();
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break;
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default:
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E_Exit("ESC 3:ILLEGAL OPCODE group %d subfunction %d",group,sub);
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}
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break;
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default:
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LOG(LOG_FPU,LOG_WARN)("ESC 3:Unhandled group %d subfunction %d",group,sub);
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break;
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}
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return;
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}
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void FPU_ESC4_EA(Bitu rm,PhysPt addr) {
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/* REGULAR TREE WITH 64 BITS REALS: double */
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fpu.regs[8].l.lower=mem_readd(addr);
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fpu.regs[8].l.upper=mem_readd(addr+4);
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EATREE(rm);
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}
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void FPU_ESC4_Normal(Bitu rm) {
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//LOOKS LIKE number 6 without popping*/
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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switch(group){
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case 0x00: /*FADDP STi,ST*/
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FPU_FADD(ST(sub),TOP);
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break;
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case 0x01: /* FMULP STi,ST*/
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|
FPU_FMUL(ST(sub),TOP);
|
|
break;
|
|
case 0x02: /* FCOM*/
|
|
FPU_FCOM(TOP,ST(sub));
|
|
break; /* TODO IS THIS ALLRIGHT ????????? (maybe reverse operators) */
|
|
case 0x03: /* FCOMP*/
|
|
FPU_FCOM(TOP,ST(sub));
|
|
FPU_FPOP();
|
|
break;
|
|
case 0x04: /* FSUBR STi,ST*/
|
|
FPU_FSUBR(ST(sub),TOP);
|
|
break;
|
|
case 0x05: /* FSUB STi,ST*/
|
|
FPU_FSUB(ST(sub),TOP);
|
|
break;
|
|
case 0x06: /* FDIVR STi,ST*/
|
|
FPU_FDIVR(ST(sub),TOP);
|
|
break;
|
|
case 0x07: /* FDIV STi,ST*/
|
|
FPU_FDIV(ST(sub),TOP);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
void FPU_ESC5_EA(Bitu rm,PhysPt addr) {
|
|
Bitu group=(rm >> 3) & 7;
|
|
Bitu sub=(rm & 7);
|
|
switch(group){
|
|
case 0x00: /* FLD double real*/
|
|
{
|
|
FPU_Reg blah;
|
|
blah.l.lower=mem_readd(addr);
|
|
blah.l.upper=mem_readd(addr+4);
|
|
FPU_PUSH(blah.d);
|
|
}
|
|
break;
|
|
case 0x01: /* FISTTP longint*/
|
|
LOG(LOG_FPU,LOG_WARN)("ESC 5 EA:Unhandled group %d subfunction %d",group,sub);
|
|
break;
|
|
|
|
case 0x02: /* FIST double real*/
|
|
mem_writed(addr,fpu.regs[TOP].l.lower);
|
|
mem_writed(addr+4,fpu.regs[TOP].l.upper);
|
|
break;
|
|
case 0x03: /*FISTP double real*/
|
|
mem_writed(addr,fpu.regs[TOP].l.lower);
|
|
mem_writed(addr+4,fpu.regs[TOP].l.upper);
|
|
FPU_FPOP();
|
|
break;
|
|
case 0x04: /* FSTOR */
|
|
FPU_FSTOR(addr);
|
|
break;
|
|
case 0x06: /* FSAVE */
|
|
FPU_FSAVE(addr);
|
|
break;
|
|
case 0x07: /*FNSTSW NG DISAGREES ON THIS*/
|
|
FPU_SET_TOP(TOP);
|
|
mem_writew(addr,fpu.sw);
|
|
//seems to break all dos4gw games :)
|
|
break;
|
|
default:
|
|
LOG(LOG_FPU,LOG_WARN)("ESC 5 EA:Unhandled group %d subfunction %d",group,sub);
|
|
}
|
|
}
|
|
|
|
void FPU_ESC5_Normal(Bitu rm) {
|
|
Bitu group=(rm >> 3) & 7;
|
|
Bitu sub=(rm & 7);
|
|
switch(group){
|
|
case 0x00: /* FFREE STi */
|
|
fpu.tags[ST(sub)]=TAG_Empty;
|
|
break;
|
|
case 0x01: /* FXCH STi*/
|
|
FPU_FXCH(TOP,ST(sub));
|
|
break;
|
|
case 0x02: /* FST STi */
|
|
FPU_FST(TOP,ST(sub));
|
|
break;
|
|
case 0x03: /* FSTP STi*/
|
|
FPU_FST(TOP,ST(sub));
|
|
FPU_FPOP();
|
|
break;
|
|
case 0x04: /* FUCOM STi */
|
|
FPU_FUCOM(TOP,ST(sub));
|
|
break;
|
|
case 0x05: /*FUCOMP STi */
|
|
FPU_FUCOM(TOP,ST(sub));
|
|
FPU_FPOP();
|
|
break;
|
|
default:
|
|
LOG(LOG_FPU,LOG_WARN)("ESC 5:Unhandled group %d subfunction %d",group,sub);
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
void FPU_ESC6_EA(Bitu rm,PhysPt addr) {
|
|
/* 16 bit (word integer) operants */
|
|
Bit16s blah = mem_readw(addr);
|
|
fpu.regs[8].d = static_cast<Real64>(blah);
|
|
EATREE(rm);
|
|
}
|
|
|
|
void FPU_ESC6_Normal(Bitu rm) {
|
|
/* all P variants working only on registers */
|
|
/* get top before switch and pop afterwards */
|
|
Bitu group=(rm >> 3) & 7;
|
|
Bitu sub=(rm & 7);
|
|
switch(group){
|
|
case 0x00: /*FADDP STi,ST*/
|
|
FPU_FADD(ST(sub),TOP);
|
|
break;
|
|
case 0x01: /* FMULP STi,ST*/
|
|
FPU_FMUL(ST(sub),TOP);
|
|
break;
|
|
case 0x02: /* FCOMP5*/
|
|
FPU_FCOM(TOP,ST(sub));
|
|
break; /* TODO IS THIS ALLRIGHT ????????? */
|
|
case 0x03: /* weird*/ /*FCOMPP*/
|
|
if(sub != 1){
|
|
LOG(LOG_FPU,LOG_WARN)("ESC 6:Unhandled group %d subfunction %d",group,sub);
|
|
;
|
|
break;
|
|
}
|
|
FPU_FCOM(TOP,ST(1));
|
|
FPU_FPOP(); /* extra pop at the bottom*/
|
|
break;
|
|
case 0x04: /* FSUBRP STi,ST*/
|
|
FPU_FSUBR(ST(sub),TOP);
|
|
break;
|
|
case 0x05: /* FSUBP STi,ST*/
|
|
FPU_FSUB(ST(sub),TOP);
|
|
break;
|
|
case 0x06: /* FDIVRP STi,ST*/
|
|
FPU_FDIVR(ST(sub),TOP);
|
|
break;
|
|
case 0x07: /* FDIVP STi,ST*/
|
|
FPU_FDIV(ST(sub),TOP);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
FPU_FPOP();
|
|
}
|
|
|
|
|
|
void FPU_ESC7_EA(Bitu rm,PhysPt addr) {
|
|
/* ROUNDING*/
|
|
|
|
Bitu group=(rm >> 3) & 7;
|
|
Bitu sub=(rm & 7);
|
|
switch(group){
|
|
case 0x00: /* FILD Bit16s */
|
|
{
|
|
Bit16s blah = mem_readw(addr);
|
|
FPU_PUSH( static_cast<Real64>(blah));
|
|
}
|
|
break;
|
|
case 0x01: /* FISTTP Bit16s */
|
|
LOG(LOG_FPU,LOG_WARN)("ESC 7 EA:Unhandled group %d subfunction %d",group,sub);
|
|
break;
|
|
|
|
case 0x02: /* FIST Bit16s */
|
|
mem_writew(addr,static_cast<Bit16s>(FROUND(fpu.regs[TOP].d)));
|
|
break;
|
|
case 0x03: /* FISTP Bit16s */
|
|
mem_writew(addr,static_cast<Bit16s>(FROUND(fpu.regs[TOP].d)));
|
|
FPU_FPOP();
|
|
break;
|
|
case 0x05: /* FILD Bit64s */
|
|
{
|
|
FPU_Reg blah;
|
|
blah.l.lower = mem_readd(addr);
|
|
blah.l.upper = mem_readd(addr+4);
|
|
FPU_PUSH(static_cast<Real64>(blah.ll));
|
|
}
|
|
break;
|
|
case 0x06: /* FBSTP packed BCD */
|
|
FPU_FBST(addr);
|
|
FPU_FPOP();
|
|
break;
|
|
case 0x07: /* FISTP Bit64s */
|
|
{
|
|
FPU_Reg blah;
|
|
blah.ll = static_cast<Bit64s>(FROUND(fpu.regs[TOP].d));
|
|
mem_writed(addr,blah.l.lower);
|
|
mem_writed(addr+4,blah.l.upper);
|
|
}
|
|
FPU_FPOP();
|
|
break;
|
|
case 0x04: /* FBLD packed BCD */
|
|
{
|
|
Real64 in = FPU_FBLD(addr);
|
|
FPU_PUSH(in);
|
|
}
|
|
break;
|
|
default:
|
|
LOG(LOG_FPU,LOG_WARN)("ESC 7 EA:Unhandled group %d subfunction %d",group,sub);
|
|
break;
|
|
}
|
|
}
|
|
|
|
void FPU_ESC7_Normal(Bitu rm) {
|
|
Bitu group=(rm >> 3) & 7;
|
|
Bitu sub=(rm & 7);
|
|
switch (group){
|
|
case 0x01: /* FXCH STi*/
|
|
FPU_FXCH(TOP,ST(sub));
|
|
break;
|
|
case 0x02: /* FSTP STi*/
|
|
case 0x03: /* FSTP STi*/
|
|
FPU_FST(TOP,ST(sub));
|
|
FPU_FPOP();
|
|
break;
|
|
case 0x04:
|
|
switch(sub){
|
|
case 0x00: /* FNSTSW AX*/
|
|
FPU_SET_TOP(TOP);
|
|
reg_ax = fpu.sw;
|
|
break;
|
|
default:
|
|
LOG(LOG_FPU,LOG_WARN)("ESC 7:Unhandled group %d subfunction %d",group,sub);
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
LOG(LOG_FPU,LOG_WARN)("ESC 7:Unhandled group %d subfunction %d",group,sub);
|
|
break;
|
|
}
|
|
|
|
}
|
|
|
|
|
|
void FPU_Init(Section*) {
|
|
FPU_FINIT();
|
|
}
|
|
|
|
#endif
|