mirror of
https://github.com/retro100/dosbox-wii.git
synced 2024-11-19 08:39:15 +01:00
567 lines
20 KiB
C++
567 lines
20 KiB
C++
/*
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* Copyright (C) 2002-2009 The DOSBox Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* $Id: vga_s3.cpp,v 1.18 2009/03/15 11:28:35 c2woody Exp $ */
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#include "dosbox.h"
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#include "inout.h"
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#include "vga.h"
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#include "mem.h"
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void SVGA_S3_WriteCRTC(Bitu reg,Bitu val,Bitu iolen) {
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switch (reg) {
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case 0x31: /* CR31 Memory Configuration */
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//TODO Base address
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vga.s3.reg_31 = val;
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vga.config.compatible_chain4 = !(val&0x08);
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if (vga.config.compatible_chain4) vga.vmemwrap = 256*1024;
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else vga.vmemwrap = vga.vmemsize;
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vga.config.display_start = (vga.config.display_start&~0x30000)|((val&0x30)<<12);
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VGA_DetermineMode();
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VGA_SetupHandlers();
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break;
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/*
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0 Enable Base Address Offset (CPUA BASE). Enables bank operation if
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set, disables if clear.
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1 Two Page Screen Image. If set enables 2048 pixel wide screen setup
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2 VGA 16bit Memory Bus Width. Set for 16bit, clear for 8bit
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3 Use Enhanced Mode Memory Mapping (ENH MAP). Set to enable access to
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video memory above 256k.
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4-5 Bit 16-17 of the Display Start Address. For the 801/5,928 see index
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51h, for the 864/964 see index 69h.
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6 High Speed Text Display Font Fetch Mode. If set enables Page Mode
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for Alpha Mode Font Access.
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7 (not 864/964) Extended BIOS ROM Space Mapped out. If clear the area
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C6800h-C7FFFh is mapped out, if set it is accessible.
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*/
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case 0x35: /* CR35 CRT Register Lock */
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if (vga.s3.reg_lock1 != 0x48) return; //Needed for uvconfig detection
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vga.s3.reg_35=val & 0xf0;
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if ((vga.svga.bank_read & 0xf) ^ (val & 0xf)) {
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vga.svga.bank_read&=0xf0;
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vga.svga.bank_read|=val & 0xf;
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vga.svga.bank_write = vga.svga.bank_read;
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VGA_SetupHandlers();
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}
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break;
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/*
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0-3 CPU Base Address. 64k bank number. For the 801/5 and 928 see 3d4h
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index 51h bits 2-3. For the 864/964 see index 6Ah.
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4 Lock Vertical Timing Registers (LOCK VTMG). Locks 3d4h index 6, 7
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(bits 0,2,3,5,7), 9 bit 5, 10h, 11h bits 0-3, 15h, 16h if set
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5 Lock Horizontal Timing Registers (LOCK HTMG). Locks 3d4h index
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0,1,2,3,4,5,17h bit 2 if set
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6 (911/924) Lock VSync Polarity.
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7 (911/924) Lock HSync Polarity.
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*/
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case 0x38: /* CR38 Register Lock 1 */
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vga.s3.reg_lock1=val;
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break;
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case 0x39: /* CR39 Register Lock 2 */
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vga.s3.reg_lock2=val;
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break;
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case 0x3a:
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vga.s3.reg_3a = val;
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break;
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case 0x40: /* CR40 System Config */
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vga.s3.reg_40 = val;
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break;
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case 0x41: /* CR41 BIOS flags */
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vga.s3.reg_41 = val;
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break;
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case 0x43: /* CR43 Extended Mode */
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vga.s3.reg_43=val & ~0x4;
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if (((val & 0x4) ^ (vga.config.scan_len >> 6)) & 0x4) {
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vga.config.scan_len&=0x2ff;
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vga.config.scan_len|=(val & 0x4) << 6;
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VGA_CheckScanLength();
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}
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break;
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/*
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2 Logical Screen Width bit 8. Bit 8 of the Display Offset Register/
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(3d4h index 13h). (801/5,928) Only active if 3d4h index 51h bits 4-5
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are 0
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*/
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case 0x45: /* Hardware cursor mode */
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vga.s3.hgc.curmode = val;
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// Activate hardware cursor code if needed
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VGA_ActivateHardwareCursor();
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break;
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case 0x46:
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vga.s3.hgc.originx = (vga.s3.hgc.originx & 0x00ff) | (val << 8);
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break;
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case 0x47: /* HGC orgX */
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vga.s3.hgc.originx = (vga.s3.hgc.originx & 0xff00) | val;
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break;
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case 0x48:
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vga.s3.hgc.originy = (vga.s3.hgc.originy & 0x00ff) | (val << 8);
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break;
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case 0x49: /* HGC orgY */
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vga.s3.hgc.originy = (vga.s3.hgc.originy & 0xff00) | val;
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break;
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case 0x4A: /* HGC foreground stack */
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if (vga.s3.hgc.fstackpos > 2) vga.s3.hgc.fstackpos = 0;
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vga.s3.hgc.forestack[vga.s3.hgc.fstackpos] = val;
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vga.s3.hgc.fstackpos++;
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break;
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case 0x4B: /* HGC background stack */
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if (vga.s3.hgc.bstackpos > 2) vga.s3.hgc.bstackpos = 0;
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vga.s3.hgc.backstack[vga.s3.hgc.bstackpos] = val;
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vga.s3.hgc.bstackpos++;
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break;
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case 0x4c: /* HGC start address high byte*/
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vga.s3.hgc.startaddr &=0xff;
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vga.s3.hgc.startaddr |= ((val & 0xf) << 8);
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if ((((Bitu)vga.s3.hgc.startaddr)<<10)+((64*64*2)/8) > vga.vmemsize) {
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vga.s3.hgc.startaddr &= 0xff; // put it back to some sane area;
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// if read back of this address is ever implemented this needs to change
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LOG(LOG_VGAMISC,LOG_NORMAL)("VGA:S3:CRTC: HGC pattern address beyond video memory" );
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}
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break;
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case 0x4d: /* HGC start address low byte*/
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vga.s3.hgc.startaddr &=0xff00;
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vga.s3.hgc.startaddr |= (val & 0xff);
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break;
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case 0x4e: /* HGC pattern start X */
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vga.s3.hgc.posx = val & 0x3f; // bits 0-5
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break;
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case 0x4f: /* HGC pattern start Y */
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vga.s3.hgc.posy = val & 0x3f; // bits 0-5
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break;
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case 0x50: // Extended System Control 1
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vga.s3.reg_50 = val;
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switch (val & S3_XGA_CMASK) {
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case S3_XGA_32BPP: vga.s3.xga_color_mode = M_LIN32; break;
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case S3_XGA_16BPP: vga.s3.xga_color_mode = M_LIN16; break;
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case S3_XGA_8BPP: vga.s3.xga_color_mode = M_LIN8; break;
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}
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switch (val & S3_XGA_WMASK) {
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case S3_XGA_1024: vga.s3.xga_screen_width = 1024; break;
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case S3_XGA_1152: vga.s3.xga_screen_width = 1152; break;
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case S3_XGA_640: vga.s3.xga_screen_width = 640; break;
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case S3_XGA_800: vga.s3.xga_screen_width = 800; break;
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case S3_XGA_1280: vga.s3.xga_screen_width = 1280; break;
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default: vga.s3.xga_screen_width = 1024; break;
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}
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break;
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case 0x51: /* Extended System Control 2 */
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vga.s3.reg_51=val & 0xc0; //Only store bits 6,7
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vga.config.display_start&=0xF3FFFF;
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vga.config.display_start|=(val & 3) << 18;
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if ((vga.svga.bank_read&0x30) ^ ((val&0xc)<<2)) {
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vga.svga.bank_read&=0xcf;
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vga.svga.bank_read|=(val&0xc)<<2;
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vga.svga.bank_write = vga.svga.bank_read;
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VGA_SetupHandlers();
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}
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if (((val & 0x30) ^ (vga.config.scan_len >> 4)) & 0x30) {
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vga.config.scan_len&=0xff;
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vga.config.scan_len|=(val & 0x30) << 4;
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VGA_CheckScanLength();
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}
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break;
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/*
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0 (80x) Display Start Address bit 18
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0-1 (928 +) Display Start Address bit 18-19
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Bits 16-17 are in index 31h bits 4-5, Bits 0-15 are in 3d4h index
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0Ch,0Dh. For the 864/964 see 3d4h index 69h
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2 (80x) CPU BASE. CPU Base Address Bit 18.
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2-3 (928 +) Old CPU Base Address Bits 19-18.
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64K Bank register bits 4-5. Bits 0-3 are in 3d4h index 35h.
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For the 864/964 see 3d4h index 6Ah
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4-5 Logical Screen Width Bit [8-9]. Bits 8-9 of the CRTC Offset register
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(3d4h index 13h). If this field is 0, 3d4h index 43h bit 2 is active
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6 (928,964) DIS SPXF. Disable Split Transfers if set. Spilt Transfers
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allows transferring one half of the VRAM shift register data while
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the other half is being output. For the 964 Split Transfers
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must be enabled in enhanced modes (4AE8h bit 0 set). Guess: They
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probably can't time the VRAM load cycle closely enough while the
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graphics engine is running.
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7 (not 864/964) Enable EPROM Write. If set enables flash memory write
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control to the BIOS ROM address
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*/
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case 0x52: // Extended System Control 1
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vga.s3.reg_52 = val;
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break;
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case 0x53:
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// Map or unmap MMIO
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// bit 4 = MMIO at A0000
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// bit 3 = MMIO at LFB + 16M (should be fine if its always enabled for now)
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if(vga.s3.ext_mem_ctrl!=val) {
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vga.s3.ext_mem_ctrl = val;
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VGA_SetupHandlers();
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}
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break;
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case 0x55: /* Extended Video DAC Control */
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vga.s3.reg_55=val;
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break;
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/*
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0-1 DAC Register Select Bits. Passed to the RS2 and RS3 pins on the
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RAMDAC, allowing access to all 8 or 16 registers on advanced RAMDACs.
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If this field is 0, 3d4h index 43h bit 1 is active.
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2 Enable General Input Port Read. If set DAC reads are disabled and the
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STRD strobe for reading the General Input Port is enabled for reading
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while DACRD is active, if clear DAC reads are enabled.
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3 (928) Enable External SID Operation if set. If set video data is
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passed directly from the VRAMs to the DAC rather than through the
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VGA chip
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4 Hardware Cursor MS/X11 Mode. If set the Hardware Cursor is in X11
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mode, if clear in MS-Windows mode
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5 (80x,928) Hardware Cursor External Operation Mode. If set the two
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bits of cursor data ,is output on the HC[0-1] pins for the video DAC
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The SENS pin becomes HC1 and the MID2 pin becomes HC0.
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6 ??
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7 (80x,928) Disable PA Output. If set PA[0-7] and VCLK are tristated.
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(864/964) TOFF VCLK. Tri-State Off VCLK Output. VCLK output tri
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-stated if set
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*/
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case 0x58: /* Linear Address Window Control */
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vga.s3.reg_58=val;
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break;
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/*
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0-1 Linear Address Window Size. Must be less than or equal to video
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memory size. 0: 64K, 1: 1MB, 2: 2MB, 3: 4MB (928)/8Mb (864/964)
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2 (not 864/964) Enable Read Ahead Cache if set
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3 (80x,928) ISA Latch Address. If set latches address during every ISA
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cycle, unlatches during every ISA cycle if clear.
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(864/964) LAT DEL. Address Latch Delay Control (VL-Bus only). If set
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address latching occours in the T1 cycle, if clear in the T2 cycle
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(I.e. one clock cycle delayed).
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4 ENB LA. Enable Linear Addressing if set.
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5 (not 864/964) Limit Entry Depth for Write-Post. If set limits Write
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-Post Entry Depth to avoid ISA bus timeout due to wait cycle limit.
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6 (928,964) Serial Access Mode (SAM) 256 Words Control. If set SAM
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control is 256 words, if clear 512 words.
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7 (928) RAS 6-MCLK. If set the random read/write cycle time is 6MCLKs,
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if clear 7MCLKs
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*/
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case 0x59: /* Linear Address Window Position High */
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if ((vga.s3.la_window&0xff00) ^ (val << 8)) {
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vga.s3.la_window=(vga.s3.la_window&0x00ff) | (val << 8);
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VGA_StartUpdateLFB();
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}
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break;
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case 0x5a: /* Linear Address Window Position Low */
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if ((vga.s3.la_window&0x00ff) ^ val) {
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vga.s3.la_window=(vga.s3.la_window&0xff00) | val;
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VGA_StartUpdateLFB();
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}
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break;
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case 0x5D: /* Extended Horizontal Overflow */
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if ((val ^ vga.s3.ex_hor_overflow) & 3) {
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vga.s3.ex_hor_overflow=val;
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VGA_StartResize();
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} else vga.s3.ex_hor_overflow=val;
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break;
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/*
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0 Horizontal Total bit 8. Bit 8 of the Horizontal Total register (3d4h
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index 0)
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1 Horizontal Display End bit 8. Bit 8 of the Horizontal Display End
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register (3d4h index 1)
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2 Start Horizontal Blank bit 8. Bit 8 of the Horizontal Start Blanking
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register (3d4h index 2).
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3 (864,964) EHB+64. End Horizontal Blank +64. If set the /BLANK pulse
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is extended by 64 DCLKs. Note: Is this bit 6 of 3d4h index 3 or
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does it really extend by 64 ?
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4 Start Horizontal Sync Position bit 8. Bit 8 of the Horizontal Start
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Retrace register (3d4h index 4).
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5 (864,964) EHS+32. End Horizontal Sync +32. If set the HSYNC pulse
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is extended by 32 DCLKs. Note: Is this bit 5 of 3d4h index 5 or
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does it really extend by 32 ?
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6 (928,964) Data Transfer Position bit 8. Bit 8 of the Data Transfer
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Position register (3d4h index 3Bh)
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7 (928,964) Bus-Grant Terminate Position bit 8. Bit 8 of the Bus Grant
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Termination register (3d4h index 5Fh).
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*/
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case 0x5e: /* Extended Vertical Overflow */
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vga.config.line_compare=(vga.config.line_compare & 0x3ff) | (val & 0x40) << 4;
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if ((val ^ vga.s3.ex_ver_overflow) & 0x3) {
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vga.s3.ex_ver_overflow=val;
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VGA_StartResize();
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} else vga.s3.ex_ver_overflow=val;
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break;
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/*
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0 Vertical Total bit 10. Bit 10 of the Vertical Total register (3d4h
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index 6). Bits 8 and 9 are in 3d4h index 7 bit 0 and 5.
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1 Vertical Display End bit 10. Bit 10 of the Vertical Display End
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register (3d4h index 12h). Bits 8 and 9 are in 3d4h index 7 bit 1
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and 6
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2 Start Vertical Blank bit 10. Bit 10 of the Vertical Start Blanking
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register (3d4h index 15h). Bit 8 is in 3d4h index 7 bit 3 and bit 9
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in 3d4h index 9 bit 5
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4 Vertical Retrace Start bit 10. Bit 10 of the Vertical Start Retrace
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register (3d4h index 10h). Bits 8 and 9 are in 3d4h index 7 bit 2
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and 7.
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6 Line Compare Position bit 10. Bit 10 of the Line Compare register
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(3d4h index 18h). Bit 8 is in 3d4h index 7 bit 4 and bit 9 in 3d4h
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index 9 bit 6.
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*/
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case 0x67: /* Extended Miscellaneous Control 2 */
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/*
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0 VCLK PHS. VCLK Phase With Respect to DCLK. If clear VLKC is inverted
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DCLK, if set VCLK = DCLK.
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2-3 (Trio64V+) streams mode
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00 disable Streams Processor
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01 overlay secondary stream on VGA-mode background
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10 reserved
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11 full Streams Processor operation
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4-7 Pixel format.
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0 Mode 0: 8bit (1 pixel/VCLK)
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1 Mode 8: 8bit (2 pixels/VCLK)
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3 Mode 9: 15bit (1 pixel/VCLK)
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5 Mode 10: 16bit (1 pixel/VCLK)
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7 Mode 11: 24/32bit (2 VCLKs/pixel)
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13 (732/764) 32bit (1 pixel/VCLK)
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*/
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vga.s3.misc_control_2=val;
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VGA_DetermineMode();
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break;
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case 0x69: /* Extended System Control 3 */
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if (((vga.config.display_start & 0x1f0000)>>16) ^ (val & 0x1f)) {
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vga.config.display_start&=0xffff;
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vga.config.display_start|=(val & 0x1f) << 16;
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}
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break;
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case 0x6a: /* Extended System Control 4 */
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vga.svga.bank_read=val & 0x7f;
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vga.svga.bank_write = vga.svga.bank_read;
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VGA_SetupHandlers();
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break;
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case 0x6b: // BIOS scratchpad: LFB adress
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vga.s3.reg_6b=(Bit8u)val;
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break;
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default:
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LOG(LOG_VGAMISC,LOG_NORMAL)("VGA:S3:CRTC:Write to illegal index %2X", reg );
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break;
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}
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}
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Bitu SVGA_S3_ReadCRTC( Bitu reg, Bitu iolen) {
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switch (reg) {
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case 0x24: /* attribute controller index (read only) */
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case 0x26:
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return (vga.attr.enabled?0x20:0x00) | (vga.attr.index&0x1f);
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case 0x2d: /* Extended Chip ID (high byte of PCI device ID) */
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return 0x88;
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case 0x2e: /* New Chip ID (low byte of PCI device ID) */
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return 0x11; // Trio64
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case 0x2f: /* Revision */
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return 0x00; // Trio64 (exact value?)
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// return 0x44; // Trio64 V+
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case 0x30: /* CR30 Chip ID/REV register */
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return 0xe1; // Trio+ dual byte
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case 0x31: /* CR31 Memory Configuration */
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//TODO mix in bits from baseaddress;
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return vga.s3.reg_31;
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case 0x35: /* CR35 CRT Register Lock */
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return vga.s3.reg_35|(vga.svga.bank_read & 0xf);
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case 0x36: /* CR36 Reset State Read 1 */
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return vga.s3.reg_36;
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case 0x37: /* Reset state read 2 */
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return 0x2b;
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case 0x38: /* CR38 Register Lock 1 */
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return vga.s3.reg_lock1;
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case 0x39: /* CR39 Register Lock 2 */
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return vga.s3.reg_lock2;
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case 0x3a:
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return vga.s3.reg_3a;
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case 0x40: /* CR40 system config */
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return vga.s3.reg_40;
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case 0x41: /* CR40 system config */
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return vga.s3.reg_41;
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case 0x42: // not interlaced
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return 0x0d;
|
|
case 0x43: /* CR43 Extended Mode */
|
|
return vga.s3.reg_43|((vga.config.scan_len>>6)&0x4);
|
|
case 0x45: /* Hardware cursor mode */
|
|
vga.s3.hgc.bstackpos = 0;
|
|
vga.s3.hgc.fstackpos = 0;
|
|
return vga.s3.hgc.curmode|0xa0;
|
|
case 0x46:
|
|
return vga.s3.hgc.originx>>8;
|
|
case 0x47: /* HGC orgX */
|
|
return vga.s3.hgc.originx&0xff;
|
|
case 0x48:
|
|
return vga.s3.hgc.originy>>8;
|
|
case 0x49: /* HGC orgY */
|
|
return vga.s3.hgc.originy&0xff;
|
|
case 0x4A: /* HGC foreground stack */
|
|
return vga.s3.hgc.forestack[vga.s3.hgc.fstackpos];
|
|
case 0x4B: /* HGC background stack */
|
|
return vga.s3.hgc.backstack[vga.s3.hgc.bstackpos];
|
|
case 0x50: // CR50 Extended System Control 1
|
|
return vga.s3.reg_50;
|
|
case 0x51: /* Extended System Control 2 */
|
|
return ((vga.config.display_start >> 16) & 3 ) |
|
|
((vga.svga.bank_read & 0x30) >> 2) |
|
|
((vga.config.scan_len & 0x300) >> 4) |
|
|
vga.s3.reg_51;
|
|
case 0x52: // CR52 Extended BIOS flags 1
|
|
return vga.s3.reg_52;
|
|
case 0x53:
|
|
return vga.s3.ext_mem_ctrl;
|
|
case 0x55: /* Extended Video DAC Control */
|
|
return vga.s3.reg_55;
|
|
case 0x58: /* Linear Address Window Control */
|
|
return vga.s3.reg_58;
|
|
case 0x59: /* Linear Address Window Position High */
|
|
return (vga.s3.la_window >> 8);
|
|
case 0x5a: /* Linear Address Window Position Low */
|
|
return (vga.s3.la_window & 0xff);
|
|
case 0x5D: /* Extended Horizontal Overflow */
|
|
return vga.s3.ex_hor_overflow;
|
|
case 0x5e: /* Extended Vertical Overflow */
|
|
return vga.s3.ex_ver_overflow;
|
|
case 0x67: /* Extended Miscellaneous Control 2 */
|
|
return vga.s3.misc_control_2;
|
|
case 0x69: /* Extended System Control 3 */
|
|
return (Bit8u)((vga.config.display_start & 0x1f0000)>>16);
|
|
case 0x6a: /* Extended System Control 4 */
|
|
return (Bit8u)(vga.svga.bank_read & 0x7f);
|
|
case 0x6b: // BIOS scatchpad: LFB address
|
|
return vga.s3.reg_6b;
|
|
default:
|
|
return 0x00;
|
|
}
|
|
}
|
|
|
|
void SVGA_S3_WriteSEQ(Bitu reg,Bitu val,Bitu iolen) {
|
|
if (reg>0x8 && vga.s3.pll.lock!=0x6) return;
|
|
switch (reg) {
|
|
case 0x08:
|
|
vga.s3.pll.lock=val;
|
|
break;
|
|
case 0x10: /* Memory PLL Data Low */
|
|
vga.s3.mclk.n=val & 0x1f;
|
|
vga.s3.mclk.r=val >> 5;
|
|
break;
|
|
case 0x11: /* Memory PLL Data High */
|
|
vga.s3.mclk.m=val & 0x7f;
|
|
break;
|
|
case 0x12: /* Video PLL Data Low */
|
|
vga.s3.clk[3].n=val & 0x1f;
|
|
vga.s3.clk[3].r=val >> 5;
|
|
break;
|
|
case 0x13: /* Video PLL Data High */
|
|
vga.s3.clk[3].m=val & 0x7f;
|
|
break;
|
|
case 0x15:
|
|
vga.s3.pll.cmd=val;
|
|
VGA_StartResize();
|
|
break;
|
|
default:
|
|
LOG(LOG_VGAMISC,LOG_NORMAL)("VGA:S3:SEQ:Write to illegal index %2X", reg );
|
|
break;
|
|
}
|
|
}
|
|
|
|
Bitu SVGA_S3_ReadSEQ(Bitu reg,Bitu iolen) {
|
|
/* S3 specific group */
|
|
if (reg>0x8 && vga.s3.pll.lock!=0x6) {
|
|
if (reg<0x1b) return 0;
|
|
else return reg;
|
|
}
|
|
switch (reg) {
|
|
case 0x08: /* PLL Unlock */
|
|
return vga.s3.pll.lock;
|
|
case 0x10: /* Memory PLL Data Low */
|
|
return vga.s3.mclk.n || (vga.s3.mclk.r << 5);
|
|
case 0x11: /* Memory PLL Data High */
|
|
return vga.s3.mclk.m;
|
|
case 0x12: /* Video PLL Data Low */
|
|
return vga.s3.clk[3].n || (vga.s3.clk[3].r << 5);
|
|
case 0x13: /* Video Data High */
|
|
return vga.s3.clk[3].m;
|
|
case 0x15:
|
|
return vga.s3.pll.cmd;
|
|
default:
|
|
LOG(LOG_VGAMISC,LOG_NORMAL)("VGA:S3:SEQ:Read from illegal index %2X", reg);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
Bitu SVGA_S3_GetClock(void) {
|
|
Bitu clock = (vga.misc_output >> 2) & 3;
|
|
if (clock == 0)
|
|
clock = 25175000;
|
|
else if (clock == 1)
|
|
clock = 28322000;
|
|
else
|
|
clock=1000*S3_CLOCK(vga.s3.clk[clock].m,vga.s3.clk[clock].n,vga.s3.clk[clock].r);
|
|
/* Check for dual transfer, master clock/2 */
|
|
if (vga.s3.pll.cmd & 0x10) clock/=2;
|
|
return clock;
|
|
}
|
|
|
|
bool SVGA_S3_HWCursorActive(void) {
|
|
return (vga.s3.hgc.curmode & 0x1) != 0;
|
|
}
|
|
|
|
bool SVGA_S3_AcceptsMode(Bitu mode) {
|
|
return VideoModeMemSize(mode) < vga.vmemsize;
|
|
}
|
|
|
|
void SVGA_Setup_S3Trio(void) {
|
|
svga.write_p3d5 = &SVGA_S3_WriteCRTC;
|
|
svga.read_p3d5 = &SVGA_S3_ReadCRTC;
|
|
svga.write_p3c5 = &SVGA_S3_WriteSEQ;
|
|
svga.read_p3c5 = &SVGA_S3_ReadSEQ;
|
|
svga.write_p3c0 = 0; /* no S3-specific functionality */
|
|
svga.read_p3c1 = 0; /* no S3-specific functionality */
|
|
|
|
svga.set_video_mode = 0; /* implemented in core */
|
|
svga.determine_mode = 0; /* implemented in core */
|
|
svga.set_clock = 0; /* implemented in core */
|
|
svga.get_clock = &SVGA_S3_GetClock;
|
|
svga.hardware_cursor_active = &SVGA_S3_HWCursorActive;
|
|
svga.accepts_mode = &SVGA_S3_AcceptsMode;
|
|
|
|
if (vga.vmemsize == 0)
|
|
vga.vmemsize = 2*1024*1024; // the most common S3 configuration
|
|
|
|
// Set CRTC 36 to specify amount of VRAM and PCI
|
|
if (vga.vmemsize < 1024*1024) {
|
|
vga.vmemsize = 512*1024;
|
|
vga.s3.reg_36 = 0xfa; // less than 1mb fast page mode
|
|
} else if (vga.vmemsize < 2048*1024) {
|
|
vga.vmemsize = 1024*1024;
|
|
vga.s3.reg_36 = 0xda; // 1mb fast page mode
|
|
} else if (vga.vmemsize < 3072*1024) {
|
|
vga.vmemsize = 2048*1024;
|
|
vga.s3.reg_36 = 0x9a; // 2mb fast page mode
|
|
} else if (vga.vmemsize < 4096*1024) {
|
|
vga.vmemsize = 3072*1024;
|
|
vga.s3.reg_36 = 0x5a; // 3mb fast page mode
|
|
} else { // Trio64 supported only up to 4M
|
|
vga.vmemsize = 4096*1024;
|
|
vga.s3.reg_36 = 0x1a; // 4mb fast page mode
|
|
}
|
|
|
|
// S3 ROM signature
|
|
PhysPt rom_base=PhysMake(0xc000,0);
|
|
phys_writeb(rom_base+0x003f,'S');
|
|
phys_writeb(rom_base+0x0040,'3');
|
|
phys_writeb(rom_base+0x0041,' ');
|
|
phys_writeb(rom_base+0x0042,'8');
|
|
phys_writeb(rom_base+0x0043,'6');
|
|
phys_writeb(rom_base+0x0044,'C');
|
|
phys_writeb(rom_base+0x0045,'7');
|
|
phys_writeb(rom_base+0x0046,'6');
|
|
phys_writeb(rom_base+0x0047,'4');
|
|
}
|