mirror of
https://github.com/retro100/dosbox-wii.git
synced 2024-09-30 02:38:35 +02:00
150 lines
3.8 KiB
C
150 lines
3.8 KiB
C
/*
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* Copyright (C) 2002 The DOSBox Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Library General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#if !defined __REGS_H
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#define __REGS_H
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#include <mem.h>
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struct Flag_Info {
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union {
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Bit8u b;
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Bit16u w;
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Bit32u d;
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} var1,var2,result;
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Bitu type;
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Bitu prev_type;
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bool cf,sf,pf,af,zf,of,df,tf,intf;
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bool nt;
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Bit8u io;
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bool oldcf;
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};
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struct Segment {
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Bit16u val;
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PhysPt phys; /* The phyiscal address start in emulated machine */
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};
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enum SegNames { cs=0,ds,es,fs,gs,ss};
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union GenReg32 {
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Bit32u dword[1];
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Bit16u word[2];
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Bit8u byte[4];
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};
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#ifdef WORDS_BIGENDIAN
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#define DW_INDEX 0
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#define W_INDEX 1
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#define BH_INDEX 2
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#define BL_INDEX 3
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#else
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#define DW_INDEX 0
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#define W_INDEX 0
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#define BH_INDEX 1
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#define BL_INDEX 0
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#endif
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struct CPU_Regs {
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GenReg32 regs[8],ip;
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};
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extern Segment Segs[6];
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extern Flag_Info flags;
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extern CPU_Regs cpu_regs;
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//#define SegPhys(index) Segs[index].phys
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//#define SegValue(index) Segs[index].val
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INLINE PhysPt SegPhys(SegNames index) {
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return Segs[index].phys;
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}
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INLINE Bit16u SegValue(SegNames index) {
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return Segs[index].val;
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}
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INLINE RealPt RealMakeSeg(SegNames index,Bit16u off) {
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return RealMake(SegValue(index),off);
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}
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INLINE void SegSet16(Bitu index,Bit16u val) {
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Segs[index].val=val;
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Segs[index].phys=val << 4;
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}
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enum REG_NUM {
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REG_NUM_AX, REG_NUM_CX, REG_NUM_DX, REG_NUM_BX,
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REG_NUM_SP, REG_NUM_BP, REG_NUM_SI, REG_NUM_DI
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};
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//macros to convert a 3-bit register index to the correct register
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#define reg_8l(reg) (cpu_regs.regs[(reg)].byte[BL_INDEX])
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#define reg_8h(reg) (cpu_regs.regs[(reg)].byte[BH_INDEX])
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#define reg_8(reg) ((reg) & 4 ? reg_8h((reg) & 3) : reg_8l((reg) & 3))
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#define reg_16(reg) (cpu_regs.regs[(reg)].word[W_INDEX])
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#define reg_32(reg) (cpu_regs.regs[(reg)].dword[DW_INDEX])
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#define reg_al cpu_regs.regs[REG_NUM_AX].byte[BL_INDEX]
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#define reg_ah cpu_regs.regs[REG_NUM_AX].byte[BH_INDEX]
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#define reg_ax cpu_regs.regs[REG_NUM_AX].word[W_INDEX]
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#define reg_eax cpu_regs.regs[REG_NUM_AX].dword[DW_INDEX]
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#define reg_bl cpu_regs.regs[REG_NUM_BX].byte[BL_INDEX]
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#define reg_bh cpu_regs.regs[REG_NUM_BX].byte[BH_INDEX]
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#define reg_bx cpu_regs.regs[REG_NUM_BX].word[W_INDEX]
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#define reg_ebx cpu_regs.regs[REG_NUM_BX].dword[DW_INDEX]
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#define reg_cl cpu_regs.regs[REG_NUM_CX].byte[BL_INDEX]
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#define reg_ch cpu_regs.regs[REG_NUM_CX].byte[BH_INDEX]
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#define reg_cx cpu_regs.regs[REG_NUM_CX].word[W_INDEX]
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#define reg_ecx cpu_regs.regs[REG_NUM_CX].dword[DW_INDEX]
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#define reg_dl cpu_regs.regs[REG_NUM_DX].byte[BL_INDEX]
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#define reg_dh cpu_regs.regs[REG_NUM_DX].byte[BH_INDEX]
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#define reg_dx cpu_regs.regs[REG_NUM_DX].word[W_INDEX]
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#define reg_edx cpu_regs.regs[REG_NUM_DX].dword[DW_INDEX]
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#define reg_si cpu_regs.regs[REG_NUM_SI].word[W_INDEX]
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#define reg_esi cpu_regs.regs[REG_NUM_SI].dword[DW_INDEX]
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#define reg_di cpu_regs.regs[REG_NUM_DI].word[W_INDEX]
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#define reg_edi cpu_regs.regs[REG_NUM_DI].dword[DW_INDEX]
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#define reg_sp cpu_regs.regs[REG_NUM_SP].word[W_INDEX]
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#define reg_esp cpu_regs.regs[REG_NUM_SP].dword[DW_INDEX]
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#define reg_bp cpu_regs.regs[REG_NUM_BP].word[W_INDEX]
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#define reg_ebp cpu_regs.regs[REG_NUM_BP].dword[DW_INDEX]
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#define reg_ip cpu_regs.ip.word[W_INDEX]
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#define reg_eip cpu_regs.ip.dword[DW_INDEX]
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#endif
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