mirror of
https://github.com/dborth/fceugx.git
synced 2025-01-09 23:29:25 +01:00
212 lines
5.4 KiB
C++
212 lines
5.4 KiB
C++
//Thanks to VirtualNES developer for reverse engineering this mapper
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//first screen add 32 to chr
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//second screen at 0x42000
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#include "mapinc.h"
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static uint8 reg[9], VRAM_switch;
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static int32 irq_enable, irq_counter, irq_latch, irq_clock;
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static void Mapper253_IRQHook(int cycles)
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{
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if( irq_enable & 0x02 )
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{
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if( (irq_clock+=cycles) >= 0x72 )
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{
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irq_clock -= 0x72;
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if( irq_counter == 0xFF )
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{
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irq_counter = irq_latch;
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irq_enable = (irq_enable & 0x01) * 3;
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X6502_IRQBegin(FCEU_IQEXT);
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} else
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{
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irq_counter++;
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}
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}
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}
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}
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static void SetBank_PPUSUB(int bank, int page)
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{
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if(page == 0x88)
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{
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VRAM_switch = 0;
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return;
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}
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else if(page == 0xC8)
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{
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VRAM_switch = 1;
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return;
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}
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if ((page == 4) || (page == 5))
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{
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printf("Page in 4 5: %d\n", page);
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if(VRAM_switch == 0)
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setchr1( bank << 10, page ); //CHR-ROM
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else
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setchr1( bank << 10, page ); //CHR-RAM
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}
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else
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{
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printf("Page: %d\n", page);
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setchr1(bank << 10, page);
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}
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}
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static DECLFW(Mapper253_Write)
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{
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printf("Address: 0x%X V: 0x%X\n", A, V);
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if (A == 0x8010) //8kb select at 0x8000
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{
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setprg8(0x8000, V);
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return;
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}
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if (A == 0xA010) //8kb select at 0xA000
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{
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setprg8(0xA000, V);
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return;
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}
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if (A == 0x9400) //Mirroring
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{
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V &= 0x03;
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switch (V)
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{
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case 0:
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setmirror(MI_V);
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break;
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case 1:
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setmirror(MI_H);
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break;
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case 2:
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setmirror(MI_0);
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break;
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case 3:
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setmirror(MI_1);
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break;
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}
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}
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switch (A & 0xF00C)
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{
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case 0xB000:
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reg[0] = (reg[0] & 0xF0) | (V & 0x0F);
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SetBank_PPUSUB( 0, reg[0] );
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break;
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case 0xB004:
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reg[0] = (reg[0] & 0x0F) | ((V & 0x0F) << 4);
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SetBank_PPUSUB( 0, reg[0] + ((V>>4)*0x100) );
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break;
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case 0xB008:
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reg[1] = (reg[1] & 0xF0) | (V & 0x0F);
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SetBank_PPUSUB( 1, reg[1] );
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break;
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case 0xB00C:
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reg[1] = (reg[1] & 0x0F) | ((V & 0x0F) << 4);
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SetBank_PPUSUB( 1, reg[1] + ((V>>4)*0x100) );
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break;
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case 0xC000:
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reg[2] = (reg[2] & 0xF0) | (V & 0x0F);
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SetBank_PPUSUB( 2, reg[2] );
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break;
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case 0xC004:
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reg[2] = (reg[2] & 0x0F) | ((V & 0x0F) << 4);
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SetBank_PPUSUB( 2, reg[2] + ((V>>4)*0x100) );
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break;
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case 0xC008:
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reg[3] = (reg[3] & 0xF0) | (V & 0x0F);
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SetBank_PPUSUB( 3, reg[3] );
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break;
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case 0xC00C:
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reg[3] = (reg[3] & 0x0F) | ((V & 0x0F) << 4);
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SetBank_PPUSUB( 3, reg[3] + ((V>>4)*0x100) );
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break;
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case 0xD000:
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reg[4] = (reg[4] & 0xF0) | (V & 0x0F);
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SetBank_PPUSUB( 4, reg[4] );
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break;
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case 0xD004:
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reg[4] = (reg[4] & 0x0F) | ((V & 0x0F) << 4);
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SetBank_PPUSUB( 4, reg[4] + ((V>>4)*0x100) );
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break;
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case 0xD008:
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reg[5] = (reg[5] & 0xF0) | (V & 0x0F);
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SetBank_PPUSUB( 5, reg[5] );
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break;
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case 0xD00C:
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reg[5] = (reg[5] & 0x0F) | ((V & 0x0F) << 4);
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SetBank_PPUSUB( 5, reg[5] + ((V>>4)*0x100) );
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break;
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case 0xE000:
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reg[6] = (reg[6] & 0xF0) | (V & 0x0F);
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SetBank_PPUSUB( 6, reg[6] );
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break;
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case 0xE004:
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reg[6] = (reg[6] & 0x0F) | ((V & 0x0F) << 4);
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SetBank_PPUSUB( 6, reg[6] + ((V>>4)*0x100) );
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break;
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case 0xE008:
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reg[7] = (reg[7] & 0xF0) | (V & 0x0F);
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SetBank_PPUSUB( 7, reg[7] );
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break;
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case 0xE00C:
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reg[7] = (reg[7] & 0x0F) | ((V & 0x0F) << 4);
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SetBank_PPUSUB( 7, reg[7] + ((V>>4)*0x100) );
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break;
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case 0xF000:
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irq_latch = (irq_latch & 0xF0) | (V & 0x0F);
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break;
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case 0xF004:
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irq_latch = (irq_latch & 0x0F) | ((V & 0x0F) << 4);
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break;
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case 0xF008:
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irq_enable = V & 0x03;
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if (irq_enable & 0x02)
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{
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irq_counter = irq_latch;
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irq_clock = 0;
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}
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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default:
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break;
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//printf("Not handled 0x%X 0x%X", A, V);
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}
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}
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static void Mapper253_Power(void)
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{
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int i;
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for (i = 0; i != 8; ++i)
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reg[i] = i;
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reg[8] = 0;
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irq_enable = 0;
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irq_counter = 0;
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irq_latch = 0;
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irq_clock = 0;
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VRAM_switch = 0;
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setprg16(0x8000, 0); //first bank
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setprg16(0xC000, head.ROM_size - 1); //last bank
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setchr8(0);
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SetWriteHandler(0x8000, 0xFFFF, Mapper253_Write);
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SetReadHandler(0x8000, 0xFFFF, CartBR);
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}
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static void Mapper253_Close(void)
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{
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}
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void Mapper253_Init(CartInfo *info)
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{
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info->Power = Mapper253_Power;
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MapIRQHook = Mapper253_IRQHook;
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info->Close = Mapper253_Close;
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SetWriteHandler(0x8000, 0xFFFF, Mapper253_Write);
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SetReadHandler(0x8000, 0xFFFF, CartBR);
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}
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