mirror of
https://github.com/dborth/fceugx.git
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328 lines
9.2 KiB
C++
328 lines
9.2 KiB
C++
/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2007-2010 CaH4e3
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* VR02/VT03 Console and OneBus System
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*
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* Street Dance (Dance pad) (Unl)
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* 101-in-1 Arcade Action II
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* DreamGEAR 75-in-1, etc.
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*
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*/
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#include "mapinc.h"
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// General Purpose Registers
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static uint8 cpu410x[16], ppu201x[16], apu40xx[64];
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// IRQ Registers
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static uint8 IRQCount, IRQa, IRQReload;
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#define IRQLatch cpu410x[0x1] // accc cccc, a = 0, AD12 switching, a = 1, HSYNC switching
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// MMC3 Registers
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static uint8 inv_hack = 0; // some OneBus Systems have swapped PRG reg commans in MMC3 inplementation,
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// trying to autodetect unusual behavior, due not to add a new mapper.
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#define mmc3cmd cpu410x[0x5] // pcv- ----, p - program swap, c - video swap, v - internal VRAM enable
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#define mirror cpu410x[0x6] // ---- ---m, m = 0 - H, m = 1 - V
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// APU Registers
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static uint8 pcm_enable = 0, pcm_irq = 0;
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static int16 pcm_addr, pcm_size, pcm_latch, pcm_clock = 0xE1;
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static writefunc defapuwrite[64];
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static readfunc defapuread[64];
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static uint32 WRAMSIZE;
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static uint8 *WRAM = NULL;
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static SFORMAT StateRegs[] =
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{
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{ cpu410x, 16, "REGC" },
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{ ppu201x, 16, "REGS" },
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{ apu40xx, 64, "REGA" },
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{ &IRQReload, 1, "IRQR" },
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{ &IRQCount, 1, "IRQC" },
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{ &IRQa, 1, "IRQA" },
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{ &pcm_enable, 1, "PCME" },
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{ &pcm_irq, 1, "PCMI" },
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{ &pcm_addr, 2, "PCMA" },
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{ &pcm_size, 2, "PCMS" },
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{ &pcm_latch, 2, "PCML" },
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{ &pcm_clock, 2, "PCMC" },
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{ 0 }
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};
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static void PSync(void) {
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uint8 bankmode = cpu410x[0xb] & 7;
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uint8 mask = (bankmode == 0x7) ? (0xff) : (0x3f >> bankmode);
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uint32 block = ((cpu410x[0x0] & 0xf0) << 4) + (cpu410x[0xa] & (~mask));
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uint32 pswap = (mmc3cmd & 0x40) << 8;
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// uint8 bank0 = (cpu410x[0xb] & 0x40)?(~1):(cpu410x[0x7]);
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// uint8 bank1 = cpu410x[0x8];
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// uint8 bank2 = (cpu410x[0xb] & 0x40)?(cpu410x[0x9]):(~1);
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// uint8 bank3 = ~0;
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uint8 bank0 = cpu410x[0x7 ^ inv_hack];
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uint8 bank1 = cpu410x[0x8 ^ inv_hack];
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uint8 bank2 = (cpu410x[0xb] & 0x40) ? (cpu410x[0x9]) : (~1);
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uint8 bank3 = ~0;
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// FCEU_printf(" PRG: %04x [%02x]",0x8000^pswap,block | (bank0 & mask));
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setprg8(0x8000 ^ pswap, block | (bank0 & mask));
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// FCEU_printf(" %04x [%02x]",0xa000^pswap,block | (bank1 & mask));
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setprg8(0xa000, block | (bank1 & mask));
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// FCEU_printf(" %04x [%02x]",0xc000^pswap,block | (bank2 & mask));
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setprg8(0xc000 ^ pswap, block | (bank2 & mask));
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// FCEU_printf(" %04x [%02x]\n",0xe000^pswap,block | (bank3 & mask));
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setprg8(0xe000, block | (bank3 & mask));
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}
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static void CSync(void) {
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static const uint8 midx[8] = { 0, 1, 2, 0, 3, 4, 5, 0 };
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uint8 mask = 0xff >> midx[ppu201x[0xa] & 7];
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uint32 block = ((cpu410x[0x0] & 0x0f) << 11) + ((ppu201x[0x8] & 0x70) << 4) + (ppu201x[0xa] & (~mask));
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uint32 cswap = (mmc3cmd & 0x80) << 5;
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uint8 bank0 = ppu201x[0x6] & (~1);
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uint8 bank1 = ppu201x[0x6] | 1;
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uint8 bank2 = ppu201x[0x7] & (~1);
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uint8 bank3 = ppu201x[0x7] | 1;
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uint8 bank4 = ppu201x[0x2];
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uint8 bank5 = ppu201x[0x3];
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uint8 bank6 = ppu201x[0x4];
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uint8 bank7 = ppu201x[0x5];
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setchr1(0x0000 ^ cswap, block | (bank0 & mask));
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setchr1(0x0400 ^ cswap, block | (bank1 & mask));
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setchr1(0x0800 ^ cswap, block | (bank2 & mask));
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setchr1(0x0c00 ^ cswap, block | (bank3 & mask));
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setchr1(0x1000 ^ cswap, block | (bank4 & mask));
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setchr1(0x1400 ^ cswap, block | (bank5 & mask));
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setchr1(0x1800 ^ cswap, block | (bank6 & mask));
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setchr1(0x1c00 ^ cswap, block | (bank7 & mask));
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setmirror((mirror ^ 1) & 1);
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}
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static void Sync(void) {
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PSync();
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CSync();
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}
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static DECLFW(UNLOneBusWriteCPU410X) {
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// FCEU_printf("CPU %04x:%04x\n",A,V);
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switch (A & 0xf) {
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case 0x1: IRQLatch = V & 0xfe; break; // <20><> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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case 0x2: IRQReload = 1; break;
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case 0x3: X6502_IRQEnd(FCEU_IQEXT); IRQa = 0; break;
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case 0x4: IRQa = 1; break;
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default:
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cpu410x[A & 0xf] = V;
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Sync();
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}
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}
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static DECLFW(UNLOneBusWritePPU201X) {
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// FCEU_printf("PPU %04x:%04x\n",A,V);
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ppu201x[A & 0x0f] = V;
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Sync();
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}
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static DECLFW(UNLOneBusWriteMMC3) {
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// FCEU_printf("MMC %04x:%04x\n",A,V);
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switch (A & 0xe001) {
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case 0x8000: mmc3cmd = (mmc3cmd & 0x38) | (V & 0xc7); Sync(); break;
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case 0x8001:
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{
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switch (mmc3cmd & 7) {
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case 0: ppu201x[0x6] = V; CSync(); break;
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case 1: ppu201x[0x7] = V; CSync(); break;
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case 2: ppu201x[0x2] = V; CSync(); break;
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case 3: ppu201x[0x3] = V; CSync(); break;
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case 4: ppu201x[0x4] = V; CSync(); break;
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case 5: ppu201x[0x5] = V; CSync(); break;
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case 6: cpu410x[0x7] = V; PSync(); break;
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case 7: cpu410x[0x8] = V; PSync(); break;
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}
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break;
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}
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case 0xa000: mirror = V; CSync(); break;
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case 0xc000: IRQLatch = V & 0xfe; break;
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case 0xc001: IRQReload = 1; break;
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case 0xe000: X6502_IRQEnd(FCEU_IQEXT); IRQa = 0; break;
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case 0xe001: IRQa = 1; break;
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}
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}
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static void UNLOneBusIRQHook(void) {
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uint32 count = IRQCount;
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if (!count || IRQReload) {
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IRQCount = IRQLatch;
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IRQReload = 0;
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} else
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IRQCount--;
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if (count && !IRQCount) {
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if (IRQa)
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X6502_IRQBegin(FCEU_IQEXT);
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}
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}
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static DECLFW(UNLOneBusWriteAPU40XX) {
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// if(((A & 0x3f)!=0x16) && ((apu40xx[0x30] & 0x10) || ((A & 0x3f)>0x17)))FCEU_printf("APU %04x:%04x\n",A,V);
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apu40xx[A & 0x3f] = V;
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switch (A & 0x3f) {
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case 0x12:
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if (apu40xx[0x30] & 0x10) {
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pcm_addr = V << 6;
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}
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break;
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case 0x13:
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if (apu40xx[0x30] & 0x10) {
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pcm_size = (V << 4) + 1;
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}
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break;
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case 0x15:
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if (apu40xx[0x30] & 0x10) {
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pcm_enable = V & 0x10;
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if (pcm_irq) {
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X6502_IRQEnd(FCEU_IQEXT);
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pcm_irq = 0;
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}
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if (pcm_enable)
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pcm_latch = pcm_clock;
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V &= 0xef;
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}
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break;
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}
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defapuwrite[A & 0x3f](A, V);
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}
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static DECLFR(UNLOneBusReadAPU40XX) {
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uint8 result = defapuread[A & 0x3f](A);
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// FCEU_printf("read %04x, %02x\n",A,result);
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switch (A & 0x3f) {
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case 0x15:
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if (apu40xx[0x30] & 0x10) {
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result = (result & 0x7f) | pcm_irq;
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}
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break;
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}
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return result;
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}
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static void UNLOneBusCpuHook(int a) {
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if (pcm_enable) {
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pcm_latch -= a;
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if (pcm_latch <= 0) {
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pcm_latch += pcm_clock;
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pcm_size--;
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if (pcm_size < 0) {
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pcm_irq = 0x80;
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pcm_enable = 0;
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X6502_IRQBegin(FCEU_IQEXT);
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} else {
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uint16 addr = pcm_addr | ((apu40xx[0x30]^3) << 14);
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uint8 raw_pcm = ARead[addr](addr) >> 1;
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defapuwrite[0x11](0x4011, raw_pcm);
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pcm_addr++;
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pcm_addr &= 0x7FFF;
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}
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}
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}
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}
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static void UNLOneBusPower(void) {
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uint32 i;
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IRQReload = IRQCount = IRQa = 0;
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memset(cpu410x, 0x00, sizeof(cpu410x));
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memset(ppu201x, 0x00, sizeof(ppu201x));
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memset(apu40xx, 0x00, sizeof(apu40xx));
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SetupCartCHRMapping(0, PRGptr[0], PRGsize[0], 0);
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for (i = 0; i < 64; i++) {
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defapuread[i] = GetReadHandler(0x4000 | i);
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defapuwrite[i] = GetWriteHandler(0x4000 | i);
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}
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SetReadHandler(0x4000, 0x403f, UNLOneBusReadAPU40XX);
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SetWriteHandler(0x4000, 0x403f, UNLOneBusWriteAPU40XX);
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SetReadHandler(0x8000, 0xFFFF, CartBR);
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SetWriteHandler(0x2010, 0x201f, UNLOneBusWritePPU201X);
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SetWriteHandler(0x4100, 0x410f, UNLOneBusWriteCPU410X);
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SetWriteHandler(0x8000, 0xffff, UNLOneBusWriteMMC3);
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if (WRAMSIZE) {
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FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
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SetWriteHandler(0x6000, 0x6000 + ((WRAMSIZE - 1) & 0x1fff), CartBW);
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SetReadHandler(0x6000, 0x6000 + ((WRAMSIZE - 1) & 0x1fff), CartBR);
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setprg8r(0x10, 0x6000, 0);
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}
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Sync();
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}
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static void UNLOneBusReset(void) {
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IRQReload = IRQCount = IRQa = 0;
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memset(cpu410x, 0x00, sizeof(cpu410x));
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memset(ppu201x, 0x00, sizeof(ppu201x));
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memset(apu40xx, 0x00, sizeof(apu40xx));
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Sync();
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}
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static void StateRestore(int version) {
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Sync();
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}
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void UNLOneBusClose(void) {
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if (WRAM)
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FCEU_gfree(WRAM);
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WRAM = NULL;
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}
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void UNLOneBus_Init(CartInfo *info) {
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info->Power = UNLOneBusPower;
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info->Reset = UNLOneBusReset;
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info->Close = UNLOneBusClose;
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if (((*(uint32*)&(info->MD5)) == 0x305fcdc3) || // PowerJoy Supermax Carts
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((*(uint32*)&(info->MD5)) == 0x6abfce8e))
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inv_hack = 0xf;
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GameHBIRQHook = UNLOneBusIRQHook;
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MapIRQHook = UNLOneBusCpuHook;
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GameStateRestore = StateRestore;
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AddExState(&StateRegs, ~0, 0, 0);
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WRAMSIZE = 8 * 1024;
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if (info->ines2)
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WRAMSIZE = info->wram_size + info->battery_wram_size;
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if (WRAMSIZE) {
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WRAM = (uint8*)FCEU_gmalloc(WRAMSIZE);
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SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1);
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AddExState(WRAM, WRAMSIZE, 0, "WRAM");
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if (info->battery) {
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info->SaveGame[0] = WRAM;
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info->SaveGameLen[0] = WRAMSIZE;
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}
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}
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}
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