mirror of
https://github.com/dborth/fceugx.git
synced 2024-05-29 06:08:43 +02:00
393 lines
9.4 KiB
C++
393 lines
9.4 KiB
C++
/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 1998 BERO
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* Copyright (C) 2002 Xodnizel
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "mapinc.h"
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static void GenMMC1Power(void);
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static void GenMMC1Init(CartInfo *info, int prg, int chr, int wram, int battery);
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static uint8 DRegs[4];
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static uint8 Buffer, BufferShift;
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static int mmc1opts;
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static void (*MMC1CHRHook4)(uint32 A, uint8 V);
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static void (*MMC1PRGHook16)(uint32 A, uint8 V);
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static uint8 *WRAM = NULL;
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static uint8 *CHRRAM = NULL;
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static int is155, is171;
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static DECLFW(MBWRAM) {
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if (!(DRegs[3] & 0x10) || is155)
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Page[A >> 11][A] = V; // WRAM is enabled.
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}
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static DECLFR(MAWRAM) {
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if ((DRegs[3] & 0x10) && !is155)
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return X.DB; // WRAM is disabled
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return(Page[A >> 11][A]);
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}
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static void MMC1CHR(void) {
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if (mmc1opts & 4) {
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if (DRegs[0] & 0x10)
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setprg8r(0x10, 0x6000, (DRegs[1] >> 4) & 1);
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else
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setprg8r(0x10, 0x6000, (DRegs[1] >> 3) & 1);
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}
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if (MMC1CHRHook4) {
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if (DRegs[0] & 0x10) {
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MMC1CHRHook4(0x0000, DRegs[1]);
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MMC1CHRHook4(0x1000, DRegs[2]);
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} else {
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MMC1CHRHook4(0x0000, (DRegs[1] & 0xFE));
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MMC1CHRHook4(0x1000, DRegs[1] | 1);
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}
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} else {
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if (DRegs[0] & 0x10) {
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setchr4(0x0000, DRegs[1]);
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setchr4(0x1000, DRegs[2]);
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} else
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setchr8(DRegs[1] >> 1);
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}
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}
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static void MMC1PRG(void) {
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uint8 offs = DRegs[1] & 0x10;
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if (MMC1PRGHook16) {
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switch (DRegs[0] & 0xC) {
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case 0xC:
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MMC1PRGHook16(0x8000, (DRegs[3] + offs));
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MMC1PRGHook16(0xC000, 0xF + offs);
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break;
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case 0x8:
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MMC1PRGHook16(0xC000, (DRegs[3] + offs));
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MMC1PRGHook16(0x8000, offs);
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break;
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case 0x0:
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case 0x4:
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MMC1PRGHook16(0x8000, ((DRegs[3] & ~1) + offs));
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MMC1PRGHook16(0xc000, ((DRegs[3] & ~1) + offs + 1));
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break;
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}
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} else {
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switch (DRegs[0] & 0xC) {
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case 0xC:
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setprg16(0x8000, (DRegs[3] + offs));
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setprg16(0xC000, 0xF + offs);
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break;
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case 0x8:
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setprg16(0xC000, (DRegs[3] + offs));
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setprg16(0x8000, offs);
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break;
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case 0x0:
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case 0x4:
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setprg16(0x8000, ((DRegs[3] & ~1) + offs));
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setprg16(0xc000, ((DRegs[3] & ~1) + offs + 1));
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break;
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}
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}
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}
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static void MMC1MIRROR(void) {
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if (!is171)
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switch (DRegs[0] & 3) {
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case 2: setmirror(MI_V); break;
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case 3: setmirror(MI_H); break;
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case 0: setmirror(MI_0); break;
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case 1: setmirror(MI_1); break;
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}
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}
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static uint64 lreset;
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static DECLFW(MMC1_write) {
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int n = (A >> 13) - 4;
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/* The MMC1 is busy so ignore the write. */
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/* As of version FCE Ultra 0.81, the timestamp is only
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increased before each instruction is executed(in other words
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precision isn't that great), but this should still work to
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deal with 2 writes in a row from a single RMW instruction.
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*/
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if ((timestampbase + timestamp) < (lreset + 2))
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return;
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// FCEU_printf("Write %04x:%02x\n",A,V);
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if (V & 0x80) {
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DRegs[0] |= 0xC;
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BufferShift = Buffer = 0;
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MMC1PRG();
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lreset = timestampbase + timestamp;
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return;
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}
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Buffer |= (V & 1) << (BufferShift++);
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if (BufferShift == 5) {
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DRegs[n] = Buffer;
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BufferShift = Buffer = 0;
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switch (n) {
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case 0: MMC1MIRROR(); MMC1CHR(); MMC1PRG(); break;
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case 1: MMC1CHR(); MMC1PRG(); break;
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case 2: MMC1CHR(); break;
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case 3: MMC1PRG(); break;
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}
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}
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}
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static void MMC1_Restore(int version) {
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MMC1MIRROR();
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MMC1CHR();
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MMC1PRG();
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lreset = 0; // timestamp(base) is not stored in save states.
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}
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static void MMC1CMReset(void) {
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int i;
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for (i = 0; i < 4; i++)
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DRegs[i] = 0;
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Buffer = BufferShift = 0;
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DRegs[0] = 0x1F;
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DRegs[1] = 0;
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DRegs[2] = 0; // Should this be something other than 0?
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DRegs[3] = 0;
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MMC1MIRROR();
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MMC1CHR();
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MMC1PRG();
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}
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static int DetectMMC1WRAMSize(uint32 crc32) {
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switch (crc32) {
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case 0xc6182024: // Romance of the 3 Kingdoms
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case 0x2225c20f: // Genghis Khan
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case 0x4642dda6: // Nobunaga's Ambition
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case 0x29449ba9: // "" "" (J)
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case 0x2b11e0b0: // "" "" (J)
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case 0xb8747abf: // Best Play Pro Yakyuu Special (J)
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case 0xc9556b36: // Final Fantasy I & II (J) [!]
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FCEU_printf(" >8KB external WRAM present. Use UNIF if you hack the ROM image.\n");
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return(16);
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break;
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default: return(8);
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}
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}
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static uint32 NWCIRQCount;
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static uint8 NWCRec;
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#define NWCDIP 0xE
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static void NWCIRQHook(int a) {
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if (!(NWCRec & 0x10)) {
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NWCIRQCount += a;
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if ((NWCIRQCount | (NWCDIP << 25)) >= 0x3e000000) {
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NWCIRQCount = 0;
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X6502_IRQBegin(FCEU_IQEXT);
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}
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}
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}
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static void NWCCHRHook(uint32 A, uint8 V) {
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if ((V & 0x10)) { // && !(NWCRec&0x10))
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NWCIRQCount = 0;
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X6502_IRQEnd(FCEU_IQEXT);
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}
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NWCRec = V;
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if (V & 0x08)
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MMC1PRG();
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else
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setprg32(0x8000, (V >> 1) & 3);
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}
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static void NWCPRGHook(uint32 A, uint8 V) {
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if (NWCRec & 0x8)
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setprg16(A, 8 | (V & 0x7));
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else
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setprg32(0x8000, (NWCRec >> 1) & 3);
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}
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static void NWCPower(void) {
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GenMMC1Power();
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setchr8r(0, 0);
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}
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void Mapper105_Init(CartInfo *info) {
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GenMMC1Init(info, 256, 256, 8, 0);
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MMC1CHRHook4 = NWCCHRHook;
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MMC1PRGHook16 = NWCPRGHook;
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MapIRQHook = NWCIRQHook;
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info->Power = NWCPower;
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}
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static void GenMMC1Power(void) {
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lreset = 0;
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if (mmc1opts & 1) {
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FCEU_CheatAddRAM(8, 0x6000, WRAM);
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if (mmc1opts & 4)
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FCEU_dwmemset(WRAM, 0, 8192)
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else if (!(mmc1opts & 2))
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FCEU_dwmemset(WRAM, 0, 8192); // wtf?
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}
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SetWriteHandler(0x8000, 0xFFFF, MMC1_write);
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SetReadHandler(0x8000, 0xFFFF, CartBR);
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if (mmc1opts & 1) {
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SetReadHandler(0x6000, 0x7FFF, MAWRAM);
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SetWriteHandler(0x6000, 0x7FFF, MBWRAM);
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setprg8r(0x10, 0x6000, 0);
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}
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MMC1CMReset();
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}
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static void GenMMC1Close(void) {
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if (CHRRAM)
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FCEU_gfree(CHRRAM);
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if (WRAM)
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FCEU_gfree(WRAM);
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CHRRAM = WRAM = NULL;
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}
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static void GenMMC1Init(CartInfo *info, int prg, int chr, int wram, int battery) {
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is155 = 0;
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info->Close = GenMMC1Close;
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MMC1PRGHook16 = MMC1CHRHook4 = 0;
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mmc1opts = 0;
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PRGmask16[0] &= (prg >> 14) - 1;
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CHRmask4[0] &= (chr >> 12) - 1;
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CHRmask8[0] &= (chr >> 13) - 1;
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if (wram) {
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WRAM = (uint8*)FCEU_gmalloc(wram * 1024);
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//mbg 17-jun-08 - this shouldve been cleared to re-initialize save ram
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//ch4 10-dec-08 - nope, this souldn't
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//mbg 29-mar-09 - no time to debate this, we need to keep from breaking some old stuff.
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//we really need to make up a policy for how compatibility and accuracy can be resolved.
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memset(WRAM, 0, wram * 1024);
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mmc1opts |= 1;
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if (wram > 8) mmc1opts |= 4;
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SetupCartPRGMapping(0x10, WRAM, wram * 1024, 1);
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AddExState(WRAM, wram * 1024, 0, "WRAM");
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if (battery) {
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mmc1opts |= 2;
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info->SaveGame[0] = WRAM + ((mmc1opts & 4) ? 8192 : 0);
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info->SaveGameLen[0] = 8192;
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}
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}
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if (!chr) {
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CHRRAM = (uint8*)FCEU_gmalloc(8192);
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SetupCartCHRMapping(0, CHRRAM, 8192, 1);
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AddExState(CHRRAM, 8192, 0, "CHRR");
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}
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AddExState(DRegs, 4, 0, "DREG");
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info->Power = GenMMC1Power;
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GameStateRestore = MMC1_Restore;
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AddExState(&lreset, 8, 1, "LRST");
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AddExState(&Buffer, 1, 1, "BFFR");
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AddExState(&BufferShift, 1, 1, "BFRS");
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}
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void Mapper1_Init(CartInfo *info) {
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int ws = DetectMMC1WRAMSize(info->CRC32);
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GenMMC1Init(info, 512, 256, ws, info->battery);
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}
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/* Same as mapper 1, without respect for WRAM enable bit. */
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void Mapper155_Init(CartInfo *info) {
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GenMMC1Init(info, 512, 256, 8, info->battery);
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is155 = 1;
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}
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/* Same as mapper 1, with different (or without) mirroring control. */
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/* Kaiser KS7058 board, KS203 custom chip */
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void Mapper171_Init(CartInfo *info) {
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GenMMC1Init(info, 32, 32, 0, 0);
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is171 = 1;
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}
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void SAROM_Init(CartInfo *info) {
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GenMMC1Init(info, 128, 64, 8, info->battery);
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}
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void SBROM_Init(CartInfo *info) {
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GenMMC1Init(info, 128, 64, 0, 0);
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}
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void SCROM_Init(CartInfo *info) {
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GenMMC1Init(info, 128, 128, 0, 0);
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}
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void SEROM_Init(CartInfo *info) {
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GenMMC1Init(info, 32, 64, 0, 0);
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}
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void SGROM_Init(CartInfo *info) {
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GenMMC1Init(info, 256, 0, 0, 0);
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}
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void SKROM_Init(CartInfo *info) {
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GenMMC1Init(info, 256, 64, 8, info->battery);
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}
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void SLROM_Init(CartInfo *info) {
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GenMMC1Init(info, 256, 128, 0, 0);
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}
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void SL1ROM_Init(CartInfo *info) {
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GenMMC1Init(info, 128, 128, 0, 0);
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}
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/* Begin unknown - may be wrong - perhaps they use different MMC1s from the
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similarly functioning boards?
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*/
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void SL2ROM_Init(CartInfo *info) {
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GenMMC1Init(info, 256, 256, 0, 0);
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}
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void SFROM_Init(CartInfo *info) {
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GenMMC1Init(info, 256, 256, 0, 0);
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}
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void SHROM_Init(CartInfo *info) {
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GenMMC1Init(info, 256, 256, 0, 0);
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}
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/* End unknown */
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/* */
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/* */
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void SNROM_Init(CartInfo *info) {
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GenMMC1Init(info, 256, 0, 8, info->battery);
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}
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void SOROM_Init(CartInfo *info) {
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GenMMC1Init(info, 256, 0, 16, info->battery);
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}
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