mirror of
https://github.com/dborth/fceugx.git
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325 lines
8.1 KiB
C++
325 lines
8.1 KiB
C++
/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2011 CaH4e3
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* SL12 Protected 3-in-1 mapper hardware (VRC2, MMC3, MMC1)
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* the same as 603-5052 board (TODO: add reading registers, merge)
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* SL1632 2-in-1 protected board, similar to SL12 (TODO: find difference)
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*
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* Known PCB:
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*
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* Garou Densetsu Special (G0904.PCB, Huang-1, GAL dip: W conf.)
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* Kart Fighter (008, Huang-1, GAL dip: W conf.)
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* Somari (008, C5052-13, GAL dip: P conf., GK2-P/GK2-V maskroms)
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* Somari (008, Huang-1, GAL dip: W conf., GK1-P/GK1-V maskroms)
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* AV Mei Shao Nv Zhan Shi (aka AV Pretty Girl Fighting) (SL-12 PCB, Hunag-1, GAL dip: unk conf. SL-11A/SL-11B maskroms)
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* Samurai Spirits (Full version) (Huang-1, GAL dip: unk conf. GS-2A/GS-4A maskroms)
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* Contra Fighter (603-5052 PCB, C5052-3, GAL dip: unk conf. SC603-A/SCB603-B maskroms)
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*
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*/
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#include "mapinc.h"
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static uint8 mode;
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static uint8 vrc2_chr[8], vrc2_prg[2], vrc2_mirr;
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static uint8 mmc3_regs[10], mmc3_ctrl, mmc3_mirr;
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static uint8 IRQCount, IRQLatch, IRQa;
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static uint8 IRQReload;
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static uint8 mmc1_regs[4], mmc1_buffer, mmc1_shift;
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static SFORMAT StateRegs[] =
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{
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{ &mode, 1, "MODE" },
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{ vrc2_chr, 8, "VRCC" },
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{ vrc2_prg, 2, "VRCP" },
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{ &vrc2_mirr, 1, "VRCM" },
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{ mmc3_regs, 10, "M3RG" },
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{ &mmc3_ctrl, 1, "M3CT" },
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{ &mmc3_mirr, 1, "M3MR" },
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{ &IRQReload, 1, "IRQR" },
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{ &IRQCount, 1, "IRQC" },
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{ &IRQLatch, 1, "IRQL" },
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{ &IRQa, 1, "IRQA" },
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{ mmc1_regs, 4, "M1RG" },
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{ &mmc1_buffer, 1, "M1BF" },
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{ &mmc1_shift, 1, "M1MR" },
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{ 0 }
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};
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static void SyncPRG(void) {
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switch (mode & 3) {
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case 0:
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setprg8(0x8000, vrc2_prg[0]);
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setprg8(0xA000, vrc2_prg[1]);
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setprg8(0xC000, ~1);
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setprg8(0xE000, ~0);
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break;
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case 1:
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{
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uint32 swap = (mmc3_ctrl >> 5) & 2;
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setprg8(0x8000, mmc3_regs[6 + swap]);
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setprg8(0xA000, mmc3_regs[7]);
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setprg8(0xC000, mmc3_regs[6 + (swap ^ 2)]);
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setprg8(0xE000, mmc3_regs[9]);
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break;
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}
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case 2:
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case 3:
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{
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uint8 bank = mmc1_regs[3] & 0xF;
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if (mmc1_regs[0] & 8) {
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if (mmc1_regs[0] & 4) {
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setprg16(0x8000, bank);
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setprg16(0xC000, 0x0F);
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} else {
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setprg16(0x8000, 0);
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setprg16(0xC000, bank);
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}
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} else
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setprg32(0x8000, bank >> 1);
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break;
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}
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}
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}
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static void SyncCHR(void) {
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uint32 base = (mode & 4) << 6;
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switch (mode & 3) {
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case 0:
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setchr1(0x0000, base | vrc2_chr[0]);
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setchr1(0x0400, base | vrc2_chr[1]);
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setchr1(0x0800, base | vrc2_chr[2]);
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setchr1(0x0c00, base | vrc2_chr[3]);
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setchr1(0x1000, base | vrc2_chr[4]);
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setchr1(0x1400, base | vrc2_chr[5]);
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setchr1(0x1800, base | vrc2_chr[6]);
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setchr1(0x1c00, base | vrc2_chr[7]);
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break;
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case 1: {
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uint32 swap = (mmc3_ctrl & 0x80) << 5;
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setchr1(0x0000 ^ swap, base | ((mmc3_regs[0]) & 0xFE));
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setchr1(0x0400 ^ swap, base | (mmc3_regs[0] | 1));
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setchr1(0x0800 ^ swap, base | ((mmc3_regs[1]) & 0xFE));
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setchr1(0x0c00 ^ swap, base | (mmc3_regs[1] | 1));
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setchr1(0x1000 ^ swap, base | mmc3_regs[2]);
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setchr1(0x1400 ^ swap, base | mmc3_regs[3]);
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setchr1(0x1800 ^ swap, base | mmc3_regs[4]);
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setchr1(0x1c00 ^ swap, base | mmc3_regs[5]);
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break;
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}
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case 2:
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case 3:
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if (mmc1_regs[0] & 0x10) {
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setchr4(0x0000, mmc1_regs[1]);
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setchr4(0x1000, mmc1_regs[2]);
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} else
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setchr8(mmc1_regs[1] >> 1);
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break;
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}
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}
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static void SyncMIR(void) {
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switch (mode & 3) {
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case 0: {
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setmirror((vrc2_mirr & 1) ^ 1);
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break;
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}
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case 1: {
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setmirror((mmc3_mirr & 1) ^ 1);
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break;
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}
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case 2:
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case 3: {
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switch (mmc1_regs[0] & 3) {
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case 0: setmirror(MI_0); break;
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case 1: setmirror(MI_1); break;
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case 2: setmirror(MI_V); break;
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case 3: setmirror(MI_H); break;
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}
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break;
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}
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}
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}
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static void Sync(void) {
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SyncPRG();
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SyncCHR();
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SyncMIR();
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}
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static DECLFW(UNLSL12ModeWrite) {
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// FCEU_printf("%04X:%02X\n",A,V);
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if ((A & 0x4100) == 0x4100) {
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mode = V;
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if (A & 1) { // hacky hacky, there are two configuration modes on SOMARI HUANG-1 PCBs
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// Solder pads with P1/P2 shorted called SOMARI P,
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// Solder pads with W1/W2 shorted called SOMARI W
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// Both identical 3-in-1 but W wanted MMC1 registers
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// to be reset when switch to MMC1 mode P one - doesn't
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// There is issue with W version of Somari at starting copyrights
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mmc1_regs[0] = 0xc;
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mmc1_regs[3] = 0;
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mmc1_buffer = 0;
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mmc1_shift = 0;
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}
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Sync();
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}
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}
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static DECLFW(UNLSL12Write) {
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// FCEU_printf("%04X:%02X\n",A,V);
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switch (mode & 3) {
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case 0: {
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if ((A >= 0xB000) && (A <= 0xE003)) {
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int32 ind = ((((A & 2) | (A >> 10)) >> 1) + 2) & 7;
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int32 sar = ((A & 1) << 2);
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vrc2_chr[ind] = (vrc2_chr[ind] & (0xF0 >> sar)) | ((V & 0x0F) << sar);
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SyncCHR();
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} else
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switch (A & 0xF000) {
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case 0x8000: vrc2_prg[0] = V; SyncPRG(); break;
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case 0xA000: vrc2_prg[1] = V; SyncPRG(); break;
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case 0x9000: vrc2_mirr = V; SyncMIR(); break;
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}
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break;
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}
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case 1: {
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switch (A & 0xE001) {
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case 0x8000: {
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uint8 old_ctrl = mmc3_ctrl;
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mmc3_ctrl = V;
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if ((old_ctrl & 0x40) != (mmc3_ctrl & 0x40))
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SyncPRG();
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if ((old_ctrl & 0x80) != (mmc3_ctrl & 0x80))
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SyncCHR();
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break;
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}
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case 0x8001:
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mmc3_regs[mmc3_ctrl & 7] = V;
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if ((mmc3_ctrl & 7) < 6)
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SyncCHR();
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else
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SyncPRG();
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break;
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case 0xA000:
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mmc3_mirr = V;
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SyncMIR();
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break;
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case 0xC000:
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IRQLatch = V;
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break;
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case 0xC001:
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IRQReload = 1;
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break;
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case 0xE000:
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X6502_IRQEnd(FCEU_IQEXT);
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IRQa = 0;
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break;
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case 0xE001:
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IRQa = 1;
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break;
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}
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break;
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}
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case 2:
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case 3: {
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if (V & 0x80) {
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mmc1_regs[0] |= 0xc;
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mmc1_buffer = mmc1_shift = 0;
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SyncPRG();
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} else {
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uint8 n = (A >> 13) - 4;
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mmc1_buffer |= (V & 1) << (mmc1_shift++);
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if (mmc1_shift == 5) {
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mmc1_regs[n] = mmc1_buffer;
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mmc1_buffer = mmc1_shift = 0;
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switch (n) {
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case 0: SyncMIR();
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case 2: SyncCHR();
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case 3:
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case 1: SyncPRG();
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}
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}
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}
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break;
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}
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}
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}
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static void UNLSL12HBIRQ(void) {
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if ((mode & 3) == 1) {
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int32 count = IRQCount;
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if (!count || IRQReload) {
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IRQCount = IRQLatch;
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IRQReload = 0;
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} else
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IRQCount--;
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if (!IRQCount) {
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if (IRQa)
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X6502_IRQBegin(FCEU_IQEXT);
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}
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}
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}
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static void StateRestore(int version) {
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Sync();
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}
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static void UNLSL12Power(void) {
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mode = 0;
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vrc2_chr[0] = ~0;
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vrc2_chr[1] = ~0;
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vrc2_chr[2] = ~0;
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vrc2_chr[3] = ~0; // W conf. of Somari wanted CHR3 has to be set to BB bank (or similar), but doesn't do that directly
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vrc2_chr[4] = 4;
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vrc2_chr[5] = 5;
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vrc2_chr[6] = 6;
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vrc2_chr[7] = 7;
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vrc2_prg[0] = 0;
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vrc2_prg[1] = 1;
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vrc2_mirr = 0;
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mmc3_regs[0] = 0;
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mmc3_regs[1] = 2;
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mmc3_regs[2] = 4;
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mmc3_regs[3] = 5;
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mmc3_regs[4] = 6;
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mmc3_regs[5] = 7;
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mmc3_regs[6] = ~3;
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mmc3_regs[7] = ~2;
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mmc3_regs[8] = ~1;
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mmc3_regs[9] = ~0;
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mmc3_ctrl = mmc3_mirr = IRQCount = IRQLatch = IRQa = 0;
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mmc1_regs[0] = 0xc;
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mmc1_regs[1] = 0;
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mmc1_regs[2] = 0;
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mmc1_regs[3] = 0;
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mmc1_buffer = 0;
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mmc1_shift = 0;
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Sync();
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SetReadHandler(0x8000, 0xFFFF, CartBR);
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SetWriteHandler(0x4100, 0x7FFF, UNLSL12ModeWrite);
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SetWriteHandler(0x8000, 0xFFFF, UNLSL12Write);
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}
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void UNLSL12_Init(CartInfo *info) {
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info->Power = UNLSL12Power;
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GameHBIRQHook = UNLSL12HBIRQ;
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GameStateRestore = StateRestore;
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AddExState(&StateRegs, ~0, 0, 0);
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}
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