671 lines
14 KiB
C++
671 lines
14 KiB
C++
/*
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* CPUC64_SC.cpp - Single-cycle 6510 (C64) emulation
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*
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* Frodo (C) 1994-1997,2002-2009 Christian Bauer
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* Notes:
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* ------
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*
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* Opcode execution:
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* - All opcodes are resolved into single clock cycles. There is one
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* switch case for each cycle.
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* - The "state" variable specifies the routine to be executed in the
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* next cycle. Its upper 8 bits contain the current opcode, its lower
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* 8 bits contain the cycle number (0..7) within the opcode.
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* - Opcodes are fetched in cycle 0 (state = 0)
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* - The states 0x0010..0x0027 are used for interrupts
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* - There is exactly one memory access in each clock cycle
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*
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* Memory configurations:
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*
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* $01 $a000-$bfff $d000-$dfff $e000-$ffff
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* -----------------------------------------------
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* 0 RAM RAM RAM
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* 1 RAM Char ROM RAM
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* 2 RAM Char ROM Kernal ROM
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* 3 Basic ROM Char ROM Kernal ROM
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* 4 RAM RAM RAM
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* 5 RAM I/O RAM
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* 6 RAM I/O Kernal ROM
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* 7 Basic ROM I/O Kernal ROM
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*
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* - All memory accesses are done with the read_byte() and
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* write_byte() functions which also do the memory address
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* decoding.
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* - If a write occurs to addresses 0 or 1, new_config is
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* called to check whether the memory configuration has
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* changed
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* - The possible interrupt sources are:
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* INT_VICIRQ: I flag is checked, jump to ($fffe)
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* INT_CIAIRQ: I flag is checked, jump to ($fffe)
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* INT_NMI: Jump to ($fffa)
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* INT_RESET: Jump to ($fffc)
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* - The z_flag variable has the inverse meaning of the
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* 6510 Z flag
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* - Only the highest bit of the n_flag variable is used
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* - The $f2 opcode that would normally crash the 6510 is
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* used to implement emulator-specific functions, mainly
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* those for the IEC routines
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*
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* Incompatibilities:
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* ------------------
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*
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* - If BA is low and AEC is high, read accesses should occur
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*/
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#include "sysdeps.h"
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#include "CPUC64.h"
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#include "CPU_common.h"
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#include "C64.h"
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#include "VIC.h"
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#include "SID.h"
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#include "CIA.h"
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#include "REU.h"
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#include "IEC.h"
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#include "Display.h"
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#include "Version.h"
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enum {
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INT_RESET = 3
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};
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/*
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* 6510 constructor: Initialize registers
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*/
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MOS6510::MOS6510(C64 *c64, uint8 *Ram, uint8 *Basic, uint8 *Kernal, uint8 *Char, uint8 *Color)
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: the_c64(c64), ram(Ram), basic_rom(Basic), kernal_rom(Kernal), char_rom(Char), color_ram(Color)
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{
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a = x = y = 0;
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sp = 0xff;
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n_flag = z_flag = 0;
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v_flag = d_flag = c_flag = false;
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i_flag = true;
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dfff_byte = 0x55;
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BALow = false;
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first_irq_cycle = first_nmi_cycle = 0;
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}
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/*
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* Reset CPU asynchronously
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*/
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void MOS6510::AsyncReset(void)
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{
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interrupt.intr[INT_RESET] = true;
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}
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/*
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* Raise NMI asynchronously (Restore key)
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*/
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void MOS6510::AsyncNMI(void)
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{
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if (!nmi_state)
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interrupt.intr[INT_NMI] = true;
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}
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/*
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* Get 6510 register state
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*/
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void MOS6510::GetState(MOS6510State *s)
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{
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s->a = a;
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s->x = x;
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s->y = y;
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s->p = 0x20 | (n_flag & 0x80);
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if (v_flag) s->p |= 0x40;
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if (d_flag) s->p |= 0x08;
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if (i_flag) s->p |= 0x04;
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if (!z_flag) s->p |= 0x02;
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if (c_flag) s->p |= 0x01;
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s->ddr = ddr;
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s->pr = pr;
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s->pc = pc;
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s->sp = sp | 0x0100;
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s->intr[INT_VICIRQ] = interrupt.intr[INT_VICIRQ];
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s->intr[INT_CIAIRQ] = interrupt.intr[INT_CIAIRQ];
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s->intr[INT_NMI] = interrupt.intr[INT_NMI];
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s->intr[INT_RESET] = interrupt.intr[INT_RESET];
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s->nmi_state = nmi_state;
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s->dfff_byte = dfff_byte;
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s->instruction_complete = (state == 0);
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}
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/*
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* Restore 6510 state
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*/
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void MOS6510::SetState(MOS6510State *s)
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{
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a = s->a;
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x = s->x;
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y = s->y;
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n_flag = s->p;
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v_flag = s->p & 0x40;
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d_flag = s->p & 0x08;
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i_flag = s->p & 0x04;
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z_flag = !(s->p & 0x02);
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c_flag = s->p & 0x01;
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ddr = s->ddr;
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pr = s->pr;
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pr_out = 0; // FIXME: should be saved in MOS6510State
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new_config();
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pc = s->pc;
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sp = s->sp & 0xff;
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interrupt.intr[INT_VICIRQ] = s->intr[INT_VICIRQ];
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interrupt.intr[INT_CIAIRQ] = s->intr[INT_CIAIRQ];
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interrupt.intr[INT_NMI] = s->intr[INT_NMI];
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interrupt.intr[INT_RESET] = s->intr[INT_RESET];
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nmi_state = s->nmi_state;
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dfff_byte = s->dfff_byte;
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if (s->instruction_complete)
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state = 0;
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}
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/*
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* Memory configuration has probably changed
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*/
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void MOS6510::new_config(void)
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{
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pr_out = (pr_out & ~ddr) | (pr & ddr);
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uint8 port = pr | ~ddr;
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basic_in = (port & 3) == 3;
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kernal_in = port & 2;
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char_in = (port & 3) && !(port & 4);
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io_in = (port & 3) && (port & 4);
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}
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/*
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* Read a byte from I/O / ROM space
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*/
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inline uint8 MOS6510::read_byte_io(uint16 adr)
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{
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switch (adr >> 12) {
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case 0xa:
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case 0xb:
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if (basic_in)
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return basic_rom[adr & 0x1fff];
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else
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return ram[adr];
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case 0xc:
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return ram[adr];
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case 0xd:
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if (io_in)
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switch ((adr >> 8) & 0x0f) {
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case 0x0: // VIC
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case 0x1:
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case 0x2:
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case 0x3:
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return TheVIC->ReadRegister(adr & 0x3f);
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case 0x4: // SID
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case 0x5:
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case 0x6:
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case 0x7:
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return TheSID->ReadRegister(adr & 0x1f);
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case 0x8: // Color RAM
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case 0x9:
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case 0xa:
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case 0xb:
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return color_ram[adr & 0x03ff] & 0x0f | TheVIC->LastVICByte & 0xf0;
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case 0xc: // CIA 1
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return TheCIA1->ReadRegister(adr & 0x0f);
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case 0xd: // CIA 2
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return TheCIA2->ReadRegister(adr & 0x0f);
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case 0xe: // REU/Open I/O
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case 0xf:
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if ((adr & 0xfff0) == 0xdf00)
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return TheREU->ReadRegister(adr & 0x0f);
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else if (adr < 0xdfa0)
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return TheVIC->LastVICByte;
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else
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return read_emulator_id(adr & 0x7f);
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}
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else if (char_in)
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return char_rom[adr & 0x0fff];
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else
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return ram[adr];
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case 0xe:
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case 0xf:
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if (kernal_in)
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return kernal_rom[adr & 0x1fff];
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else
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return ram[adr];
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default: // Can't happen
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return 0;
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}
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}
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/*
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* Read a byte from the CPU's address space
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*/
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uint8 MOS6510::read_byte(uint16 adr)
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{
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if (adr < 0xa000) {
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if (adr >= 2) {
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return ram[adr];
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} else if (adr == 0) {
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return ddr;
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} else {
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uint8 byte = (pr | ~ddr) & (pr_out | 0x17);
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if (!(ddr & 0x20))
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byte &= 0xdf;
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return byte;
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}
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} else
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return read_byte_io(adr);
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}
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/*
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* $dfa0-$dfff: Emulator identification
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*/
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const char frodo_id[0x5c] = "FRODO\r(C) 1994-1997 CHRISTIAN BAUER";
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uint8 MOS6510::read_emulator_id(uint16 adr)
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{
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switch (adr) {
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case 0x7c: // $dffc: revision
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return FRODO_REVISION << 4;
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case 0x7d: // $dffd: version
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return FRODO_VERSION;
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case 0x7e: // $dffe returns 'F' (Frodo ID)
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return 'F';
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case 0x7f: // $dfff alternates between $55 and $aa
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dfff_byte = ~dfff_byte;
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return dfff_byte;
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default:
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return frodo_id[adr - 0x20];
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}
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}
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/*
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* Read a word (little-endian) from the CPU's address space
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*/
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inline uint16 MOS6510::read_word(uint16 adr)
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{
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return read_byte(adr) | (read_byte(adr+1) << 8);
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}
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/*
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* Write a byte to I/O space
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*/
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inline void MOS6510::write_byte_io(uint16 adr, uint8 byte)
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{
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if (adr >= 0xe000) {
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ram[adr] = byte;
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if (adr == 0xff00)
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TheREU->FF00Trigger();
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} else if (io_in)
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switch ((adr >> 8) & 0x0f) {
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case 0x0: // VIC
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case 0x1:
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case 0x2:
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case 0x3:
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TheVIC->WriteRegister(adr & 0x3f, byte);
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return;
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case 0x4: // SID
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case 0x5:
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case 0x6:
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case 0x7:
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TheSID->WriteRegister(adr & 0x1f, byte);
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return;
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case 0x8: // Color RAM
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case 0x9:
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case 0xa:
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case 0xb:
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color_ram[adr & 0x03ff] = byte & 0x0f;
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return;
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case 0xc: // CIA 1
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TheCIA1->WriteRegister(adr & 0x0f, byte);
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return;
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case 0xd: // CIA 2
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TheCIA2->WriteRegister(adr & 0x0f, byte);
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return;
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case 0xe: // REU/Open I/O
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case 0xf:
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if ((adr & 0xfff0) == 0xdf00)
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TheREU->WriteRegister(adr & 0x0f, byte);
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return;
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}
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else
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ram[adr] = byte;
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}
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/*
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* Write a byte to the CPU's address space
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*/
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void MOS6510::write_byte(uint16 adr, uint8 byte)
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{
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if (adr < 0xd000) {
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if (adr >= 2)
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ram[adr] = byte;
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else if (adr == 0) {
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ddr = byte;
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ram[0] = TheVIC->LastVICByte;
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new_config();
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} else {
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pr = byte;
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ram[1] = TheVIC->LastVICByte;
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new_config();
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}
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} else
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write_byte_io(adr, byte);
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}
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/*
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* Read byte from 6510 address space with special memory config (used by SAM)
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*/
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uint8 MOS6510::ExtReadByte(uint16 adr)
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{
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// Save old memory configuration
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bool bi = basic_in, ki = kernal_in, ci = char_in, ii = io_in;
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// Set new configuration
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basic_in = (ExtConfig & 3) == 3;
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kernal_in = ExtConfig & 2;
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char_in = (ExtConfig & 3) && ~(ExtConfig & 4);
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io_in = (ExtConfig & 3) && (ExtConfig & 4);
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// Read byte
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uint8 byte = read_byte(adr);
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// Restore old configuration
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basic_in = bi; kernal_in = ki; char_in = ci; io_in = ii;
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return byte;
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}
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/*
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* Write byte to 6510 address space with special memory config (used by SAM)
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*/
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void MOS6510::ExtWriteByte(uint16 adr, uint8 byte)
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{
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// Save old memory configuration
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bool bi = basic_in, ki = kernal_in, ci = char_in, ii = io_in;
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// Set new configuration
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basic_in = (ExtConfig & 3) == 3;
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kernal_in = ExtConfig & 2;
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char_in = (ExtConfig & 3) && ~(ExtConfig & 4);
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io_in = (ExtConfig & 3) && (ExtConfig & 4);
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// Write byte
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write_byte(adr, byte);
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// Restore old configuration
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basic_in = bi; kernal_in = ki; char_in = ci; io_in = ii;
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}
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/*
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* Read byte from 6510 address space with current memory config (used by REU)
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*/
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uint8 MOS6510::REUReadByte(uint16 adr)
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{
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return read_byte(adr);
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}
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/*
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* Write byte to 6510 address space with current memory config (used by REU)
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*/
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void MOS6510::REUWriteByte(uint16 adr, uint8 byte)
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{
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write_byte(adr, byte);
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}
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/*
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* Adc instruction
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*/
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inline void MOS6510::do_adc(uint8 byte)
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{
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if (!d_flag) {
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uint16 tmp;
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// Binary mode
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tmp = a + byte + (c_flag ? 1 : 0);
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c_flag = tmp > 0xff;
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v_flag = !((a ^ byte) & 0x80) && ((a ^ tmp) & 0x80);
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z_flag = n_flag = a = tmp;
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} else {
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uint16 al, ah;
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// Decimal mode
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al = (a & 0x0f) + (byte & 0x0f) + (c_flag ? 1 : 0); // Calculate lower nybble
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if (al > 9) al += 6; // BCD fixup for lower nybble
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ah = (a >> 4) + (byte >> 4); // Calculate upper nybble
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if (al > 0x0f) ah++;
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z_flag = a + byte + (c_flag ? 1 : 0); // Set flags
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n_flag = ah << 4; // Only highest bit used
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v_flag = (((ah << 4) ^ a) & 0x80) && !((a ^ byte) & 0x80);
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if (ah > 9) ah += 6; // BCD fixup for upper nybble
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c_flag = ah > 0x0f; // Set carry flag
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a = (ah << 4) | (al & 0x0f); // Compose result
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}
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}
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/*
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* Sbc instruction
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*/
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inline void MOS6510::do_sbc(uint8 byte)
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{
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uint16 tmp = a - byte - (c_flag ? 0 : 1);
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if (!d_flag) {
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// Binary mode
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c_flag = tmp < 0x100;
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v_flag = ((a ^ tmp) & 0x80) && ((a ^ byte) & 0x80);
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z_flag = n_flag = a = tmp;
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} else {
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uint16 al, ah;
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// Decimal mode
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al = (a & 0x0f) - (byte & 0x0f) - (c_flag ? 0 : 1); // Calculate lower nybble
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ah = (a >> 4) - (byte >> 4); // Calculate upper nybble
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if (al & 0x10) {
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al -= 6; // BCD fixup for lower nybble
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ah--;
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}
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if (ah & 0x10) ah -= 6; // BCD fixup for upper nybble
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c_flag = tmp < 0x100; // Set flags
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v_flag = ((a ^ tmp) & 0x80) && ((a ^ byte) & 0x80);
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z_flag = n_flag = tmp;
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a = (ah << 4) | (al & 0x0f); // Compose result
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}
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}
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/*
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* Reset CPU
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*/
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void MOS6510::Reset(void)
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{
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// Delete 'CBM80' if present
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if (ram[0x8004] == 0xc3 && ram[0x8005] == 0xc2 && ram[0x8006] == 0xcd
|
|
&& ram[0x8007] == 0x38 && ram[0x8008] == 0x30)
|
|
ram[0x8004] = 0;
|
|
|
|
// Initialize extra 6510 registers and memory configuration
|
|
ddr = pr = pr_out = 0;
|
|
new_config();
|
|
|
|
// Clear all interrupt lines
|
|
interrupt.intr_any = 0;
|
|
nmi_state = false;
|
|
|
|
// Read reset vector
|
|
pc = read_word(0xfffc);
|
|
state = 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* Illegal opcode encountered
|
|
*/
|
|
|
|
void MOS6510::illegal_op(uint8 op, uint16 at)
|
|
{
|
|
char illop_msg[80];
|
|
|
|
sprintf(illop_msg, "Illegal opcode %02x at %04x.", op, at);
|
|
ShowRequester(illop_msg, "Reset");
|
|
the_c64->Reset();
|
|
Reset();
|
|
}
|
|
|
|
|
|
/*
|
|
* Emulate one 6510 clock cycle
|
|
*/
|
|
|
|
// Read byte from memory
|
|
#define read_to(adr, to) \
|
|
if (BALow) \
|
|
return; \
|
|
to = read_byte(adr);
|
|
|
|
// Read byte from memory, throw away result
|
|
#define read_idle(adr) \
|
|
if (BALow) \
|
|
return; \
|
|
read_byte(adr);
|
|
|
|
void MOS6510::EmulateCycle(void)
|
|
{
|
|
uint8 data, tmp;
|
|
|
|
// Any pending interrupts in state 0 (opcode fetch)?
|
|
if (!state && interrupt.intr_any) {
|
|
if (interrupt.intr[INT_RESET])
|
|
Reset();
|
|
else if (interrupt.intr[INT_NMI] && (the_c64->CycleCounter-first_nmi_cycle >= 2)) {
|
|
interrupt.intr[INT_NMI] = false; // Simulate an edge-triggered input
|
|
state = 0x0010;
|
|
} else if ((interrupt.intr[INT_VICIRQ] || interrupt.intr[INT_CIAIRQ]) && (the_c64->CycleCounter-first_irq_cycle >= 2) && !i_flag)
|
|
state = 0x0008;
|
|
}
|
|
|
|
#include "CPU_emulcycle.h"
|
|
|
|
// Extension opcode
|
|
case O_EXT:
|
|
if (pc < 0xe000) {
|
|
illegal_op(0xf2, pc-1);
|
|
break;
|
|
}
|
|
switch (read_byte(pc++)) {
|
|
case 0x00:
|
|
ram[0x90] |= TheIEC->Out(ram[0x95], ram[0xa3] & 0x80);
|
|
c_flag = false;
|
|
pc = 0xedac;
|
|
Last;
|
|
case 0x01:
|
|
ram[0x90] |= TheIEC->OutATN(ram[0x95]);
|
|
c_flag = false;
|
|
pc = 0xedac;
|
|
Last;
|
|
case 0x02:
|
|
ram[0x90] |= TheIEC->OutSec(ram[0x95]);
|
|
c_flag = false;
|
|
pc = 0xedac;
|
|
Last;
|
|
case 0x03:
|
|
ram[0x90] |= TheIEC->In(a);
|
|
set_nz(a);
|
|
c_flag = false;
|
|
pc = 0xedac;
|
|
Last;
|
|
case 0x04:
|
|
TheIEC->SetATN();
|
|
pc = 0xedfb;
|
|
Last;
|
|
case 0x05:
|
|
TheIEC->RelATN();
|
|
pc = 0xedac;
|
|
Last;
|
|
case 0x06:
|
|
TheIEC->Turnaround();
|
|
pc = 0xedac;
|
|
Last;
|
|
case 0x07:
|
|
TheIEC->Release();
|
|
pc = 0xedac;
|
|
Last;
|
|
default:
|
|
illegal_op(0xf2, pc-1);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
illegal_op(op, pc-1);
|
|
break;
|
|
}
|
|
}
|