mirror of
https://github.com/autinerd/game_and_watch_emulator.git
synced 2025-12-16 07:16:26 +01:00
46 lines
1.5 KiB
Python
46 lines
1.5 KiB
Python
from .periph import Periph
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class FMC(Periph):
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BASE_ADDR = 0x5200_4000
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def __init__(self):
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self._BCR1 = 0x30DB
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self._BCR2 = 0x30D2
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self._BCR3 = 0x30D2
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self._BCR4 = 0x30D2
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self._PCR = 0x18
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self._SDCR1 = 0x2D0
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self._SDCR2 = 0x2D0
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def read_mem(self, address: int, size: int) -> int:
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if address == self.BASE_ADDR:
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return self._BCR1
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elif address == self.BASE_ADDR + 8:
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return self._BCR2
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elif address == self.BASE_ADDR + 16:
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return self._BCR3
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elif address == self.BASE_ADDR + 24:
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return self._BCR4
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elif address == self.BASE_ADDR + 0x80:
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return self._PCR
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elif address == self.BASE_ADDR + 0x140:
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return self._SDCR1
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elif address == self.BASE_ADDR + 0x144:
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return self._SDCR2
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return 0
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def write_mem(self, address: int, size: int, data: int):
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if address == self.BASE_ADDR:
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self.set_reg('_BCR1', 0x833FFB7F, data)
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elif address == self.BASE_ADDR + 8:
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self.set_reg('_BCR2', 0x833FFB7F, data)
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elif address == self.BASE_ADDR + 16:
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self.set_reg('_BCR3', 0x833FFB7F, data)
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elif address == self.BASE_ADDR + 24:
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self.set_reg('_BCR4', 0x833FFB7F, data)
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elif address == self.BASE_ADDR + 0x80:
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return self._PCR
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elif address == self.BASE_ADDR + 0x140:
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return self._SDCR1
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elif address == self.BASE_ADDR + 0x144:
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return self._SDCR2 |