mirror of
https://github.com/autinerd/game_and_watch_emulator.git
synced 2025-12-16 07:16:26 +01:00
191 lines
7.4 KiB
Python
191 lines
7.4 KiB
Python
from .periph import Periph
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from .. import consts
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from queue import Queue
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class LTDC(Periph):
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BASE_ADDR = 0x5000_1000
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def __init__(self):
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self._SSCR = 0
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self._BPCR = 0
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self._AWCR = 0
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self._TWCR = 0
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self._GCR = 0x2220
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self._SRCR = 0
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self._BCCR = 0
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self._IER = 0
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self._ISR = 0
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self._ICR = 0
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self._LIPCR = 0
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self._CPSR = 0
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self._CDSR = 0
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self._L1CR = 0
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self._L2CR = 0
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self._L1WHPCR = 0
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self._L2WHPCR = 0
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self._L1WVPCR = 0
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self._L2WVPCR = 0
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self._L1WCKCR = 0
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self._L2WCKCR = 0
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self._L1PFCR = 0
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self._L2PFCR = 0
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self._L1CACR = 0xFF
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self._L2CACR = 0xFF
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self._L1DCCR = 0
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self._L2DCCR = 0
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self._L1BFCR = 0
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self._L2BFCR = 0
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self._L1CFBAR = 0
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self._L2CFBAR = 0
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self._L1CFBLR = 0
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self._L2CFBLR = 0
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self._L1CFBLNR = 0
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self._L2CFBLNR = 0
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self._L1CLUTWR = 0
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self._L2CLUTWR = 0
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def read_mem(self, address: int, size: int) -> int:
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if address == self.BASE_ADDR + 0x8:
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return self._SSCR
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elif address == self.BASE_ADDR + 0xC:
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return self._BPCR
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elif address == self.BASE_ADDR + 0x10:
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return self._AWCR
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elif address == self.BASE_ADDR + 0x14:
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return self._TWCR
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elif address == self.BASE_ADDR + 0x18:
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return self._GCR
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elif address == self.BASE_ADDR + 0x24:
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return self._SRCR
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elif address == self.BASE_ADDR + 0x2C:
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return self._BCCR
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elif address == self.BASE_ADDR + 0x34:
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return self._IER
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elif address == self.BASE_ADDR + 0x38:
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return self._ISR
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elif address == self.BASE_ADDR + 0x3C:
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return self._ICR
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elif address == self.BASE_ADDR + 0x40:
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return self._LIPCR
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elif address == self.BASE_ADDR + 0x44:
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return self._CPSR
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elif address == self.BASE_ADDR + 0x48:
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return self._CDSR
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elif address == self.BASE_ADDR + 0x84:
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return self._L1CR
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elif address == self.BASE_ADDR + 0x104:
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return self._L2CR
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elif address == self.BASE_ADDR + 0x88:
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return self._L1WHPCR
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elif address == self.BASE_ADDR + 0x108:
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return self._L2WHPCR
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elif address == self.BASE_ADDR + 0x8C:
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return self._L1WVPCR
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elif address == self.BASE_ADDR + 0x10C:
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return self._L2WVPCR
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elif address == self.BASE_ADDR + 0x90:
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return self._L1WCKCR
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elif address == self.BASE_ADDR + 0x110:
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return self._L2WCKCR
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elif address == self.BASE_ADDR + 0x94:
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return self._L1PFCR
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elif address == self.BASE_ADDR + 0x114:
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return self._L2PFCR
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elif address == self.BASE_ADDR + 0x98:
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return self._L1CACR
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elif address == self.BASE_ADDR + 0x118:
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return self._L2CACR
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elif address == self.BASE_ADDR + 0x9C:
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return self._L1DCCR
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elif address == self.BASE_ADDR + 0x11C:
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return self._L2DCCR
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elif address == self.BASE_ADDR + 0xA0:
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return self._L1BFCR
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elif address == self.BASE_ADDR + 0x120:
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return self._L2BFCR
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elif address == self.BASE_ADDR + 0xAC:
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return self._L1CFBAR
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elif address == self.BASE_ADDR + 0x12C:
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return self._L2CFBAR
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elif address == self.BASE_ADDR + 0xB0:
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return self._L1CFBLR
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elif address == self.BASE_ADDR + 0x130:
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return self._L2CFBLR
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elif address == self.BASE_ADDR + 0xB4:
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return self._L1CFBLNR
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elif address == self.BASE_ADDR + 0x134:
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return self._L2CFBLNR
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elif address == self.BASE_ADDR + 0xC4:
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return self._L1CLUTWR
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elif address == self.BASE_ADDR + 0x144:
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return self._L2CLUTWR
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def write_mem(self, address: int, size: int, data: int):
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if address == self.BASE_ADDR + 0x8:
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self.set_reg('_SSCR', 0x0FFF_07FF, data)
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elif address == self.BASE_ADDR + 0xC:
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self.set_reg('_BPCR', 0x0FFF_07FF, data)
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elif address == self.BASE_ADDR + 0x10:
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self.set_reg('_AWCR', 0x0FFF_07FF, data)
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elif address == self.BASE_ADDR + 0x14:
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self.set_reg('_TWCR', 0x0FFF_07FF, data)
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elif address == self.BASE_ADDR + 0x18:
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self.set_reg('_GCR', 0xF001_0001, data)
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elif address == self.BASE_ADDR + 0x24:
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self.set_reg('_SRCR', 0x0000_0003, data)
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elif address == self.BASE_ADDR + 0x2C:
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self.set_reg('_BCCR', 0x00FF_FFFF, data)
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elif address == self.BASE_ADDR + 0x34:
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self.set_reg('_IER', 0x0000_000F, data)
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elif address == self.BASE_ADDR + 0x3C:
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self._ISR &= ~data & 0xF
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elif address == self.BASE_ADDR + 0x40:
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self.set_reg('_LIPCR', 0x0000_0FFF, data)
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elif address == self.BASE_ADDR + 0x84:
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self.set_reg('_L1CR', 0x0000_0013, data)
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elif address == self.BASE_ADDR + 0x104:
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self.set_reg('_L2CR', 0x0000_0013, data)
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elif address == self.BASE_ADDR + 0x88:
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self.set_reg('_L1WHPCR', 0x0FFF_0FFF, data)
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elif address == self.BASE_ADDR + 0x108:
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self.set_reg('_L2WHPCR', 0x0FFF_0FFF, data)
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elif address == self.BASE_ADDR + 0x8C:
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self.set_reg('_L1WVPCR', 0x07FF_07FF, data)
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elif address == self.BASE_ADDR + 0x10C:
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self.set_reg('_L2WVPCR', 0x07FF_07FF, data)
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elif address == self.BASE_ADDR + 0x90:
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self.set_reg('_L1WCKCR', 0x00FF_FFFF, data)
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elif address == self.BASE_ADDR + 0x110:
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self.set_reg('_L2WCKCR', 0x00FF_FFFF, data)
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elif address == self.BASE_ADDR + 0x94:
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self.set_reg('_L1PFCR', 0x0000_0007, data)
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elif address == self.BASE_ADDR + 0x114:
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self.set_reg('_L2PFCR', 0x0000_0007, data)
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elif address == self.BASE_ADDR + 0x98:
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self.set_reg('_L1CACR', 0x0000_00FF, data)
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elif address == self.BASE_ADDR + 0x118:
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self.set_reg('_L2CACR', 0x0000_00FF, data)
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elif address == self.BASE_ADDR + 0x9C:
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self.set_reg('_L1DCCR', 0xFFFF_FFFF, data)
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elif address == self.BASE_ADDR + 0x11C:
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self.set_reg('_L2DCCR', 0xFFFF_FFFF, data)
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elif address == self.BASE_ADDR + 0xA0:
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self.set_reg('_L1BFCR', 0x0000_0707, data)
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elif address == self.BASE_ADDR + 0x120:
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self.set_reg('_L2BFCR', 0x0000_0707, data)
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elif address == self.BASE_ADDR + 0xAC:
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self.set_reg('_L1CFBAR', 0xFFFF_FFFF, data)
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elif address == self.BASE_ADDR + 0x12C:
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self.set_reg('_L2CFBAR', 0xFFFF_FFFF, data)
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elif address == self.BASE_ADDR + 0xB0:
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self.set_reg('_L1CFBLR', 0x1FFF_1FFF, data)
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elif address == self.BASE_ADDR + 0x130:
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self.set_reg('_L2CFBLR', 0x1FFF_1FFF, data)
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elif address == self.BASE_ADDR + 0xB4:
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self.set_reg('_L1CFBLNR', 0x0000_07FF, data)
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elif address == self.BASE_ADDR + 0x134:
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self.set_reg('_L2CFBLNR', 0x0000_07FF, data)
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elif address == self.BASE_ADDR + 0xC4:
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self.set_reg('_L1CLUTWR', 0xFFFF_FFFF, data)
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elif address == self.BASE_ADDR + 0x144:
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self.set_reg('_L2CLUTWR', 0xFFFF_FFFF, data)
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