mirror of
https://github.com/autinerd/game_and_watch_emulator.git
synced 2025-12-16 07:16:26 +01:00
83 lines
2.9 KiB
Python
83 lines
2.9 KiB
Python
from .periph import Periph
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class SPI2(Periph):
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BASE_ADDR = 0x4000_3800
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def __init__(self):
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self._CR1 = 0
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self._CR2 = 0
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self._CFG1 = 0x7_0007
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self._CFG2 = 0
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self._IER = 0
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self._SR = 0x1002
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self._IFCR = 0
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self._TXDR = 0
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self._RXDR = 0
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self._CRCPOLY = 0x107
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self._TXCRC = 0
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self._RXCRC = 0
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self._UDRDR = 0
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self._I2SCFGR = 0
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def read_mem(self, address: int, size: int) -> int:
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if address == self.BASE_ADDR:
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return self._CR1
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elif address == self.BASE_ADDR + 4:
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return self._CR2
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elif address == self.BASE_ADDR + 8:
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return self._CFG1
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elif address == self.BASE_ADDR + 0xC:
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return self._CFG2
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elif address == self.BASE_ADDR + 0x10:
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return self._IER
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elif address == self.BASE_ADDR + 0x14:
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return self._SR
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elif address == self.BASE_ADDR + 0x18:
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return self._IFCR
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elif address == self.BASE_ADDR + 0x30:
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return self._RXDR
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elif address == self.BASE_ADDR + 0x40:
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return self._CRCPOLY
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elif address == self.BASE_ADDR + 0x44:
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return self._TXCRC
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elif address == self.BASE_ADDR + 0x48:
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return self._RXCRC
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elif address == self.BASE_ADDR + 0x4C:
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return self._UDRDR
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elif address == self.BASE_ADDR + 0x50:
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return self._I2SCFGR
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return 0
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def write_mem(self, address: int, size: int, data: int):
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if address == self.BASE_ADDR:
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self.set_reg('_CR1', 0x1_FF01, data)
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elif address == self.BASE_ADDR + 4:
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self.set_reg('_CR2', 0xFFFF_FFFF, data)
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elif address == self.BASE_ADDR + 8:
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self.set_reg('_CFG1', 0x705F_DFFF, data)
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elif address == self.BASE_ADDR + 0xC:
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self.set_reg('_CFG2', 0xF7FE_80FF, data)
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elif address == self.BASE_ADDR + 0x10:
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self.set_reg('_IER', 0x0000_0FFF, data)
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elif address == self.BASE_ADDR + 0x18:
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d = data & 0x0000_0FF8
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self._SR &= (~d & 0xFFFF_FFFF)
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elif address == self.BASE_ADDR + 0x20:
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self.set_reg('_TXDR', 0x0, data)
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if self._CR2 & 0xFFFF > 0:
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self._CR2 -= 1
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if self._CR2 & 0xFFFF == 0:
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self._SR |= 0b1000
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elif address == self.BASE_ADDR + 0x30:
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self.set_reg('_RXDR', 0x0, data)
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elif address == self.BASE_ADDR + 0x40:
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self.set_reg('_CRCPOLY', 0x0, data)
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elif address == self.BASE_ADDR + 0x44:
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self.set_reg('_TXCRC', 0x0, data)
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elif address == self.BASE_ADDR + 0x48:
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self.set_reg('_RXCRC', 0x0, data)
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elif address == self.BASE_ADDR + 0x4C:
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self.set_reg('_UDRDR', 0x0, data)
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elif address == self.BASE_ADDR + 0x50:
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self.set_reg('_I2SCFGR', 0x0, data)
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