mirror of
https://github.com/autinerd/game_and_watch_emulator.git
synced 2025-12-16 07:16:26 +01:00
50 lines
1.6 KiB
Python
50 lines
1.6 KiB
Python
from .periph import Periph
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class TIM5(Periph):
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BASE_ADDR = 0x4000_0C00
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def __init__(self):
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self._CR1 = 0
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self._DIER = 0
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self._SR = 0
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self._EGR = 0
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self._CNT = 0
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self._PSC = 0
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self._ARR = 0xFFFF_FFFF
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def read_mem(self, address: int, size: int) -> int:
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if address == self.BASE_ADDR:
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return self._CR1
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elif address == self.BASE_ADDR + 0xC:
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return self._DIER
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elif address == self.BASE_ADDR + 0x10:
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return self._SR
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elif address == self.BASE_ADDR + 0x14:
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return self._EGR
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elif address == self.BASE_ADDR + 0x24:
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return self._CNT
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elif address == self.BASE_ADDR + 0x28:
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return self._PSC
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elif address == self.BASE_ADDR + 0x2C:
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return self._ARR
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return 0
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def write_mem(self, address: int, size: int, data: int):
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if address == self.BASE_ADDR:
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self.set_reg('_CR1', 0x0BFF, data)
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elif address == self.BASE_ADDR + 0xC:
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self.set_reg('_DIER', 0x5F5F, data)
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elif address == self.BASE_ADDR + 0x10:
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self.set_reg('_SR', 0x1E5F, data)
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elif address == self.BASE_ADDR + 0x14:
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self.set_reg('_EGR', 0x005F, data)
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if self._EGR & 1:
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self._SR |= 1
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self._EGR &= ~1 & 0xFFFF_FFFF
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elif address == self.BASE_ADDR + 0x24:
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self.set_reg('_CNT', 0xFFFF_FFFF, data)
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elif address == self.BASE_ADDR + 0x28:
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self.set_reg('_PSC', 0xFFFF, data)
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elif address == self.BASE_ADDR + 0x2C:
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self.set_reg('_ARR', 0xFFFF_FFFF, data)
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