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101 lines
2.0 KiB
ArmAsm
101 lines
2.0 KiB
ArmAsm
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// this code was taken from libogc, see http://www.devkitpro.org/
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#include "asm.h"
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.extern ICFlashInvalidate
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.extern ICEnable
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.extern DCEnable
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.extern L2Init
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.extern L2Enable
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.globl __CacheInit
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__CacheInit:
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mflr r0
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stw r0, 4(sp)
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stwu sp, -16(sp)
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stw r31, 12(sp)
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mfspr r3,HID0 # (HID0)
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rlwinm r0,r3, 0, 16, 16
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cmplwi r0, 0x0000 # Check if the Instruction Cache has been enabled or not.
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bne ICEnabled
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bl ICEnable
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ICEnabled:
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mfspr r3, HID0 # bl PPCMfhid0
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rlwinm r0, r3, 0, 17, 17
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cmplwi r0, 0x0000 # Check if the Data Cache has been enabled or not.
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bne DCEnabled
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bl DCEnable
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DCEnabled:
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mfspr r3, L2CR # (L2CR)
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clrrwi r0, r3, 31 # Clear all of the bits except 31
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cmplwi r0, 0x0000
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bne L2Enabled
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bl L2Init
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bl L2Enable
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L2Enabled:
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# Restore the non-volatile registers to their previous values and return.
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lwz r0, 20(sp)
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lwz r31, 12(sp)
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addi sp, sp, 16
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mtlr r0
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blr
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.globl __SystemInit
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__SystemInit:
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mflr r0
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stw r0, 4(sp)
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stwu sp, -24(sp)
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stw r31, 20(sp)
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stw r30, 16(sp)
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stw r29, 12(sp)
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# Clear various SPR's
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li r3,0
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mtspr 952, r3
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mtspr 956, r3
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mtspr 953, r3
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mtspr 954, r3
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mtspr 957, r3
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mtspr 958, r3
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#if 0
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lis r3,0x8390 //bits set: H4A(HID4 access), SBE(2nd BAT enabled), SR0(store 0), LPE(PS LE exception), L2CFI(L2 castout prior to L2 inv. flash)
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mtspr HID4,r3
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#endif
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# Disable Speculative Bus Accesses to non-guarded space from both caches.
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mfspr r3, HID0
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ori r3, r3, 0x0200
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mtspr HID0, r3
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mfspr r3,HID2 # (HID2)
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rlwinm r3, r3, 0, 2, 0
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mtspr HID2,r3 # (HID2)
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# Restore the non-volatile registers to their previous values and return.
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lwz r0, 28(sp)
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lwz r31,20(sp)
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lwz r30,16(sp)
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lwz r29,12(sp)
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addi sp, sp, 24
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mtlr r0
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blr
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.global systemcallhandler_start,systemcallhandler_end
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systemcallhandler_start:
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mfspr r3,HID0
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ori r4,r3,0x0008
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mtspr HID0,r4
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isync
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sync
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mtspr HID0,r3
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rfi
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systemcallhandler_end:
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nop
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