mirror of
https://github.com/fail0verflow/hbc.git
synced 2024-11-19 08:09:19 +01:00
466 lines
6.6 KiB
ArmAsm
466 lines
6.6 KiB
ArmAsm
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/*-------------------------------------------------------------
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cache_asm.S -- Cache interface
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Copyright (C) 2004
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Michael Wiedenbauer (shagkur)
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Dave Murphy (WinterMute)
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This software is provided 'as-is', without any express or implied
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warranty. In no event will the authors be held liable for any
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damages arising from the use of this software.
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Permission is granted to anyone to use this software for any
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purpose, including commercial applications, and to alter it and
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redistribute it freely, subject to the following restrictions:
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1. The origin of this software must not be misrepresented; you
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must not claim that you wrote the original software. If you use
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this software in a product, an acknowledgment in the product
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documentation would be appreciated but is not required.
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2. Altered source versions must be plainly marked as such, and
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must not be misrepresented as being the original software.
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3. This notice may not be removed or altered from any source
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distribution.
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-------------------------------------------------------------*/
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#include "asm.h"
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.globl DCFlashInvalidate
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DCFlashInvalidate:
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mfspr r3,HID0
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ori r3,r3,0x0400
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mtspr HID0,r3
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blr
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.globl DCEnable
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DCEnable:
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sync
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mfspr r3,HID0
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ori r3,r3,0x4000
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mtspr HID0,r3
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blr
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/* .globl DCDisable
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DCDisable:
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sync
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mfspr r3,HID0
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rlwinm r3,r3,0,18,16
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mtspr HID0,r3
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blr
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*/
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/* .globl DCFreeze
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DCFreeze:
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sync
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mfspr r3,HID0
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ori r3,r3,0x1000
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mtspr HID0,r3
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blr
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.globl DCUnfreeze
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DCUnfreeze:
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mfspr r3,HID0
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rlwinm r3,r3,0,20,18
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mtspr HID0,r3
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blr
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.globl DCTouchLoad
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DCTouchLoad:
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dcbt r0,r3
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blr
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.globl DCBlockZero
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DCBlockZero:
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dcbz r0,r3
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blr
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.globl DCBlockStore
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DCBlockStore:
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dcbst r0,r3
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blr
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.globl DCBlockFlush
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DCBlockFlush:
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dcbf r0,r3
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blr
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.globl DCBlockInvalidate
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DCBlockInvalidate:
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dcbi r0,r3
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blr
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*/
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.globl DCInvalidateRange
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DCInvalidateRange:
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cmplwi r4, 0 # zero or negative size?
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blelr
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clrlwi. r5, r3, 27 # check for lower bits set in address
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beq 1f
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addi r4, r4, 0x20
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1:
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addi r4, r4, 0x1f
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srwi r4, r4, 5
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mtctr r4
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2:
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dcbi r0, r3
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addi r3, r3, 0x20
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bdnz 2b
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blr
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.globl DCFlushRange
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DCFlushRange:
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cmplwi r4, 0 # zero or negative size?
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blelr
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clrlwi. r5, r3, 27 # check for lower bits set in address
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beq 1f
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addi r4, r4, 0x20
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1:
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addi r4, r4, 0x1f
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srwi r4, r4, 5
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mtctr r4
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2:
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dcbf r0, r3
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addi r3, r3, 0x20
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bdnz 2b
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sc
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blr
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/* .globl DCStoreRange
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DCStoreRange:
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cmplwi r4, 0 # zero or negative size?
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blelr
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clrlwi. r5, r3, 27 # check for lower bits set in address
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beq 1f
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addi r4, r4, 0x20
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1:
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addi r4, r4, 0x1f
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srwi r4, r4, 5
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mtctr r4
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2:
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dcbst r0, r3
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addi r3, r3, 0x20
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bdnz 2b
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sc
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blr
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*/
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.globl DCFlushRangeNoSync
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DCFlushRangeNoSync:
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cmplwi r4, 0 # zero or negative size?
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blelr
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clrlwi. r5, r3, 27 # check for lower bits set in address
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beq 1f
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addi r4, r4, 0x20
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1:
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addi r4, r4, 0x1f
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srwi r4, r4, 5
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mtctr r4
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2:
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dcbf r0, r3
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addi r3, r3, 0x20
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bdnz 2b
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blr
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/* .globl DCStoreRangeNoSync
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DCStoreRangeNoSync:
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cmplwi r4, 0 # zero or negative size?
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blelr
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clrlwi. r5, r3, 27 # check for lower bits set in address
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beq 1f
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addi r4, r4, 0x20
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1:
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addi r4, r4, 0x1f
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srwi r4, r4, 5
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mtctr r4
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2:
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dcbst r0, r3
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addi r3, r3, 0x20
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bdnz 2b
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blr
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.globl DCZeroRange
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DCZeroRange:
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cmplwi r4, 0 # zero or negative size?
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blelr
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clrlwi. r5, r3, 27 # check for lower bits set in address
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beq 1f
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addi r4, r4, 0x20
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1:
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addi r4, r4, 0x1f
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srwi r4, r4, 5
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mtctr r4
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2:
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dcbz r0, r3
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addi r3, r3, 0x20
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bdnz 2b
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blr
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.globl DCTouchRange
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DCTouchRange:
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cmplwi r4, 0 # zero or negative size?
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blelr
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clrlwi. r5, r3, 27 # check for lower bits set in address
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beq 1f
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addi r4, r4, 0x20
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1:
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addi r4, r4, 0x1f
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srwi r4, r4, 5
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mtctr r4
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2:
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dcbt r0, r3
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addi r3, r3, 0x20
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bdnz 2b
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blr
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*/
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.globl ICInvalidateRange
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ICInvalidateRange:
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cmplwi r4, 0 # zero or negative size?
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blelr
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clrlwi. r5, r3, 27 # check for lower bits set in address
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beq 1f
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addi r4, r4, 0x20
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1:
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addi r4, r4, 0x1f
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srwi r4, r4, 5
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mtctr r4
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2:
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icbi r0, r3
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addi r3, r3, 0x20
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bdnz 2b
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sync
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isync
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blr
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.globl ICFlashInvalidate
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ICFlashInvalidate:
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mfspr r3,HID0
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ori r3,r3,0x0800
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mtspr HID0,r3
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blr
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.globl ICEnable
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ICEnable:
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isync
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mfspr r3,HID0
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ori r3,r3,0x8000
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mtspr HID0,r3
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blr
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.globl ICDisable
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ICDisable:
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isync
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mfspr r3,HID0
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rlwinm r3,r3,0,17,15
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mtspr HID0,r3
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blr
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/* .globl ICFreeze
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ICFreeze:
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isync
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mfspr r3,HID0
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ori r3,r3,0x2000
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mtspr HID0,r3
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blr
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.globl ICUnfreeze
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ICUnfreeze:
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mfspr r3,HID0
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rlwinm r3,r3,0,19,17
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mtspr HID0,r3
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blr
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.globl ICBlockInvalidate
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ICBlockInvalidate:
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icbi r0,r3
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blr
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*/
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.globl ICSync
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ICSync:
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isync
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blr
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.globl L2Init
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L2Init:
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mflr r0
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stw r0,4(sp)
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stwu sp,-16(sp)
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stw r31,12(sp)
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mfmsr r3
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mr r31,r3
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sync
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li r3,48
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mtmsr r3
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sync
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bl L2Disable
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bl L2GlobalInvalidate
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mr r3,r31
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mtmsr r3
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lwz r0,20(sp)
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lwz r31,12(sp)
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mtlr r0
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blr
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.globl L2Enable
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L2Enable:
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mfspr r3,L2CR;
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oris r0,r3,0x8000
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rlwinm r3,r0,0,11,9
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mtspr L2CR,r3
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blr
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.globl L2Disable
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L2Disable:
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sync
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mfspr r3,L2CR
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clrlwi r3,r3,1
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mtspr L2CR,r3
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sync
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blr
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.globl L2GlobalInvalidate
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L2GlobalInvalidate:
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mflr r0
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stw r0,4(sp)
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stwu sp,-8(sp)
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bl L2Disable
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mfspr r3,L2CR
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oris r3,r3,0x0020
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mtspr L2CR,r3
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1: mfspr r3,L2CR
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clrlwi r0,r3,31
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cmplwi r0,0x0000
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bne 1b
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mfspr r3,L2CR
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rlwinm r3,r3,0,11,9
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mtspr L2CR,r3
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2: mfspr r3,L2CR
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clrlwi r0,r3,31
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cmplwi r0,0x0000
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bne 2b
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lwz r0,12(sp)
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addi sp,sp,8
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mtlr r0
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blr
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/* .globl __LCEnable
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__LCEnable:
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mfmsr r5
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ori r5,r5,0x1000
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mtmsr r5
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lis r3,0x8000
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li r4,1024
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mtctr r4
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1: dcbt r0,r3
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dcbst r0,r3
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bdnz 1b
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mfspr r4,HID2
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oris r4,r4,0x100f
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mtspr HID2,r4
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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lis r3,0xe000
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ori r3,r3,0x0002
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mtspr DBAT3L,r3
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ori r3,r3,0x01fe
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mtspr DBAT3U,r3
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isync
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lis r3,0xe000
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li r6,512
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mtctr r6
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li r6,0
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2: dcbz_l r6,r3
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addi r3,r3,32
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bdnz 2b
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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blr
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.globl LCDisable
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LCDisable:
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lis r3,0xe000
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li r4,512
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mtctr r4
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1: dcbi r0,r3
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addi r3,r3,32
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bdnz 1b
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mfspr r4,HID2
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rlwinm r4,r4,0,4,2
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mtspr HID2,r4
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blr
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.globl LCAllocOneTag
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LCAllocOneTag:
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cmpwi r3,0
|
||
|
|
beq 1f
|
||
|
|
dcbi r0,r4
|
||
|
|
1: dcbz_l r0,r4
|
||
|
|
blr
|
||
|
|
|
||
|
|
.globl LCAllocTags
|
||
|
|
LCAllocTags:
|
||
|
|
mflr r6
|
||
|
|
cmplwi r5,0
|
||
|
|
ble 2f
|
||
|
|
mtctr r5
|
||
|
|
cmpwi r3,0
|
||
|
|
beq 3f
|
||
|
|
1: dcbi r0,r4
|
||
|
|
dcbz_l r0,r4
|
||
|
|
addi r4,r4,32
|
||
|
|
bdnz 1b
|
||
|
|
b 2f
|
||
|
|
3: dcbz_l r0,r4
|
||
|
|
addi r4,r4,32
|
||
|
|
bdnz 3b
|
||
|
|
2: mtlr r6
|
||
|
|
blr
|
||
|
|
|
||
|
|
.globl LCLoadBlocks
|
||
|
|
LCLoadBlocks:
|
||
|
|
extrwi r6,r5,5,25
|
||
|
|
clrlwi r4,r4,4
|
||
|
|
or r6,r6,r4
|
||
|
|
mtspr DMAU,r6
|
||
|
|
clrlslwi r6,r5,30,2
|
||
|
|
or r6,r6,r3
|
||
|
|
ori r6,r6,0x0012
|
||
|
|
mtspr DMAL,r6
|
||
|
|
blr
|
||
|
|
|
||
|
|
.globl LCStoreBlocks
|
||
|
|
LCStoreBlocks:
|
||
|
|
extrwi r6,r5,5,25
|
||
|
|
clrlwi r4,r4,4
|
||
|
|
or r6,r6,r3
|
||
|
|
mtspr DMAU,r6
|
||
|
|
clrlslwi r6,r5,30,2
|
||
|
|
or r6,r6,r4
|
||
|
|
ori r6,r6,0x0002
|
||
|
|
mtspr DMAL,r6
|
||
|
|
blr
|
||
|
|
|
||
|
|
*/
|