mirror of
https://github.com/fail0verflow/hbc.git
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331 lines
6.1 KiB
ArmAsm
331 lines
6.1 KiB
ArmAsm
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# crt0.s file for the GameCube V1.0 by Costis (costis@gbaemu.com)!
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.text
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.section .start,"ax",@progbits
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.extern _start
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.align 2
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.globl _start
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_start:
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lis 3,__mem1_start@h
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ori 3,3,__mem1_start@l
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lis 4,__mem2_start@h
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ori 4,4,__mem2_start@l
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lis 5,__self_end@h
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ori 5,5,__self_end@l
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_reloc_loop:
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lwz 2,0(3)
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stw 2,0(4)
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addi 3,3,4
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addi 4,4,4
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cmplw 4,5
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blt _reloc_loop
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lis 4,__mem2_start@h
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ori 4,4,__mem2_start@l
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_flush_loop:
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dcbst 0,4
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sync
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icbi 0,4
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addi 4,4,32
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cmplw 4,5
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blt _flush_loop
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sync
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isync
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lis 3,_mem2_entry@h
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ori 3,3,_mem2_entry@l
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mtctr 3
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bctr
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_mem2_entry:
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# Clear all GPRs except
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.irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
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li \i,0
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.endr
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lis 1,_stack_bot@h
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ori 1,1,_stack_bot@l
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stwu 0,-64(1)
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lis 2,0x8000
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stw 1,0x34(2) # write sp
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# lis 13,_SDA_BASE_@h
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# ori 13,13,_SDA_BASE_@l # Set the Small Data (Read\Write) base register.
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bl InitHardware # Initialize the GameCube Hardware (Floating Point Registers, Caches, etc.)
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bl SystemInit # Initialize more cache aspects, clear a few SPR's, and disable interrupts.
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# clear BSS
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lis 3, __bss_start@h
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ori 3, 3, __bss_start@l
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li 4, 0
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lis 5, __bss_end@h
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ori 5, 5, __bss_end@l
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sub 5, 5, 3
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bl memset
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mr 3, 28
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bl stubmain # Branch to the user code!
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b .
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InitHardware:
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mflr 31 # Store the link register in r31
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bl PSInit # Initialize Paired Singles
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bl FPRInit # Initialize the FPR's
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bl CacheInit # Initialize the system caches
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mtlr 31 # Retreive the link register from r31
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blr
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PSInit:
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mfspr 3, 920 # (HID2)
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oris 3, 3, 0xA000
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mtspr 920, 3 # (HID2)
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# Set the Instruction Cache invalidation bit in HID0
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mfspr 3,1008
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ori 3,3,0x0800
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mtspr 1008,3
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sync
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# Clear various Special Purpose Registers
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li 3,0
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mtspr 912,3
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mtspr 913,3
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mtspr 914,3
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mtspr 915,3
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mtspr 916,3
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mtspr 917,3
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mtspr 918,3
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mtspr 919,3
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# Return
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blr
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FPRInit:
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# Enable the Floating Point Registers
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mfmsr 3
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ori 3,3,0x2000
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mtmsr 3
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# Clear all of the FPR's to 0
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lis 3, zfloat@h
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ori 3, 3, zfloat@l
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lfd 0, 0(3)
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fmr 1,0
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fmr 2,0
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fmr 3,0
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fmr 4,0
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fmr 5,0
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fmr 6,0
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fmr 7,0
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fmr 8,0
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fmr 9,0
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fmr 10,0
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fmr 11,0
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fmr 12,0
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fmr 13,0
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fmr 14,0
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fmr 15,0
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fmr 16,0
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fmr 17,0
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fmr 18,0
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fmr 19,0
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fmr 20,0
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fmr 21,0
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fmr 22,0
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fmr 23,0
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fmr 24,0
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fmr 25,0
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fmr 26,0
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fmr 27,0
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fmr 28,0
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fmr 29,0
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fmr 30,0
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fmr 31,0
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mtfsf 255,0
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# Return
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blr
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CacheInit:
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mflr 0
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stw 0, 4(1)
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stwu 1, -16(1)
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stw 31, 12(1)
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stw 30, 8(1)
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mfspr 3,1008 # (HID0)
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rlwinm 0, 3, 0, 16, 16
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cmplwi 0, 0x0000 # Check if the Instruction Cache has been enabled or not.
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bne ICEnabled
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# If not, then enable it.
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isync
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mfspr 3, 1008
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ori 3, 3, 0x8000
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mtspr 1008, 3
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ICEnabled:
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mfspr 3, 1008 # bl PPCMfhid0
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rlwinm 0, 3, 0, 17, 17
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cmplwi 0, 0x0000 # Check if the Data Cache has been enabled or not.
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bne DCEnabled
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# If not, then enable it.
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sync
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mfspr 3, 1008
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ori 3, 3, 0x4000
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mtspr 1008, 3
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DCEnabled:
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mfspr 3, 1017 # (L2CR)
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clrrwi 0, 3, 31 # Clear all of the bits except 31
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cmplwi 0, 0x0000
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bne L2GISkip # Skip the L2 Global Cache Invalidation process if it has already been done befor.
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# Store the current state of the MSR in r30
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mfmsr 3
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mr 30,3
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sync
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# Enable Instruction and Data Address Translation
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li 3, 48
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mtmsr 3
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sync
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sync
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# Disable the L2 Global Cache.
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mfspr 3, 1017 # (L2CR
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clrlwi 3, 3, 1
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mtspr 1017, 3 # (L2CR)
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sync
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# Invalidate the L2 Global Cache.
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bl L2GlobalInvalidate
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# Restore the previous state of the MSR from r30
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mr 3, 30
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mtmsr 3
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# Enable the L2 Global Cache and disable the L2 Data Only bit and the L2 Global Invalidate Bit.
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mfspr 3, 1017 # (L2CR)
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oris 0, 3, 0x8000
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rlwinm 3, 0, 0, 11, 9
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mtspr 1017, 3 # (L2CR)
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L2GISkip:
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# Restore the non-volatile registers to their previous values and return.
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lwz 0, 20(1)
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lwz 31, 12(1)
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lwz 30, 8(1)
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addi 1, 1, 16
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mtlr 0
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blr
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L2GlobalInvalidate:
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mflr 0
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stw 0, 4(1)
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stwu 1, -16(1)
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stw 31, 12(1)
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sync
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# Disable the L2 Cache.
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mfspr 3, 1017 # bl PPCMf1017
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clrlwi 3, 3, 1
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mtspr 1017, 3 # bl PPCMt1017
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sync
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# Initiate the L2 Cache Global Invalidation process.
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mfspr 3, 1017 # (L2CR)
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oris 3, 3, 0x0020
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mtspr 1017, 3 # (L2CR)
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# Wait until the L2 Cache Global Invalidation has been completed.
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L2GICheckComplete:
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mfspr 3, 1017 # (L2CR)
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clrlwi 0, 3, 31
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cmplwi 0, 0x0000
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bne L2GICheckComplete
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# Clear the L2 Data Only bit and the L2 Global Invalidate Bit.
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mfspr 3, 1017 # (L2CR)
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rlwinm 3, 3, 0, 11, 9
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mtspr 1017, 3 # (L2CR)
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# Wait until the L2 Cache Global Invalidation status bit signifies that it is ready.
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L2GDICheckComplete:
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mfspr 3, 1017 # (L2CR)
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clrlwi 0, 3, 31
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cmplwi 0, 0x0000
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bne L2GDICheckComplete
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# Restore the non-volatile registers to their previous values and return.
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lwz 0, 20(1)
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lwz 31, 12(1)
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addi 1, 1, 16
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mtlr 0
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blr
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SystemInit:
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mflr 0
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stw 0, 4(1)
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stwu 1, -0x18(1)
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stw 31, 0x14(1)
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stw 30, 0x10(1)
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stw 29, 0xC(1)
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# Disable interrupts!
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mfmsr 3
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rlwinm 4,3,0,17,15
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rlwinm 4,4,0,26,24
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mtmsr 4
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# Clear various SPR's
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li 3,0
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mtspr 952, 3
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mtspr 956, 3
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mtspr 953, 3
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mtspr 954, 3
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mtspr 957, 3
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mtspr 958, 3
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# Disable Speculative Bus Accesses to non-guarded space from both caches.
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mfspr 3, 1008 # (HID0)
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ori 3, 3, 0x0200
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mtspr 1008, 3
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# Set the Non-IEEE mode in the FPSCR
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mtfsb1 29
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mfspr 3,920 # (HID2)
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rlwinm 3, 3, 0, 2, 0
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mtspr 920,3 # (HID2)
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# Restore the non-volatile registers to their previous values and return.
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lwz 0, 0x1C(1)
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lwz 31, 0x14(1)
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lwz 30, 0x10(1)
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lwz 29, 0xC(1)
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addi 1, 1, 0x18
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mtlr 0
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blr
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zfloat:
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.float 0
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.align 4
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_got_start:
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