mirror of
https://github.com/fail0verflow/hbc.git
synced 2024-09-29 09:48:36 +02:00
102 lines
2.8 KiB
ArmAsm
102 lines
2.8 KiB
ArmAsm
#define IBAT0U 528
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#define IBAT0L 529
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#define IBAT1U 530
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#define IBAT1L 531
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#define IBAT2U 532
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#define IBAT2L 533
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#define IBAT3U 534
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#define IBAT3L 535
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#define IBAT4U 560
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#define IBAT4L 561
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#define IBAT5U 562
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#define IBAT5L 563
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#define IBAT6U 564
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#define IBAT6L 565
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#define IBAT7U 566
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#define IBAT7L 567
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#define DBAT0U 536
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#define DBAT0L 537
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#define DBAT1U 538
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#define DBAT1L 539
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#define DBAT2U 540
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#define DBAT2L 541
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#define DBAT3U 542
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#define DBAT3L 543
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#define DBAT4U 568
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#define DBAT4L 569
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#define DBAT5U 570
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#define DBAT5L 571
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#define DBAT6U 572
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#define DBAT6L 573
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#define DBAT7U 574
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#define DBAT7L 575
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.text
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.section .realmode,"ax",@progbits
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.extern _start
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.align 2
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.globl _realmode_vector
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_realmode_vector:
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// HID0 = 00110c64:
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// bus checkstops off, sleep modes off,
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// caches off, caches invalidate,
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// store gathering off, enable data cache
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// flush assist, enable branch target cache,
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// enable branch history table
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lis 3,0x0011 ; ori 3,3,0x0c64 ; mtspr 1008,3 ; isync
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// MSR = 00002000 (FP on)
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li 4,0x2000 ; mtmsr 4
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// HID0 |= 0000c000 (caches on)
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ori 3,3,0xc000 ; mtspr 1008,3 ; isync
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// clear all BATs
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li 0,0
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mtspr 528,0 ; mtspr 530,0 ; mtspr 532,0 ; mtspr 534,0 // IBATU 0..3
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mtspr 536,0 ; mtspr 538,0 ; mtspr 540,0 ; mtspr 542,0 // DBATU 0..3
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mtspr 560,0 ; mtspr 562,0 ; mtspr 564,0 ; mtspr 566,0 // IBATU 4..7
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mtspr 568,0 ; mtspr 570,0 ; mtspr 572,0 ; mtspr 574,0 // DBATU 4..7
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isync
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// clear all SRs
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lis 0,0x8000
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mtsr 0,0 ; mtsr 1,0 ; mtsr 2,0 ; mtsr 3,0
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mtsr 4,0 ; mtsr 5,0 ; mtsr 6,0 ; mtsr 7,0
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mtsr 8,0 ; mtsr 9,0 ; mtsr 10,0 ; mtsr 11,0
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mtsr 12,0 ; mtsr 13,0 ; mtsr 14,0 ; mtsr 15,0
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isync
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// set [DI]BAT0 for 256MB@80000000,
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// real 00000000, WIMG=0000, R/W
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li 3,2 ; lis 4,0x8000 ; ori 4,4,0x1fff
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mtspr IBAT0L,3 ; mtspr IBAT0U,4 ; mtspr DBAT0L,3 ; mtspr DBAT0U,4 ; isync
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// set [DI]BAT4 for 256MB@90000000,
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// real 10000000, WIMG=0000, R/W
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addis 3,3,0x1000 ; addis 4,4,0x1000
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mtspr IBAT4L,3 ; mtspr IBAT4U,4 ; mtspr DBAT4L,3 ; mtspr DBAT4U,4 ; isync
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// set DBAT1 for 256MB@c0000000,
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// real 00000000, WIMG=0101, R/W
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li 3,0x2a ; lis 4,0xc000 ; ori 4,4,0x1fff
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mtspr DBAT1L,3 ; mtspr DBAT1U,4 ; isync
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// set DBAT5 for 256MB@d0000000,
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// real 10000000, WIMG=0101, R/W
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addis 3,3,0x1000 ; addis 4,4,0x1000
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mtspr DBAT5L,3 ; mtspr DBAT5U,4 ; isync
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// enable [DI]BAT4-7 in HID4
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lis 3, 0x8200
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mtspr 1011,3
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// set MSR[DR:IR] = 11, jump to _start
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lis 3,__mem1_entry@h ; ori 3,3,__mem1_entry@l ; mtsrr0 3
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mfmsr 3 ; ori 3,3,0x30 ; mtsrr1 3
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rfi
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