mirror of
https://github.com/isfshax/isfshax.git
synced 2024-11-08 20:55:09 +01:00
339 lines
15 KiB
C
339 lines
15 KiB
C
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/*
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* minute - a port of the "mini" IOS replacement for the Wii U.
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*
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* Copyright (C) 2016 SALT
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* Copyright (C) 2016 Daz Jones <daz@dazzozo.com>
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*
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* This code is licensed to you under the terms of the GNU GPL, version 2;
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* see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
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*/
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#ifndef _LATTE_H
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#define _LATTE_H
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/*
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* Latte registers.
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* http://wiiubrew.org/wiki/Hardware/Latte_Registers
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*/
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#define LT_REG_BASE (0x0D800000)
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#define LT_IPC_PPCMSG_COMPAT (LT_REG_BASE + 0x000)
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#define LT_IPC_PPCCTRL_COMPAT (LT_REG_BASE + 0x004)
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#define LT_IPC_ARMMSG_COMPAT (LT_REG_BASE + 0x008)
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#define LT_IPC_ARMCTRL_COMPAT (LT_REG_BASE + 0x00C)
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#define LT_TIMER (LT_REG_BASE + 0x010)
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#define LT_ALARM (LT_REG_BASE + 0x014)
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#define LT_INTSR_PPC_COMPAT (LT_REG_BASE + 0x030)
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#define LT_INTMR_PPC_COMPAT (LT_REG_BASE + 0x034)
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#define LT_INTSR_ARM_COMPAT (LT_REG_BASE + 0x038)
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#define LT_INTMR_ARM_COMPAT (LT_REG_BASE + 0x03C)
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#define LT_INTMR_ARM2X_COMPAT (LT_REG_BASE + 0x040)
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#define LT_UNK044 (LT_REG_BASE + 0x044)
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#define LT_AHB_WDG_STATUS (LT_REG_BASE + 0x048)
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#define LT_AHB_WDG_CONFIG (LT_REG_BASE + 0x04C)
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#define LT_AHB_DMA_STATUS (LT_REG_BASE + 0x050)
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#define LT_AHB_CPU_STATUS (LT_REG_BASE + 0x054)
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#define LT_ERROR (LT_REG_BASE + 0x058)
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#define LT_ERROR_MASK (LT_REG_BASE + 0x05C)
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#define LT_MEMIRR (LT_REG_BASE + 0x060)
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#define LT_AHBPROT (LT_REG_BASE + 0x064)
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#define LT_UNK068 (LT_REG_BASE + 0x068)
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#define LT_UNK06C (LT_REG_BASE + 0x06C)
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#define LT_EXICTRL (LT_REG_BASE + 0x070)
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#define LT_UNK074 (LT_REG_BASE + 0x074)
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#define LT_UNK088 (LT_REG_BASE + 0x088)
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#define LT_GPIOE_OUT (LT_REG_BASE + 0x0C0)
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#define LT_GPIOE_DIR (LT_REG_BASE + 0x0C4)
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#define LT_GPIOE_IN (LT_REG_BASE + 0x0C8)
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#define LT_GPIOE_INTLVL (LT_REG_BASE + 0x0CC)
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#define LT_GPIOE_INTFLAG (LT_REG_BASE + 0x0D0)
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#define LT_GPIOE_INTMASK (LT_REG_BASE + 0x0D4)
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#define LT_GPIOE_INMIR (LT_REG_BASE + 0x0D8)
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#define LT_GPIO_ENABLE (LT_REG_BASE + 0x0DC)
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#define LT_GPIO_OUT (LT_REG_BASE + 0x0E0)
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#define LT_GPIO_DIR (LT_REG_BASE + 0x0E4)
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#define LT_GPIO_IN (LT_REG_BASE + 0x0E8)
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#define LT_GPIO_INTLVL (LT_REG_BASE + 0x0EC)
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#define LT_GPIO_INTFLAG (LT_REG_BASE + 0x0F0)
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#define LT_GPIO_INTMASK (LT_REG_BASE + 0x0F4)
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#define LT_GPIO_INMIR (LT_REG_BASE + 0x0F8)
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#define LT_GPIO_OWNER (LT_REG_BASE + 0x0FC)
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#define LT_AHB_UNK100 (LT_REG_BASE + 0x100)
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#define LT_AHB_UNK104 (LT_REG_BASE + 0x104)
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#define LT_AHB_UNK108 (LT_REG_BASE + 0x108)
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#define LT_AHB_UNK10C (LT_REG_BASE + 0x10C)
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#define LT_AHB_UNK110 (LT_REG_BASE + 0x110)
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#define LT_AHB_UNK114 (LT_REG_BASE + 0x114)
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#define LT_AHB_UNK118 (LT_REG_BASE + 0x118)
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#define LT_AHB_UNK11C (LT_REG_BASE + 0x11C)
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#define LT_AHB_UNK120 (LT_REG_BASE + 0x120)
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#define LT_AHB_UNK124 (LT_REG_BASE + 0x124)
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#define LT_AHB_UNK130 (LT_REG_BASE + 0x130)
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#define LT_AHB_UNK134 (LT_REG_BASE + 0x134)
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#define LT_AHB_UNK138 (LT_REG_BASE + 0x138)
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#define LT_ARB_CFG (LT_REG_BASE + 0x140)
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#define LT_DIFLAGS (LT_REG_BASE + 0x180)
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#define LT_RESETS_AHB (LT_REG_BASE + 0x184)
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#define LT_COMPAT_MEMCTRL_WORKAROUND (LT_REG_BASE + 0x188)
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#define LT_BOOT0 (LT_REG_BASE + 0x18C)
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#define LT_CLOCKINFO (LT_REG_BASE + 0x190)
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#define LT_RESETS_COMPAT (LT_REG_BASE + 0x194)
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#define LT_CLOCKGATE_COMPAT (LT_REG_BASE + 0x198)
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#define LT_SATA_UNK1A8 (LT_REG_BASE + 0x1A8)
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#define LT_SATA_UNK1C8 (LT_REG_BASE + 0x1C8)
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#define LT_SATA_UNK1CC (LT_REG_BASE + 0x1CC)
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#define LT_SATA_UNK1D0 (LT_REG_BASE + 0x1D0)
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#define LT_UNK1D8 (LT_REG_BASE + 0x1D8)
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#define LT_IOPOWER (LT_REG_BASE + 0x1DC)
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#define LT_IOSTRENGTH_CTRL0 (LT_REG_BASE + 0x1E0)
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#define LT_IOSTRENGTH_CTRL1 (LT_REG_BASE + 0x1E4)
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#define LT_ACRCLK_STRENGTH_CTRL (LT_REG_BASE + 0x1E8)
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#define LT_OTPCMD (LT_REG_BASE + 0x1EC)
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#define LT_OTPDATA (LT_REG_BASE + 0x1F0)
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#define LT_UNK204 (LT_REG_BASE + 0x204)
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#define LT_ASICREV_ACR (LT_REG_BASE + 0x214)
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#define LT_UNK224 (LT_REG_BASE + 0x224)
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#define LT_UNK250 (LT_REG_BASE + 0x250)
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#define LT_UNK254 (LT_REG_BASE + 0x254)
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#define LT_UNK258 (LT_REG_BASE + 0x258)
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#define LT_IPC_PPC0_PPCMSG (LT_REG_BASE + 0x400)
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#define LT_IPC_PPC0_PPCCTRL (LT_REG_BASE + 0x404)
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#define LT_IPC_PPC0_ARMMSG (LT_REG_BASE + 0x408)
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#define LT_IPC_PPC0_ARMCTRL (LT_REG_BASE + 0x40C)
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#define LT_IPC_PPC1_PPCMSG (LT_REG_BASE + 0x410)
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#define LT_IPC_PPC1_PPCCTRL (LT_REG_BASE + 0x414)
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#define LT_IPC_PPC1_ARMMSG (LT_REG_BASE + 0x418)
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#define LT_IPC_PPC1_ARMCTRL (LT_REG_BASE + 0x41C)
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#define LT_IPC_PPC2_PPCMSG (LT_REG_BASE + 0x420)
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#define LT_IPC_PPC2_PPCCTRL (LT_REG_BASE + 0x424)
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#define LT_IPC_PPC2_ARMMSG (LT_REG_BASE + 0x428)
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#define LT_IPC_PPC2_ARMCTRL (LT_REG_BASE + 0x42C)
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#define LT_INTSR_AHBALL_PPC0 (LT_REG_BASE + 0x440)
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#define LT_INTSR_AHBLT_PPC0 (LT_REG_BASE + 0x444)
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#define LT_INTMR_AHBALL_PPC0 (LT_REG_BASE + 0x448)
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#define LT_INTMR_AHBLT_PPC0 (LT_REG_BASE + 0x44C)
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#define LT_INTSR_AHBALL_PPC1 (LT_REG_BASE + 0x450)
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#define LT_INTSR_AHBLT_PPC1 (LT_REG_BASE + 0x454)
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#define LT_INTMR_AHBALL_PPC1 (LT_REG_BASE + 0x458)
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#define LT_INTMR_AHBLT_PPC1 (LT_REG_BASE + 0x45C)
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#define LT_INTSR_AHBALL_PPC2 (LT_REG_BASE + 0x460)
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#define LT_INTSR_AHBLT_PPC2 (LT_REG_BASE + 0x464)
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#define LT_INTMR_AHBALL_PPC2 (LT_REG_BASE + 0x468)
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#define LT_INTMR_AHBLT_PPC2 (LT_REG_BASE + 0x46C)
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#define LT_INTSR_AHBALL_ARM (LT_REG_BASE + 0x470)
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#define LT_INTSR_AHBLT_ARM (LT_REG_BASE + 0x474)
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#define LT_INTMR_AHBALL_ARM (LT_REG_BASE + 0x478)
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#define LT_INTMR_AHBLT_ARM (LT_REG_BASE + 0x47C)
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#define LT_INTMR_AHBALL_ARM2X (LT_REG_BASE + 0x480)
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#define LT_INTMR_AHBLT_ARM2X (LT_REG_BASE + 0x484)
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#define LT_AHB2_WDG_STATUS (LT_REG_BASE + 0x4A0)
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#define LT_AHB2_DMA_STATUS (LT_REG_BASE + 0x4A4)
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#define LT_AHB2_CPU_STATUS (LT_REG_BASE + 0x4A8)
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#define LT_UNK4C8 (LT_REG_BASE + 0x4C8)
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#define LT_UNK4CC (LT_REG_BASE + 0x4CC)
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#define LT_UNK4D0 (LT_REG_BASE + 0x4D0)
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#define LT_UNK4D4 (LT_REG_BASE + 0x4D4)
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#define LT_UNK4DC (LT_REG_BASE + 0x4DC)
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#define LT_UNK4E0 (LT_REG_BASE + 0x4E0)
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#define LT_UNK4E4 (LT_REG_BASE + 0x4E4)
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#define LT_UNK500 (LT_REG_BASE + 0x500)
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#define LT_UNK504 (LT_REG_BASE + 0x504)
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#define LT_OTPPROT (LT_REG_BASE + 0x510)
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#define LT_SYSPROT (LT_REG_BASE + 0x514)
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#define LT_GPIOE2_OUT (LT_REG_BASE + 0x520)
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#define LT_GPIOE2_DIR (LT_REG_BASE + 0x524)
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#define LT_GPIOE2_IN (LT_REG_BASE + 0x528)
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#define LT_GPIOE2_INTLVL (LT_REG_BASE + 0x52C)
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#define LT_GPIOE2_INTFLAG (LT_REG_BASE + 0x530)
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#define LT_GPIOE2_INTMASK (LT_REG_BASE + 0x534)
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#define LT_GPIOE2_INMIR (LT_REG_BASE + 0x538)
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#define LT_GPIO2_ENABLE (LT_REG_BASE + 0x53C)
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#define LT_GPIO2_OUT (LT_REG_BASE + 0x540)
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#define LT_GPIO2_DIR (LT_REG_BASE + 0x544)
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#define LT_GPIO2_IN (LT_REG_BASE + 0x548)
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#define LT_GPIO2_INTLVL (LT_REG_BASE + 0x54C)
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#define LT_GPIO2_INTFLAG (LT_REG_BASE + 0x550)
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#define LT_GPIO2_INTMASK (LT_REG_BASE + 0x554)
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#define LT_GPIO2_INMIR (LT_REG_BASE + 0x558)
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#define LT_GPIO2_OWNER (LT_REG_BASE + 0x55C)
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#define LT_I2C_CLOCK (LT_REG_BASE + 0x570)
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#define LT_I2C_INOUT_DATA (LT_REG_BASE + 0x574)
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#define LT_I2C_INOUT_CTRL (LT_REG_BASE + 0x578)
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#define LT_I2C_INOUT_SIZE (LT_REG_BASE + 0x57C)
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#define LT_I2C_INT_MASK (LT_REG_BASE + 0x580)
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#define LT_I2C_INT_STATE (LT_REG_BASE + 0x584)
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#define LT_ASICREV_CCR (LT_REG_BASE + 0x5A0)
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#define LT_DEBUG (LT_REG_BASE + 0x5A4)
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#define LT_COMPAT_MEMCTRL_STATE (LT_REG_BASE + 0x5B0)
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#define LT_COMPAT_AHB_STATE (LT_REG_BASE + 0x5B4)
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#define LT_COMPAT_STEREO_OUT_SELECT (LT_REG_BASE + 0x5B8)
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#define LT_IOP2X (LT_REG_BASE + 0x5BC)
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#define LT_UNK5C0 (LT_REG_BASE + 0x5C0)
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#define LT_IOSTRENGTH_CTRL2 (LT_REG_BASE + 0x5C8)
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#define LT_UNK5CC (LT_REG_BASE + 0x5CC)
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#define LT_RESETS (LT_REG_BASE + 0x5E0)
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#define LT_RESETS_AHMN (LT_REG_BASE + 0x5E4)
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#define LT_CLOCKGATE (LT_REG_BASE + 0x5E8)
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#define LT_SYSPLL_CFG (LT_REG_BASE + 0x5EC)
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#define LT_ABIF_CPLTL_OFFSET (LT_REG_BASE + 0x620)
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#define LT_ABIF_CPLTL_DATA (LT_REG_BASE + 0x624)
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#define LT_UNK628 (LT_REG_BASE + 0x628)
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#define LT_60XE_CFG (LT_REG_BASE + 0x640)
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#define LT_UNK660 (LT_REG_BASE + 0x660)
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#define LT_UNK640 (LT_REG_BASE + 0x640)
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#define LT_DCCMPT (LT_REG_BASE + 0x708)
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/*
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* NAND registers.
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* http://wiiubrew.org/wiki/Hardware/NAND_Interface
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*/
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#define NAND_REG_BASE (0x0D010000)
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#define NAND_CTRL (NAND_REG_BASE + 0x000)
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#define NAND_CONF (NAND_REG_BASE + 0x004)
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#define NAND_ADDR0 (NAND_REG_BASE + 0x008)
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#define NAND_ADDR1 (NAND_REG_BASE + 0x00C)
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#define NAND_DATA (NAND_REG_BASE + 0x010)
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#define NAND_ECC (NAND_REG_BASE + 0x014)
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#define NAND_BANK (NAND_REG_BASE + 0x018)
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#define NAND_UNK1 (NAND_REG_BASE + 0x01C)
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#define NAND_BANK_CTRL (NAND_REG_BASE + 0x030)
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#define NAND_UNK3 (NAND_REG_BASE + 0x040)
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/*
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* AES registers.
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* http://wiiubrew.org/wiki/Hardware/AES_Engine
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*/
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#define AES_REG_BASE (0x0D020000)
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#define AES_CTRL (AES_REG_BASE + 0x000)
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#define AES_SRC (AES_REG_BASE + 0x004)
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#define AES_DEST (AES_REG_BASE + 0x008)
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#define AES_KEY (AES_REG_BASE + 0x00C)
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#define AES_IV (AES_REG_BASE + 0x010)
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/*
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* SHA-1 registers.
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* http://wiiubrew.org/wiki/Hardware/SHA-1_Engine
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*/
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#define SHA_REG_BASE (0x0D030000)
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#define SHA_CTRL (SHA_REG_BASE + 0x000)
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#define SHA_SRC (SHA_REG_BASE + 0x004)
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#define SHA_H0 (SHA_REG_BASE + 0x008)
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#define SHA_H1 (SHA_REG_BASE + 0x00C)
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#define SHA_H2 (SHA_REG_BASE + 0x010)
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#define SHA_H3 (SHA_REG_BASE + 0x014)
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#define SHA_H4 (SHA_REG_BASE + 0x018)
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/*
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* SD Host Controller registers.
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* http://wiiubrew.org/wiki/Hardware/SD_Host_Controller
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*/
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#define SD0_REG_BASE (0x0D070000)
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#define SD1_REG_BASE (0x0D080000)
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#define SD2_REG_BASE (0x0D100000)
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#define SD3_REG_BASE (0x0D110000)
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/*
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* OHCI registers.
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* http://wiiubrew.org/wiki/Hardware/USB_Host_Controller
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*/
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#define OHCI0_REG_BASE (0x0D050000)
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#define OHCI1_REG_BASE (0x0D060000)
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#define OHCI10_REG_BASE (0x0D130000)
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#define OHCI20_REG_BASE (0x0D150000)
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/*
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* EHCI registers.
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* http://wiiubrew.org/wiki/Hardware/USB_Host_Controller
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*/
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||
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#define EHCI0_REG_BASE (0x0D040000)
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||
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#define EHCI1_REG_BASE (0x0D120000)
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||
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#define EHCI2_REG_BASE (0x0D140000)
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||
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||
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/*
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||
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* EXI registers.
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||
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* http://wiiubrew.org/wiki/Hardware/Legacy#External_Interface
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||
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*/
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||
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#define EXI_REG_BASE (0x0D806800)
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||
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#define EXI0_REG_BASE (EXI_REG_BASE + 0x000)
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||
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#define EXI1_REG_BASE (EXI_REG_BASE + 0x014)
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||
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#define EXI2_REG_BASE (EXI_REG_BASE + 0x028)
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||
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|
#define EXIBOOT_REG_BASE (EXI_REG_BASE + 0x040)
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||
|
|
|
||
|
|
#define EXI0_CSR (EXI0_REG_BASE + 0x000)
|
||
|
|
#define EXI0_MAR (EXI0_REG_BASE + 0x004)
|
||
|
|
#define EXI0_LENGTH (EXI0_REG_BASE + 0x008)
|
||
|
|
#define EXI0_CR (EXI0_REG_BASE + 0x00C)
|
||
|
|
#define EXI0_DATA (EXI0_REG_BASE + 0x010)
|
||
|
|
|
||
|
|
#define EXI1_CSR (EXI1_REG_BASE + 0x000)
|
||
|
|
#define EXI1_MAR (EXI1_REG_BASE + 0x004)
|
||
|
|
#define EXI1_LENGTH (EXI1_REG_BASE + 0x008)
|
||
|
|
#define EXI1_CR (EXI1_REG_BASE + 0x00C)
|
||
|
|
#define EXI1_DATA (EXI1_REG_BASE + 0x010)
|
||
|
|
|
||
|
|
#define EXI2_CSR (EXI2_REG_BASE + 0x000)
|
||
|
|
#define EXI2_MAR (EXI2_REG_BASE + 0x004)
|
||
|
|
#define EXI2_LENGTH (EXI2_REG_BASE + 0x008)
|
||
|
|
#define EXI2_CR (EXI2_REG_BASE + 0x00C)
|
||
|
|
#define EXI2_DATA (EXI2_REG_BASE + 0x010)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Memory Controller registers.
|
||
|
|
* http://wiiubrew.org/wiki/Hardware/Memory_Controller
|
||
|
|
*/
|
||
|
|
#define MEM_REG_BASE (0x0D8B4000)
|
||
|
|
|
||
|
|
#define MEM_PROT (MEM_REG_BASE + 0x20A)
|
||
|
|
#define MEM_PROT_START (MEM_REG_BASE + 0x20C)
|
||
|
|
#define MEM_PROT_END (MEM_REG_BASE + 0x20E)
|
||
|
|
#define MEM_REFRESH_FLAG (MEM_REG_BASE + 0x226)
|
||
|
|
#define MEM_FLUSH_MASK (MEM_REG_BASE + 0x228)
|
||
|
|
#define MEM_FLUSH_ACK (MEM_REG_BASE + 0x22A)
|
||
|
|
#define MEM_SEQ_REG_VAL (MEM_REG_BASE + 0x2C4)
|
||
|
|
#define MEM_SEQ_REG_ADDR (MEM_REG_BASE + 0x2C6)
|
||
|
|
#define MEM_SEQ0_REG_VAL (MEM_REG_BASE + 0x300)
|
||
|
|
#define MEM_SEQ0_REG_ADDR (MEM_REG_BASE + 0x302)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* AHMN registers.
|
||
|
|
* http://wiiubrew.org/wiki/Hardware/XN_Controller
|
||
|
|
*/
|
||
|
|
#define AHMN_REG_BASE (0x0D8B0800)
|
||
|
|
|
||
|
|
#define AHMN_MEM0_CONFIG (AHMN_REG_BASE + 0x000)
|
||
|
|
#define AHMN_MEM1_CONFIG (AHMN_REG_BASE + 0x004)
|
||
|
|
#define AHMN_MEM2_CONFIG (AHMN_REG_BASE + 0x008)
|
||
|
|
#define AHMN_RDBI_MASK (AHMN_REG_BASE + 0x00C)
|
||
|
|
#define AHMN_ERROR_MASK (AHMN_REG_BASE + 0x020)
|
||
|
|
#define AHMN_ERROR (AHMN_REG_BASE + 0x024)
|
||
|
|
#define AHMN_UNK40 (AHMN_REG_BASE + 0x040)
|
||
|
|
#define AHMN_UNK44 (AHMN_REG_BASE + 0x044)
|
||
|
|
#define AHMN_TRANSFER_STATE (AHMN_REG_BASE + 0x050)
|
||
|
|
#define AHMN_WORKAROUND (AHMN_REG_BASE + 0x054)
|
||
|
|
|
||
|
|
#define AHMN_MEM0 (AHMN_REG_BASE + 0x100)
|
||
|
|
#define AHMN_MEM1 (AHMN_REG_BASE + 0x200)
|
||
|
|
#define AHMN_MEM2 (AHMN_REG_BASE + 0x400)
|
||
|
|
|
||
|
|
#endif
|