mirror of
https://github.com/wiiu-env/libfat.git
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3a9b3b5e3a
Combined all CF-based hardware drivers into one set of routines with different sets of registers. Speed should remain the same, but size should be reduced.
308 lines
8.6 KiB
C
308 lines
8.6 KiB
C
/*
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io_efa2.c by CyteX
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Based on io_mpfc.c by chishm (Michael Chisholm)
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Hardware Routines for reading the NAND flash located on
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EFA2 flash carts
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This software is completely free. No warranty is provided.
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If you use it, please give me credit and email me about your
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project at cytex <at> gmx <dot> de and do not forget to also
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drop chishm <at> hotmail <dot> com a line
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Use with permission by Michael "Chishm" Chisholm
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*/
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#include "io_efa2.h"
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//
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// EFA2 register addresses
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//
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// RTC registers
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#define REG_RTC_CLK (*(vu16*)0x080000c4)
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#define REG_RTC_EN (*(vu16*)0x080000c8)
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// "Magic" registers used for unlock/lock sequences
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#define REG_EFA2_MAGIC_A (*(vu16*)0x09fe0000)
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#define REG_EFA2_MAGIC_B (*(vu16*)0x08000000)
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#define REG_EFA2_MAGIC_C (*(vu16*)0x08020000)
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#define REG_EFA2_MAGIC_D (*(vu16*)0x08040000)
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#define REG_EFA2_MAGIC_E (*(vu16*)0x09fc0000)
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// NAND flash lock/unlock register
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#define REG_EFA2_NAND_LOCK (*(vu16*)0x09c40000)
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// NAND flash enable register
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#define REG_EFA2_NAND_EN (*(vu16*)0x09400000)
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// NAND flash command write register
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#define REG_EFA2_NAND_CMD (*(vu8*)0x09ffffe2)
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// NAND flash address/data write register
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#define REG_EFA2_NAND_WR (*(vu8*)0x09ffffe0)
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// NAND flash data read register
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#define REG_EFA2_NAND_RD (*(vu8*)0x09ffc000)
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// ID of Samsung K9K1G NAND flash chip
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#define EFA2_NAND_ID 0xEC79A5C0
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// first sector of udisk
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#define EFA2_UDSK_START 0x40
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//
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// EFA2 access functions
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//
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// deactivate RTC ports
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static inline void _EFA2_rtc_deactivate(void) {
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REG_RTC_EN = 0;
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}
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// unlock register access
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static void _EFA2_reg_unlock(void) {
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REG_EFA2_MAGIC_A = 0x0d200;
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REG_EFA2_MAGIC_B = 0x01500;
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REG_EFA2_MAGIC_C = 0x0d200;
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REG_EFA2_MAGIC_D = 0x01500;
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}
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// finish/lock register access
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static inline void _EFA2_reg_lock(void) {
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REG_EFA2_MAGIC_E = 0x1500;
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}
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// global reset/init/enable/unlock ?
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static void _EFA2_global_unlock(void) {
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_EFA2_reg_unlock();
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*(vu16*)0x09880000 = 0x08000;
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_EFA2_reg_lock();
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}
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// global lock, stealth mode
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/*static void _EFA2_global_lock(void) {
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// quite sure there is such a sequence, but haven't had
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// a look for it upto now
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}*/
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// unlock NAND Flash
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static void _EFA2_nand_unlock(void) {
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_EFA2_reg_unlock();
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REG_EFA2_NAND_LOCK = 0x01500;
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_EFA2_reg_lock();
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}
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// lock NAND Flash
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static void _EFA2_nand_lock(void) {
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_EFA2_reg_unlock();
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REG_EFA2_NAND_LOCK = 0x0d200;
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_EFA2_reg_lock();
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}
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//
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// Set NAND Flash chip enable and write protection bits ?
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//
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// val | ~CE | ~WP |
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// -----+-----+-----+
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// 0 | 0 | 0 |
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// 1 | 1 | 0 |
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// 3 | 1 | 1 |
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// -----+-----+-----+
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//
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static void _EFA2_nand_enable(u16 val) {
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_EFA2_reg_unlock();
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REG_EFA2_NAND_EN = val;
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_EFA2_reg_lock();
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}
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//
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// Perform NAND reset
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// NAND has to be unlocked and enabled when called
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//
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static inline void _EFA2_nand_reset(void) {
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REG_EFA2_NAND_CMD = 0xff; // write reset command
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}
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//
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// Read out NAND ID information, could be used for card detection
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//
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// | EFA2 1GBit |
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// ------------------+------------+
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// maker code | 0xEC |
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// device code | 0x79 |
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// don't care | 0xA5 |
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// multi plane code | 0xC0 |
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// ------------------+------------+
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//
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static u32 _EFA2_nand_id(void) {
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u8 byte;
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u32 id;
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_EFA2_nand_unlock();
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_EFA2_nand_enable(1);
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REG_EFA2_NAND_CMD = 0x90; // write id command
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REG_EFA2_NAND_WR = 0x00; // (dummy) address cycle
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byte = REG_EFA2_NAND_RD; // read maker code
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id = byte;
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byte = REG_EFA2_NAND_RD; // read device code
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id = (id << 8) | byte;
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byte = REG_EFA2_NAND_RD; // read don't care
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id = (id << 8) | byte;
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byte = REG_EFA2_NAND_RD; // read multi plane code
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id = (id << 8) | byte;
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_EFA2_nand_enable(0);
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_EFA2_nand_lock();
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return (id);
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}
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//
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// Start of gba_nds_fat block device description
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//
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/*-----------------------------------------------------------------
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EFA2_clearStatus
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Reads and checks NAND status information
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bool return OUT: true if NAND is idle
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-----------------------------------------------------------------*/
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bool _EFA2_clearStatus (void)
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{
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// tbd: currently there is no write support, so always return
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// true, there is no possibility for pending operations
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return true;
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}
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/*-----------------------------------------------------------------
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EFA2_isInserted
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Checks to see if the NAND chip used by the EFA2 is present
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bool return OUT: true if the correct NAND chip is found
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-----------------------------------------------------------------*/
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bool _EFA2_isInserted (void)
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{
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_EFA2_clearStatus();
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return (_EFA2_nand_id() == EFA2_NAND_ID);
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}
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/*-----------------------------------------------------------------
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EFA2_readSectors
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Read "numSecs" 512 byte sectors starting from "sector" into "buffer"
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No error correction, no use of spare cells, no use of R/~B signal
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u32 sector IN: number of first 512 byte sector to be read
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u32 numSecs IN: number of 512 byte sectors to read,
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void* buffer OUT: pointer to 512 byte buffer to store data in
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bool return OUT: true if successful
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-----------------------------------------------------------------*/
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bool _EFA2_readSectors (u32 sector, u32 numSecs, void* buffer)
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{
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int i;
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#ifndef _IO_ALLOW_UNALIGNED
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u8 byte;
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u16 word;
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#endif
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// NAND page 0x40 (EFA2_UDSK_START) contains the MBR of the
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// udisk and thus is sector 0. The original EFA2 firmware
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// does never look at this, it only watches page 0x60, which
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// contains the boot block of the FAT16 partition. That is
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// fixed, so the EFA2 udisk must not be reformated, else
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// the ARK Octopus and also the original Firmware won't be
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// able to access the udisk anymore and I have to write a
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// recovery tool.
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u32 page = EFA2_UDSK_START + sector;
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// future enhancement: wait for possible write operations to
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// be finisched
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if (!_EFA2_clearStatus()) return false;
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_EFA2_nand_unlock();
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_EFA2_nand_enable(1);
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_EFA2_nand_reset();
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// set NAND to READ1 operation mode and transfer page address
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REG_EFA2_NAND_CMD = 0x00; // write READ1 command
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REG_EFA2_NAND_WR = 0x00; // write address [7:0]
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REG_EFA2_NAND_WR = (page ) & 0xff; // write address [15:8]
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REG_EFA2_NAND_WR = (page >> 8 ) & 0xff; // write address[23:16]
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REG_EFA2_NAND_WR = (page >> 16) & 0xff; // write address[26:24]
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// Due to a bug in EFA2 design there is need to waste some cycles
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// "by hand" instead the possibility to check the R/~B port of
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// the NAND flash via a register. The RTC deactivation is only
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// there to make sure the loop won't be optimized by the compiler
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for (i=0 ; i < 3 ; i++) _EFA2_rtc_deactivate();
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while (numSecs--)
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{
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// read page data
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#ifdef _IO_ALLOW_UNALIGNED
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// slow byte access to RAM, but works in principle
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for (i=0 ; i < 512 ; i++)
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((u8*)buffer)[i] = REG_EFA2_NAND_RD;
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#else
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// a bit faster, but DMA is not possible
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for (i=0 ; i < 256 ; i++) {
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byte = REG_EFA2_NAND_RD; // read lo-byte
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word = byte;
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byte = REG_EFA2_NAND_RD; // read hi-byte
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word = word | (byte << 8);
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((u16*)buffer)[i] = word;
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}
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#endif
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}
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_EFA2_nand_enable(0);
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_EFA2_nand_lock();
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return true;
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}
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/*-----------------------------------------------------------------
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EFA2_writeSectors
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Write "numSecs" 512 byte sectors starting at "sector" from "buffer"
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u32 sector IN: address of 512 byte sector on card to write
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u32 numSecs IN: number of 512 byte sectors to write
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1 to 256 sectors can be written, 0 = 256
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void* buffer IN: pointer to 512 byte buffer to read data from
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bool return OUT: true if successful
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-----------------------------------------------------------------*/
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bool _EFA2_writeSectors (u32 sector, u8 numSecs, void* buffer)
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{
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// Upto now I focused on reading NAND, write operations
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// will follow
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return false;
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}
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/*-----------------------------------------------------------------
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EFA2_shutdown
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unload the EFA2 interface
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-----------------------------------------------------------------*/
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bool _EFA2_shutdown(void)
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{
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return _EFA2_clearStatus();
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}
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/*-----------------------------------------------------------------
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EFA2_startUp
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initializes the EFA2 card, returns true if successful,
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otherwise returns false
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-----------------------------------------------------------------*/
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bool _EFA2_startUp(void)
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{
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_EFA2_global_unlock();
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return (_EFA2_nand_id() == EFA2_NAND_ID);
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}
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/*-----------------------------------------------------------------
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the actual interface structure
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-----------------------------------------------------------------*/
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IO_INTERFACE _io_efa2 = {
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DEVICE_TYPE_EFA2,
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FEATURE_MEDIUM_CANREAD | FEATURE_SLOT_GBA,
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(FN_MEDIUM_STARTUP)&_EFA2_startUp,
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(FN_MEDIUM_ISINSERTED)&_EFA2_isInserted,
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(FN_MEDIUM_READSECTORS)&_EFA2_readSectors,
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(FN_MEDIUM_WRITESECTORS)&_EFA2_writeSectors,
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(FN_MEDIUM_CLEARSTATUS)&_EFA2_clearStatus,
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(FN_MEDIUM_SHUTDOWN)&_EFA2_shutdown
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};
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