mirror of
https://github.com/Maschell/libutils.git
synced 2024-11-18 18:19:16 +01:00
239 lines
8.1 KiB
C
239 lines
8.1 KiB
C
#include "kernel_defs.h"
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#include <dynamic_libs/os_functions.h>
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#include <dynamic_libs/os_types.h>
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#include "utils/utils.h"
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#include "syscalls.h"
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extern void my_PrepareTitle_hook(void);
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static void KernelCopyData(u32 addr, u32 src, u32 len)
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{
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/*
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* Setup a DBAT access with cache inhibited to write through and read directly from memory
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*/
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u32 dbatu0, dbatl0, dbatu1, dbatl1;
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// save the original DBAT value
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asm volatile("mfdbatu %0, 0" : "=r" (dbatu0));
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asm volatile("mfdbatl %0, 0" : "=r" (dbatl0));
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asm volatile("mfdbatu %0, 1" : "=r" (dbatu1));
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asm volatile("mfdbatl %0, 1" : "=r" (dbatl1));
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u32 target_dbatu0 = 0;
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u32 target_dbatl0 = 0;
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u32 target_dbatu1 = 0;
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u32 target_dbatl1 = 0;
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unsigned char *dst_p = (unsigned char*)addr;
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unsigned char *src_p = (unsigned char*)src;
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// we only need DBAT modification for addresses out of our own DBAT range
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// as our own DBAT is available everywhere for user and supervisor
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// since our own DBAT is on DBAT5 position we don't collide here
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if(addr < 0x00800000 || addr >= 0x01000000)
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{
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target_dbatu0 = (addr & 0x00F00000) | 0xC0000000 | 0x1F;
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target_dbatl0 = (addr & 0xFFF00000) | 0x32;
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asm volatile("mtdbatu 0, %0" : : "r" (target_dbatu0));
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asm volatile("mtdbatl 0, %0" : : "r" (target_dbatl0));
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dst_p = (unsigned char*)((addr & 0xFFFFFF) | 0xC0000000);
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}
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if(src < 0x00800000 || src >= 0x01000000)
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{
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target_dbatu1 = (src & 0x00F00000) | 0xB0000000 | 0x1F;
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target_dbatl1 = (src & 0xFFF00000) | 0x32;
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asm volatile("mtdbatu 1, %0" : : "r" (target_dbatu1));
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asm volatile("mtdbatl 1, %0" : : "r" (target_dbatl1));
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src_p = (unsigned char*)((src & 0xFFFFFF) | 0xB0000000);
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}
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asm volatile("eieio; isync");
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u32 i;
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for(i = 0; i < len; i++)
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{
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// if we are on the edge to next chunk
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if((target_dbatu0 != 0) && (((u32)dst_p & 0x00F00000) != (target_dbatu0 & 0x00F00000)))
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{
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target_dbatu0 = ((addr + i) & 0x00F00000) | 0xC0000000 | 0x1F;
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target_dbatl0 = ((addr + i) & 0xFFF00000) | 0x32;
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dst_p = (unsigned char*)(((addr + i) & 0xFFFFFF) | 0xC0000000);
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asm volatile("eieio; isync");
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asm volatile("mtdbatu 0, %0" : : "r" (target_dbatu0));
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asm volatile("mtdbatl 0, %0" : : "r" (target_dbatl0));
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asm volatile("eieio; isync");
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}
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if((target_dbatu1 != 0) && (((u32)src_p & 0x00F00000) != (target_dbatu1 & 0x00F00000)))
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{
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target_dbatu1 = ((src + i) & 0x00F00000) | 0xB0000000 | 0x1F;
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target_dbatl1 = ((src + i) & 0xFFF00000) | 0x32;
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src_p = (unsigned char*)(((src + i) & 0xFFFFFF) | 0xB0000000);
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asm volatile("eieio; isync");
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asm volatile("mtdbatu 1, %0" : : "r" (target_dbatu1));
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asm volatile("mtdbatl 1, %0" : : "r" (target_dbatl1));
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asm volatile("eieio; isync");
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}
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*dst_p = *src_p;
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++dst_p;
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++src_p;
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}
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/*
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* Restore original DBAT value
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*/
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asm volatile("eieio; isync");
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asm volatile("mtdbatu 0, %0" : : "r" (dbatu0));
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asm volatile("mtdbatl 0, %0" : : "r" (dbatl0));
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asm volatile("mtdbatu 1, %0" : : "r" (dbatu1));
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asm volatile("mtdbatl 1, %0" : : "r" (dbatl1));
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asm volatile("eieio; isync");
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}
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static void KernelReadDBATs(bat_table_t * table)
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{
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u32 i = 0;
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asm volatile("eieio; isync");
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asm volatile("mfspr %0, 536" : "=r" (table->bat[i].h));
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asm volatile("mfspr %0, 537" : "=r" (table->bat[i].l));
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i++;
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asm volatile("mfspr %0, 538" : "=r" (table->bat[i].h));
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asm volatile("mfspr %0, 539" : "=r" (table->bat[i].l));
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i++;
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asm volatile("mfspr %0, 540" : "=r" (table->bat[i].h));
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asm volatile("mfspr %0, 541" : "=r" (table->bat[i].l));
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i++;
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asm volatile("mfspr %0, 542" : "=r" (table->bat[i].h));
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asm volatile("mfspr %0, 543" : "=r" (table->bat[i].l));
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i++;
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asm volatile("mfspr %0, 568" : "=r" (table->bat[i].h));
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asm volatile("mfspr %0, 569" : "=r" (table->bat[i].l));
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i++;
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asm volatile("mfspr %0, 570" : "=r" (table->bat[i].h));
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asm volatile("mfspr %0, 571" : "=r" (table->bat[i].l));
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i++;
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asm volatile("mfspr %0, 572" : "=r" (table->bat[i].h));
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asm volatile("mfspr %0, 573" : "=r" (table->bat[i].l));
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i++;
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asm volatile("mfspr %0, 574" : "=r" (table->bat[i].h));
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asm volatile("mfspr %0, 575" : "=r" (table->bat[i].l));
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}
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static void KernelWriteDBATs(bat_table_t * table)
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{
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u32 i = 0;
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asm volatile("eieio; isync");
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asm volatile("mtspr 536, %0" : : "r" (table->bat[i].h));
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asm volatile("mtspr 537, %0" : : "r" (table->bat[i].l));
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i++;
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asm volatile("mtspr 538, %0" : : "r" (table->bat[i].h));
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asm volatile("mtspr 539, %0" : : "r" (table->bat[i].l));
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i++;
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asm volatile("mtspr 540, %0" : : "r" (table->bat[i].h));
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asm volatile("mtspr 541, %0" : : "r" (table->bat[i].l));
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i++;
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asm volatile("mtspr 542, %0" : : "r" (table->bat[i].h));
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asm volatile("mtspr 543, %0" : : "r" (table->bat[i].l));
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i++;
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asm volatile("mtspr 568, %0" : : "r" (table->bat[i].h));
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asm volatile("mtspr 569, %0" : : "r" (table->bat[i].l));
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i++;
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asm volatile("mtspr 570, %0" : : "r" (table->bat[i].h));
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asm volatile("mtspr 571, %0" : : "r" (table->bat[i].l));
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i++;
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asm volatile("mtspr 572, %0" : : "r" (table->bat[i].h));
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asm volatile("mtspr 573, %0" : : "r" (table->bat[i].l));
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i++;
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asm volatile("mtspr 574, %0" : : "r" (table->bat[i].h));
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asm volatile("mtspr 575, %0" : : "r" (table->bat[i].l));
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asm volatile("eieio; isync");
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}
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/* Read a 32-bit word with kernel permissions */
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uint32_t __attribute__ ((noinline)) kern_read(const void *addr)
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{
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uint32_t result;
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asm volatile (
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"li 3,1\n"
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"li 4,0\n"
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"li 5,0\n"
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"li 6,0\n"
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"li 7,0\n"
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"lis 8,1\n"
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"mr 9,%1\n"
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"li 0,0x3400\n"
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"mr %0,1\n"
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"sc\n"
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"nop\n"
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"mr 1,%0\n"
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"mr %0,3\n"
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: "=r"(result)
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: "b"(addr)
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: "memory", "ctr", "lr", "0", "3", "4", "5", "6", "7", "8", "9", "10",
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"11", "12"
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);
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return result;
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}
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/* Write a 32-bit word with kernel permissions */
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void __attribute__ ((noinline)) kern_write(void *addr, uint32_t value)
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{
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asm volatile (
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"li 3,1\n"
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"li 4,0\n"
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"mr 5,%1\n"
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"li 6,0\n"
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"li 7,0\n"
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"lis 8,1\n"
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"mr 9,%0\n"
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"mr %1,1\n"
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"li 0,0x3500\n"
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"sc\n"
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"nop\n"
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"mr 1,%1\n"
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:
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: "r"(addr), "r"(value)
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: "memory", "ctr", "lr", "0", "3", "4", "5", "6", "7", "8", "9", "10",
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"11", "12"
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);
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}
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void KernelSetupSyscalls(void)
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{
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//! assign 1 so that this variable gets into the retained .data section
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static uint8_t ucSyscallsSetupRequired = 1;
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if(!ucSyscallsSetupRequired)
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return;
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ucSyscallsSetupRequired = 0;
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kern_write((void*)(OS_SPECIFICS->addr_KernSyscallTbl1 + (0x36 * 4)), (u32)KernelReadDBATs);
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kern_write((void*)(OS_SPECIFICS->addr_KernSyscallTbl2 + (0x36 * 4)), (u32)KernelReadDBATs);
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kern_write((void*)(OS_SPECIFICS->addr_KernSyscallTbl3 + (0x36 * 4)), (u32)KernelReadDBATs);
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kern_write((void*)(OS_SPECIFICS->addr_KernSyscallTbl4 + (0x36 * 4)), (u32)KernelReadDBATs);
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kern_write((void*)(OS_SPECIFICS->addr_KernSyscallTbl5 + (0x36 * 4)), (u32)KernelReadDBATs);
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kern_write((void*)(OS_SPECIFICS->addr_KernSyscallTbl1 + (0x37 * 4)), (u32)KernelWriteDBATs);
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kern_write((void*)(OS_SPECIFICS->addr_KernSyscallTbl2 + (0x37 * 4)), (u32)KernelWriteDBATs);
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kern_write((void*)(OS_SPECIFICS->addr_KernSyscallTbl3 + (0x37 * 4)), (u32)KernelWriteDBATs);
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kern_write((void*)(OS_SPECIFICS->addr_KernSyscallTbl4 + (0x37 * 4)), (u32)KernelWriteDBATs);
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kern_write((void*)(OS_SPECIFICS->addr_KernSyscallTbl5 + (0x37 * 4)), (u32)KernelWriteDBATs);
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kern_write((void*)(OS_SPECIFICS->addr_KernSyscallTbl1 + (0x25 * 4)), (u32)KernelCopyData);
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kern_write((void*)(OS_SPECIFICS->addr_KernSyscallTbl2 + (0x25 * 4)), (u32)KernelCopyData);
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kern_write((void*)(OS_SPECIFICS->addr_KernSyscallTbl3 + (0x25 * 4)), (u32)KernelCopyData);
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kern_write((void*)(OS_SPECIFICS->addr_KernSyscallTbl4 + (0x25 * 4)), (u32)KernelCopyData);
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kern_write((void*)(OS_SPECIFICS->addr_KernSyscallTbl5 + (0x25 * 4)), (u32)KernelCopyData);
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}
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