2008-12-28 14:35:37 +01:00
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#ifndef __HOLLYWOOD_H__
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#define __HOLLYWOOD_H__
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/* Hollywood Registers */
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#define HW_PPC_REG_BASE 0xd000000
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#define HW_REG_BASE 0xd800000
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// The PPC can only see the first three IPC registers
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#define HW_IPC_PPCMSG (HW_REG_BASE + 0x000) //PPC to ARM
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#define HW_IPC_PPCCTRL (HW_REG_BASE + 0x004)
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#define HW_IPC_ARMMSG (HW_REG_BASE + 0x008) //ARM to PPC
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#define HW_IPC_ARMCTRL (HW_REG_BASE + 0x00c)
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// Write one to send a message. Cleared when peer writes one to IPC_CTRL_RECV.
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#define IPC_CTRL_SEND 0x01
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// Set by peer to acknowledge a message. Write one to clear.
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#define IPC_CTRL_SENT 0x02
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// Set by peer to send a message. Write one to clear.
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#define IPC_CTRL_RECV 0x04
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// Write one acknowledge a message. Cleared when peer writes one to IPC_CTRL_SENT.
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#define IPC_CTRL_RECVD 0x08
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// Enable interrupt when a message is received
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#define IPC_CTRL_INT_RECV 0x10
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// Enable interrupt when a sent message is acknowledged
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#define IPC_CTRL_INT_SENT 0x20
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/*
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The IPC registers are connected to each other.
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Both registers are identical and this works for
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both peers. Flag bits are cleared by writing a one
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to them.
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When Peer A sets this Peer B sees this set
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IPC_CTRL_SEND IPC_CTRL_RECV
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IPC_CTRL_RECVD IPC_CTRL_SENT
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In fact, bit _SEND on Peer A and bit _RECV on peer B are the same bit,
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and the same goes for _RECVD and _SENT, except writing one from A _sets_
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the bit, and writing one from B _clears_ the bit. The same, of course,
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is true for the other pair of bits in the other direction.
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The flow, therefore, goes as follows, for a message
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from A to B. Steps with the same number can be taken
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in any order.
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1. Peer A writes the message address to the register
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2. Peer A sets IPC_CTRL_SEND
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3. Peer B sees IPC_CTRL_RECV
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4. Peer B writes one to IPC_CTRL_RECV to clear it (A's IPC_CTRL_SEND is cleared at this point)
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4. Peer B reads its message address register
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5. Peer B sets IPC_CTRL_RECVD
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6. Peer A sees IPC_CTRL_SENT
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7. Peer A writes one to IPC_CTRL_SENT to clear it (B's IPC_CTRL_RECVD is cleared at this point)
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7. Peer A may now write to the message address register again
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The same is true for a message from Peer B to Peer A.
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In the particular case of IOS IPC, the PPC is always the "master"
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(it sends requests as messages) and the ARM is always the "slave"
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(it replies to PPC's requests). IOS can handle up to 16(15?)
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simultaneously pending transactions (the PPC can send up to 16(15?)
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messages without getting any replies - for example, due to
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asynchronous requests or multithreaded execution of blocking
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requests)
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*/
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#define HW_TIMER (HW_REG_BASE + 0x010)
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#define HW_ALARM (HW_REG_BASE + 0x014)
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// maybe?
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#define HW_FIQFLAG (HW_REG_BASE + 0x030)
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#define HW_FIQENABLE (HW_REG_BASE + 0x034)
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#define HW_IRQFLAG (HW_REG_BASE + 0x038)
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#define HW_IRQENABLE (HW_REG_BASE + 0x03c)
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#define HW_MEMMIRR (HW_REG_BASE + 0x060)
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// something to do with PPCBOOT
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// and legacy DI it seems ?!?
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#define HW_EXICTRL (HW_REG_BASE + 0x070)
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#define EXICTRL_ENABLE_EXI 1
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// PPC side of GPIO1 (Starlet can access this too)
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// Output state
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#define HW_GPIO1BOUT (HW_REG_BASE + 0x0c0)
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// Direction (1=output)
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#define HW_GPIO1BDIR (HW_REG_BASE + 0x0c4)
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// Input state
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#define HW_GPIO1BIN (HW_REG_BASE + 0x0c8)
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// Interrupt level
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#define HW_GPIO1BINTLVL (HW_REG_BASE + 0x0cc)
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// Interrupt flags (write 1 to clear)
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#define HW_GPIO1BINTFLAG (HW_REG_BASE + 0x0d0)
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// Interrupt propagation enable
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// Do these interrupts go anywhere???
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#define HW_GPIO1BINTENABLE (HW_REG_BASE + 0x0d4)
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//??? seems to be a mirror of inputs at some point... power-up state?
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#define HW_GPIO1BINMIR (HW_REG_BASE + 0x0d8)
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// 0xFFFFFF by default, if cleared disables respective outputs. Top bits non-settable.
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#define HW_GPIO1ENABLE (HW_REG_BASE + 0x0dc)
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#define HW_GPIO1_SLOT 0x000020
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#define HW_GPIO1_DEBUG 0xFF0000
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#define HW_GPIO1_DEBUG_SH 16
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// Starlet side of GPIO1
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// Output state
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#define HW_GPIO1OUT (HW_REG_BASE + 0x0e0)
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// Direction (1=output)
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#define HW_GPIO1DIR (HW_REG_BASE + 0x0e4)
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// Input state
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#define HW_GPIO1IN (HW_REG_BASE + 0x0e8)
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// Interrupt level
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#define HW_GPIO1INTLVL (HW_REG_BASE + 0x0ec)
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// Interrupt flags (write 1 to clear)
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#define HW_GPIO1INTFLAG (HW_REG_BASE + 0x0f0)
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// Interrupt propagation enable (interrupts go to main interrupt 0x800)
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#define HW_GPIO1INTENABLE (HW_REG_BASE + 0x0f4)
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//??? seems to be a mirror of inputs at some point... power-up state?
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#define HW_GPIO1INMIR (HW_REG_BASE + 0x0f8)
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// Owner of each GPIO bit. If 1, GPIO1B registers assume control. If 0, GPIO1 registers assume control.
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#define HW_GPIO1OWNER (HW_REG_BASE + 0x0fc)
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// ????
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#define HW_DIFLAGS (HW_REG_BASE + 0x180)
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#define DIFLAGS_BOOT_CODE 0x100000
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// maybe a GPIO???
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#define HW_RESETS (HW_REG_BASE + 0x194)
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2009-01-08 23:27:22 +01:00
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#define HW_CLOCKS (HW_REG_BASE + 0x1b4)
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2008-12-28 14:35:37 +01:00
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#define HW_GPIO2OUT (HW_REG_BASE + 0x1c8)
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#define HW_GPIO2DIR (HW_REG_BASE + 0x1cc)
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#define HW_GPIO2IN (HW_REG_BASE + 0x1d0)
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#define HW_OTPCMD (HW_REG_BASE + 0x1ec)
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#define HW_OTPDATA (HW_REG_BASE + 0x1f0)
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2009-02-20 13:24:48 +01:00
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#define HW_VERSION (HW_REG_BASE + 0x214)
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2008-12-28 14:35:37 +01:00
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/* NAND Registers */
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#define NAND_REG_BASE 0xd010000
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#define NAND_CMD (NAND_REG_BASE + 0x000)
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#define NAND_STATUS NAND_CMD
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#define NAND_CONF (NAND_REG_BASE + 0x004)
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#define NAND_ADDR0 (NAND_REG_BASE + 0x008)
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#define NAND_ADDR1 (NAND_REG_BASE + 0x00c)
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#define NAND_DATA (NAND_REG_BASE + 0x010)
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#define NAND_ECC (NAND_REG_BASE + 0x014)
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#define NAND_UNK1 (NAND_REG_BASE + 0x018)
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#define NAND_UNK2 (NAND_REG_BASE + 0x01c)
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/* AES Registers */
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#define AES_REG_BASE 0xd020000
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#define AES_CMD (AES_REG_BASE + 0x000)
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#define AES_SRC (AES_REG_BASE + 0x004)
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#define AES_DEST (AES_REG_BASE + 0x008)
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#define AES_KEY (AES_REG_BASE + 0x00c)
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#define AES_IV (AES_REG_BASE + 0x010)
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/* SHA-1 Registers */
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#define SHA_REG_BASE 0xd030000
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#define SHA_CMD (SHA_REG_BASE + 0x000)
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#define SHA_SRC (SHA_REG_BASE + 0x004)
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#define SHA_H0 (SHA_REG_BASE + 0x008)
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#define SHA_H1 (SHA_REG_BASE + 0x00c)
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#define SHA_H2 (SHA_REG_BASE + 0x010)
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#define SHA_H3 (SHA_REG_BASE + 0x014)
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#define SHA_H4 (SHA_REG_BASE + 0x018)
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/* SD Host Controller Registers */
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#define SD_REG_BASE 0xd070000
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#define SDHC_SDMA_ADDR (0x000)
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#define SDHC_BLOCK_SIZE (0x004)
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#define SDHC_BLOCK_COUNT (0x006)
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#define SDHC_CMD_ARG (0x008)
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#define SDHC_CMD_TRANSFER_MODE (0x00c)
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#define SDHC_CMD (0x00e)
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#define SDHC_RESPONSE (0x010)
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#define SDHC_DATA (0x020)
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#define SDHC_PRESENT_STATE (0x024)
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#define SDHC_HOST_CONTROL (0x028)
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#define SDHC_POWER_CONTROL (0x029)
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#define SDHC_BLOCK_GAP_CONTROL (0x02a)
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#define SDHC_WAKEUP_CONTROL (0x02b)
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#define SDHC_CLOCK_CONTROL (0x02c)
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#define SDHC_TIMEOUT_CONTROL (0x02e)
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#define SDHC_SOFTWARE_RESET (0x02f)
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#define SDHC_NORMAL_INTERRUPT_STATUS (0x030)
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#define SDHC_ERROR_INTERRUPT_STATUS (0x032)
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#define SDHC_NORMAL_INTERRUPT_ENABLE (0x034)
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#define SDHC_ERROR_INTERRUPT_ENABLE (0x036)
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#define SDHC_NORMAL_INTERRUPT_SIGNAL_ENABLE (0x038)
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#define SDHC_ERROR_INTERRUPT_SIGNAL_ENABLE (0x03a)
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#define SDHC_AMCD12_ERROR_STATUS (0x03c)
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#define SDHC_CAPABILITIES (0x040)
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#define SDHC_MAX_CAPABILITIES (0x048)
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#define SDHC_FORCE_ERROR_EVENT_ACMD12 (0x050)
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#define SDHC_FORCE_ERROR_EVENT_INTERRUPT (0x052)
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#define SDHC_ADMA_ERROR_STATUS (0x054)
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#define SDHC_ADMA_SYSTEM_ADDR (0x058)
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#define SDHC_SLOT_INTERRUPT_STATUS (0x0fc)
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#define SDHC_VERSION (0x0fe)
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/* EXI Registers */
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#define EXI_REG_BASE 0xd806800
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#define EXI0_REG_BASE (EXI_REG_BASE+0x000)
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#define EXI1_REG_BASE (EXI_REG_BASE+0x014)
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#define EXI2_REG_BASE (EXI_REG_BASE+0x028)
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#define EXI0_CSR (EXI0_REG_BASE+0x000)
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#define EXI0_MAR (EXI0_REG_BASE+0x004)
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#define EXI0_LENGTH (EXI0_REG_BASE+0x008)
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#define EXI0_CR (EXI0_REG_BASE+0x00c)
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#define EXI0_DATA (EXI0_REG_BASE+0x010)
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#define EXI1_CSR (EXI1_REG_BASE+0x000)
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#define EXI1_MAR (EXI1_REG_BASE+0x004)
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#define EXI1_LENGTH (EXI1_REG_BASE+0x008)
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#define EXI1_CR (EXI1_REG_BASE+0x00c)
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#define EXI1_DATA (EXI1_REG_BASE+0x010)
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#define EXI2_CSR (EXI2_REG_BASE+0x000)
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#define EXI2_MAR (EXI2_REG_BASE+0x004)
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#define EXI2_LENGTH (EXI2_REG_BASE+0x008)
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#define EXI2_CR (EXI2_REG_BASE+0x00c)
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#define EXI2_DATA (EXI2_REG_BASE+0x010)
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#define EXI_BOOT_BASE (EXI_REG_BASE+0x040)
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/* MEMORY CONTROLLER Registers */
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#define MEM_REG_BASE 0xd8b4000
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#define MEM_PROT (MEM_REG_BASE+0x20a)
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#define MEM_PROT_START (MEM_REG_BASE+0x20c)
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#define MEM_PROT_END (MEM_REG_BASE+0x20e)
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#define MEM_FLUSHREQ (MEM_REG_BASE+0x228)
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#define MEM_FLUSHACK (MEM_REG_BASE+0x22a)
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#endif
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