diff --git a/ipc.h b/ipc.h
index 672f69a..c1f81dc 100644
--- a/ipc.h
+++ b/ipc.h
@@ -36,11 +36,12 @@
 #define IPC_NAND_READ	0x0002
 #define IPC_NAND_WRITE	0x0003
 #define IPC_NAND_ERASE	0x0004
+#define IPC_NAND_STATUS	0x0005
 
 #define IPC_SD_MOUNT	0x0000
 #define IPC_SD_SELECT	0x0001
 #define IPC_SD_GETSTATE	0x0002
-#define IPC_SD_READ	0x0003
+#define IPC_SD_READ		0x0003
 #define IPC_SD_WRITE	0x0004
 
 #define IPC_KEYS_GETOTP	0x0000
diff --git a/nand.c b/nand.c
index b40e464..3c33568 100644
--- a/nand.c
+++ b/nand.c
@@ -119,10 +119,12 @@ void __nand_setup_dma(u8 *data, u8 *spare) {
 int nand_reset(void)
 {
 	NAND_debug("nand_reset()\n");
+	// IOS actually uses NAND_FLAGS_IRQ | NAND_FLAGS_WAIT here
 	nand_send_command(NAND_RESET, 0, NAND_FLAGS_WAIT, 0);
 	__nand_wait();
-// yay cargo cult
+// enable NAND controller
 	__nand_write32(NAND_CONF, 0x08000000);
+// set configuration parameters for 512MB flash chips
 	__nand_write32(NAND_CONF, 0x4b3e0e7f);
 	return 0;
 }
@@ -133,14 +135,16 @@ void nand_get_id(u8 *idbuf) {
 	dc_invalidaterange(idbuf, 0x40);
 
 	__nand_setup_dma(idbuf, (u8 *)-1);
-	nand_send_command(NAND_CHIPID, 1, NAND_FLAGS_IRQ | NAND_FLAGS_RD, 0x40);
+	nand_send_command(NAND_CHIPID, 1, NAND_FLAGS_RD, 0x40);
 }
 
 void nand_get_status(u8 *status_buf) {
 	status_buf[0]=0;
+
 	dc_invalidaterange(status_buf, 0x40);
+
 	__nand_setup_dma(status_buf, (u8 *)-1);
-	nand_send_command(NAND_GETSTATUS, 0, NAND_FLAGS_IRQ | NAND_FLAGS_RD, 0x40);
+	nand_send_command(NAND_GETSTATUS, 0, NAND_FLAGS_RD, 0x40);
 }
 
 void nand_read_page(u32 pageno, void *data, void *ecc) {
@@ -216,6 +220,12 @@ void nand_ipc(volatile ipc_request *req)
 			nand_get_id((u8 *)req->args[0]);
 			break;
 
+		case IPC_NAND_STATUS:
+			ipc_code = req->code;
+			ipc_tag = req->tag;
+			nand_get_status((u8 *)req->args[0]);
+			break;
+
 		case IPC_NAND_READ:
 			ipc_code = req->code;
 			ipc_tag = req->tag;