mirror of
https://github.com/fail0verflow/mini.git
synced 2024-06-23 03:26:08 +02:00
Memory stuff and add not working (so far) MMU/pagetable enable code
This commit is contained in:
marcan
bushing
parent
3a258f2ed9
commit
26816ee411
5
main.c
5
main.c
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@ -150,6 +150,9 @@ void *_main(void *base)
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gecko_init();
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gecko_puts("MiniIOS v0.1 loading\n");
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gecko_puts("Configuring caches and MMU...\n");
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mem_initialize();
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irq_initialize();
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@ -186,6 +189,8 @@ void *_main(void *base)
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ipc_shutdown();
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gecko_puts("Shutting down interrupts...\n");
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irq_shutdown();
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gecko_puts("Shutting down caches and MMU...\n");
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mem_shutdown();
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//vector = patch_boot2(base, (((u64)tidh)<<32) | tidl);
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100
memory.c
100
memory.c
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@ -4,12 +4,17 @@
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#include "utils.h"
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#include "gecko.h"
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#include "hollywood.h"
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#include "irq.h"
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void _dc_inval_entries(void *start, int count);
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void _dc_flush_entries(void *start, int count);
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void _dc_flush(void);
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void _dc_inval(void);
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void _ic_inval(void);
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void _drain_write_buffer(void);
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void _tlb_inval(void);
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extern u32 __page_table[4096];
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#define LINESIZE 0x20
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#define CACHESIZE 0x4000
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@ -51,7 +56,7 @@ u32 _mc_read32(u32 addr)
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}
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data = read32(addr);
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read32(HW_214); //???
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if(!(read32(HW_214) & 0xF0))
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write32(HW_130, tmp130);
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@ -133,7 +138,7 @@ void ahb_memflush(enum AHBDEV dev)
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u16 req = 0;
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u16 ack;
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int i;
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switch(dev)
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{
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case MEMORY:
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@ -149,9 +154,9 @@ void ahb_memflush(enum AHBDEV dev)
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}
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break;
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}
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write16(MEM_FLUSHREQ, req);
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for(i=0;i<1000000;i++) {
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ack = read16(MEM_FLUSHACK);
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_magic_bullshit(0);
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@ -166,6 +171,7 @@ void ahb_memflush(enum AHBDEV dev)
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void dc_flushrange(void *start, u32 size)
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{
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u32 cookie = irq_kill();
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if(size > 0x4000) {
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_dc_flush();
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} else {
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@ -175,27 +181,34 @@ void dc_flushrange(void *start, u32 size)
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}
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_drain_write_buffer();
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//ahb_memflush(MEMORY);
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irq_restore(cookie);
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}
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void dc_invalidaterange(void *start, u32 size)
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{
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u32 cookie = irq_kill();
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void *end = ALIGN_FORWARD(((u8*)start) + size, LINESIZE);
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start = ALIGN_BACKWARD(start, LINESIZE);
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_dc_inval_entries(start, (end - start) / LINESIZE);
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//_magic_bullshit(0);
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irq_restore(cookie);
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}
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void dc_flushall(void)
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{
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u32 cookie = irq_kill();
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_dc_flush();
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_drain_write_buffer();
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//ahb_memflush(MEMORY);
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irq_restore(cookie);
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}
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void ic_invalidateall(void)
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{
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u32 cookie = irq_kill();
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_ic_inval();
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//_magic_bullshit(0);
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irq_restore(cookie);
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}
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void mem_protect(int enable, void *start, void *end)
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@ -209,10 +222,87 @@ void mem_protect(int enable, void *start, void *end)
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void mem_setswap(int enable)
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{
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u32 d = read32(HW_MEMMIRR);
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if((d & 0x20) && !enable)
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write32(HW_MEMMIRR, d & ~0x20);
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if((!(d & 0x20)) && enable)
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write32(HW_MEMMIRR, d | 0x20);
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}
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#define SECTION 0x012
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#define NONBUFFERABLE 0x000
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#define BUFFERABLE 0x004
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#define WRITETHROUGH_CACHE 0x008
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#define WRITEBACK_CACHE 0x00C
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#define DOMAIN(x) ((x)<<5)
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#define AP_ROM 0x000
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#define AP_NOUSER 0x400
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#define AP_ROUSER 0x800
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#define AP_RWUSER 0xC00
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// from, to, size: units of 1MB
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void map_section(u16 from, u16 to, u16 size, u32 attributes)
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{
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attributes |= SECTION;
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while(size--) {
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__page_table[from++] = (to++<<20) | attributes;
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}
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}
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void mem_initialize(void)
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{
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u32 cookie = irq_kill();
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gecko_printf("MEM: cleaning up\n");
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_ic_inval();
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_dc_inval();
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_tlb_inval();
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gecko_printf("MEM: mapping sections\n");
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memset32(__page_table, 0, 16384);
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map_section(0x000, 0x000, 0x018, WRITEBACK_CACHE | DOMAIN(0) | AP_RWUSER);
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map_section(0x100, 0x100, 0x040, WRITEBACK_CACHE | DOMAIN(0) | AP_RWUSER);
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map_section(0x0d0, 0x0d0, 0x001, NONBUFFERABLE | DOMAIN(0) | AP_RWUSER);
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map_section(0x0d8, 0x0d8, 0x001, NONBUFFERABLE | DOMAIN(0) | AP_RWUSER);
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map_section(0xfff, 0xfff, 0x001, WRITEBACK_CACHE | DOMAIN(0) | AP_RWUSER);
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set_dacr(0xFFFFFFFF); //manager access for all domains, ignore AP
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_drain_write_buffer();
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gecko_printf("MEM: enabling caches\n");
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u32 cr = get_cr();
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cr |= 0x1004; //ICACHE/DCACHE and MMU enable
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set_cr(cr);
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gecko_printf("MEM: enabling MMU\n");
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cr |= 0x0001; //ICACHE/DCACHE and MMU enable
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set_cr(cr);
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gecko_printf("MEM: init done\n");
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irq_restore(cookie);
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}
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void mem_shutdown(void)
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{
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u32 cookie = irq_kill();
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_dc_flush();
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_drain_write_buffer();
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u32 cr = get_cr();
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cr &= ~0x1005; //disable ICACHE, DCACHE, MMU
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set_cr(cr);
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_ic_inval();
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_dc_inval();
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_tlb_inval();
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irq_restore(cookie);
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}
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54
memory.h
54
memory.h
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@ -24,4 +24,58 @@ void ahb_memflush(enum AHBDEV dev);
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void mem_protect(int enable, void *start, void *end);
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void mem_setswap(int enable);
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void mem_initialize(void);
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void mem_shutdown(void);
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static inline u32 get_cr(void)
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{
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u32 data;
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__asm__ volatile ( "mrc\tp15, 0, %0, c1, c0, 0" : "=r" (data) );
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return data;
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}
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static inline u32 get_ttbr(void)
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{
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u32 data;
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__asm__ volatile ( "mrc\tp15, 0, %0, c2, c0, 0" : "=r" (data) );
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return data;
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}
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static inline u32 get_dacr(void)
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{
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u32 data;
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__asm__ volatile ( "mrc\tp15, 0, %0, c3, c0, 0" : "=r" (data) );
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return data;
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}
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static inline void set_cr(u32 data)
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{
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__asm__ volatile ( "mcr\tp15, 0, %0, c1, c0, 0" :: "r" (data) );
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}
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static inline void set_ttbr(u32 data)
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{
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__asm__ volatile ( "mcr\tp15, 0, %0, c2, c0, 0" :: "r" (data) );
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}
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static inline void set_dacr(u32 data)
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{
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__asm__ volatile ( "mcr\tp15, 0, %0, c3, c0, 0" :: "r" (data) );
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}
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static inline u32 get_dfsr(void)
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{
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u32 data;
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__asm__ volatile ( "mrc\tp15, 0, %0, c5, c0, 0" : "=r" (data) );
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return data;
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}
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static inline u32 get_ifsr(void)
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{
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u32 data;
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__asm__ volatile ( "mrc\tp15, 0, %0, c5, c0, 1" : "=r" (data) );
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return data;
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}
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static inline u32 get_far(void)
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{
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u32 data;
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__asm__ volatile ( "mrc\tp15, 0, %0, c6, c0, 0" : "=r" (data) );
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return data;
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}
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#endif
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11
memory_asm.S
11
memory_asm.S
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@ -3,8 +3,10 @@
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.globl _dc_inval_entries
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.globl _dc_flush_entries
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.globl _dc_flush
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.globl _dc_inval
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.globl _ic_inval
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.globl _drain_write_buffer
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.globl _tlb_inval
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.text
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@ -27,6 +29,11 @@ _dc_flush:
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bne _dc_flush
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bx lr
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_dc_inval:
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mov r0, #0
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mcr p15, 0, r0, c7, c6, 0
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bx lr
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_ic_inval:
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0
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@ -37,3 +44,7 @@ _drain_write_buffer:
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mcr p15, 0, r0, c7, c10, 4
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bx lr
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_tlb_inval:
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mov r0, #0
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mcr p15, 0, r0, c8, c7
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bx lr
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