diff --git a/boot2.c b/boot2.c
index 9505bb3..dbb5d51 100644
--- a/boot2.c
+++ b/boot2.c
@@ -62,9 +62,7 @@ void boot2_init() {
 	aes_set_iv(iv);
 	aes_set_key(otp.common_key);
 	memcpy(key, tikptr+0x1bf, 16);
-	dc_flushrange(key, 32);
 	aes_decrypt(key, key, 1, 0);
-	dc_invalidaterange(key, 32);
 
 	memcpy(&datalen, tmdptr+0x1e4+8+4, 4);
 	memset(iv, 0, 16);
@@ -73,9 +71,7 @@ void boot2_init() {
 	aes_reset();
 	aes_set_iv(iv);
 	aes_set_key(key);
-	dc_flushrange(cntptr, ALIGN_FORWARD(datalen, 16));
 	aes_decrypt(cntptr, cntptr, ALIGN_FORWARD(datalen, 16)/16, 0);
-	dc_invalidaterange(cntptr, ALIGN_FORWARD(datalen, 16));
 
 	memcpy(boot2, cntptr, datalen);
 	boot2_initialized = 1;
diff --git a/crypto.c b/crypto.c
index 696e398..59c1604 100644
--- a/crypto.c
+++ b/crypto.c
@@ -112,10 +112,17 @@ void aes_decrypt(u8 *src, u8 *dst, u32 blocks, u8 keep_iv)
 		this_blocks = blocks;
 		if (this_blocks > 0x80)
 			this_blocks = 0x80;
-	
+
 		write32(AES_SRC, dma_addr(src));
 		write32(AES_DEST, dma_addr(dst));
+
+		dc_flushrange(src, blocks * 16);
+		dc_invalidaterange(src, blocks * 16);
+
+		ahb_flush_to(AHB_AES);
 		aes_command(AES_CMD_DECRYPT, keep_iv, this_blocks);
+		ahb_flush_from(AHB_AES);
+		ahb_flush_to(AHB_STARLET);
 
 		blocks -= this_blocks;
 		src += this_blocks<<4;
@@ -138,12 +145,8 @@ void aes_ipc(volatile ipc_request *req)
 			aes_set_key((u8 *)req->args);
 			break;
 		case IPC_AES_DECRYPT:
-			dc_invalidaterange((u8 *)req->args[0],
-					(req->args[3]+1)*16);
 			aes_decrypt((u8 *)req->args[0], (u8 *)req->args[1],
 				    req->args[2], req->args[3]);
-			dc_flushrange((u8 *)req->args[1],
-					(req->args[3]+1)*16);
 			break;
 		default:
 			gecko_printf("IPC: unknown SLOW AES request %04x\n",
diff --git a/memory.c b/memory.c
index b4af38d..253df35 100644
--- a/memory.c
+++ b/memory.c
@@ -69,8 +69,8 @@ void _ahb_flush_to(enum AHBDEV dev) {
 		case AHB_1: mask = 0x4000; break;
 		//case 2: mask = 0x0001; break;
 		case AHB_NAND: mask = 0x0002; break;
-		//case 4: mask = 0x0004; break;
-		//case 5: mask = 0x0008; break;
+		case AHB_AES: mask = 0x0004; break;
+		case AHB_SHA1: mask = 0x0008; break;
 		//case 6: mask = 0x0010; break;
 		//case 7: mask = 0x0020; break;
 		//case 8: mask = 0x0040; break;
@@ -88,6 +88,8 @@ void _ahb_flush_to(enum AHBDEV dev) {
 		switch(dev) {
 			// 2 to 10 in IOS, add more
 			case AHB_NAND:
+			case AHB_AES:
+			case AHB_SHA1:
 			case AHB_SDHC:
 				while((read32(HW_18C) & 0xF) == 9)
 					set32(HW_188, 0x10000);
@@ -155,6 +157,10 @@ void ahb_flush_from(enum AHBDEV dev)
 		case AHB_1:
 			req = 1;
 			break;
+		case AHB_AES:
+		case AHB_SHA1:
+			req = 2;
+			break;
 		case AHB_NAND:
 		case AHB_SDHC:
 			req = 8;
diff --git a/memory.h b/memory.h
index c583c24..60e3ffe 100644
--- a/memory.h
+++ b/memory.h
@@ -10,9 +10,11 @@
 	((typeof(x))(((u32)(x)) & (~(align-1))))
 
 enum AHBDEV {
-	AHB_STARLET = 0, //or MEM2??
-	AHB_1 = 1, //or MEM1??
+	AHB_STARLET = 0, //or MEM2 or some controller or bus or ??
+	AHB_1 = 1, //ppc or something else???
 	AHB_NAND = 3,
+	AHB_AES = 4,
+	AHB_SHA1 = 5,
 	AHB_SDHC = 9,
 };