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HW_214 = HW_VERSION
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parent
b877791528
commit
51553cd77a
@ -139,6 +139,7 @@
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#define HW_OTPCMD (HW_REG_BASE + 0x1ec)
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#define HW_OTPCMD (HW_REG_BASE + 0x1ec)
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#define HW_OTPDATA (HW_REG_BASE + 0x1f0)
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#define HW_OTPDATA (HW_REG_BASE + 0x1f0)
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#define HW_VERSION (HW_REG_BASE + 0x214)
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/* NAND Registers */
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/* NAND Registers */
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7
memory.c
7
memory.c
@ -35,7 +35,6 @@ extern u32 __page_table[4096];
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#define HW_138 (HW_REG_BASE + 0x138)
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#define HW_138 (HW_REG_BASE + 0x138)
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#define HW_188 (HW_REG_BASE + 0x188)
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#define HW_188 (HW_REG_BASE + 0x188)
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#define HW_18C (HW_REG_BASE + 0x18c)
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#define HW_18C (HW_REG_BASE + 0x18c)
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#define HW_214 (HW_REG_BASE + 0x214)
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// what is this thing doing anyway?
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// what is this thing doing anyway?
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// and why only on reads?
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// and why only on reads?
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@ -44,7 +43,7 @@ u32 _mc_read32(u32 addr)
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u32 data;
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u32 data;
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u32 tmp130 = 0;
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u32 tmp130 = 0;
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// this seems to be a bug workaround
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// this seems to be a bug workaround
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if(!(read32(HW_214) & 0xF0))
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if(!(read32(HW_VERSION) & 0xF0))
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{
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{
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tmp130 = read32(HW_130);
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tmp130 = read32(HW_130);
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write32(HW_130, tmp130 | 0x400);
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write32(HW_130, tmp130 | 0x400);
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@ -55,9 +54,9 @@ u32 _mc_read32(u32 addr)
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read32(HW_138);
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read32(HW_138);
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}
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}
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data = read32(addr);
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data = read32(addr);
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read32(HW_214); //???
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read32(HW_VERSION); //???
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if(!(read32(HW_214) & 0xF0))
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if(!(read32(HW_VERSION) & 0xF0))
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write32(HW_130, tmp130);
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write32(HW_130, tmp130);
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return data;
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return data;
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