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Add ahb stuff for SD

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marcan 2009-03-07 20:44:54 +01:00 committed by bushing
parent 526c6d3865
commit 689f718c64
3 changed files with 10 additions and 3 deletions
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4
memory.c
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@ -74,7 +74,7 @@ void _ahb_flush_to(enum AHBDEV dev) {
//case 6: mask = 0x0010; break;
//case 7: mask = 0x0020; break;
//case 8: mask = 0x0040; break;
//case 9: mask = 0x0080; break;
case AHB_SDHC: mask = 0x0080; break;
//case 10: mask = 0x0100; break;
//case 11: mask = 0x1000; break;
//case 12: mask = 0x0000; break;
@ -88,6 +88,7 @@ void _ahb_flush_to(enum AHBDEV dev) {
switch(dev) {
// 2 to 10 in IOS, add more
case AHB_NAND:
case AHB_SDHC:
while((read32(HW_18C) & 0xF) == 9)
set32(HW_188, 0x10000);
clear32(HW_188, 0x10000);
@ -155,6 +156,7 @@ void ahb_flush_from(enum AHBDEV dev)
req = 1;
break;
case AHB_NAND:
case AHB_SDHC:
req = 8;
break;
default:

1
memory.h
View File

@ -13,6 +13,7 @@ enum AHBDEV {
AHB_STARLET = 0, //or MEM2??
AHB_1 = 1, //or MEM1??
AHB_NAND = 3,
AHB_SDHC = 9,
};
void dc_flushrange(const void *start, u32 size);

8
sdhc.c
View File

@ -597,10 +597,12 @@ static s32 __sd_cmd(sdhci_t *sdhci, u32 cmd, u32 type, u32 arg, u32 blk_cnt, voi
if(use_dma == 1)
{
sdhc_debug(sdhci->reg_base, "preparing buffer for SDMA transfer");
if(mask == SDHC_BFR_WRITE_ENABLE)
if(mask == SDHC_BFR_WRITE_ENABLE) {
dc_flushrange(buffer, blk_cnt * BLOCK_SIZE);
else
ahb_flush_to(AHB_SDHC);
} else {
dc_invalidaterange(buffer, blk_cnt * BLOCK_SIZE);
}
__sd_write32(sdhci->reg_base + SDHC_SDMA_ADDR, dma_addr(buffer));
__sd_write16(sdhci->reg_base + SDHC_NORMAL_INTERRUPT_STATUS, 0);
@ -699,6 +701,8 @@ static s32 __sd_cmd(sdhci_t *sdhci, u32 cmd, u32 type, u32 arg, u32 blk_cnt, voi
sdhc_debug(sdhci->reg_base, "transfer completed. disabling interrupts again and returning.");
__sd_write16(sdhci->reg_base + SDHC_NORMAL_INTERRUPT_STATUS, INTERRUPT_TRANSFER_COMPLETE | INTERRUPT_DMA);
__sd_write16(sdhci->reg_base + SDHC_NORMAL_INTERRUPT_ENABLE, 0);
if(mask == SDHC_BFR_READ_ENABLE)
ahb_flush_from(AHB_SDHC);
return 0;
}
else if(retval & INTERRUPT_DMA)