From 8e1f68f0cb21f012df20f646a5d560e2b11b4bf3 Mon Sep 17 00:00:00 2001 From: bushing Date: Sun, 10 May 2009 23:36:36 -0700 Subject: [PATCH] trivial whitespace fixes --- boot2.c | 12 +++-- bsdtypes.h | 1 + crypto.c | 6 +-- diskio.c | 11 ---- exception.c | 3 +- gpio.h | 2 +- hollywood.h | 152 ++++++++++++++++++++++++---------------------------- integer.h | 14 ++--- ipc.c | 10 ++-- memory.c | 30 +++++------ memory.h | 7 +++ nand.h | 8 ++- powerpc.c | 4 +- powerpc.h | 4 +- 14 files changed, 123 insertions(+), 141 deletions(-) diff --git a/boot2.c b/boot2.c index f9c86cc..ee714e4 100644 --- a/boot2.c +++ b/boot2.c @@ -142,7 +142,8 @@ static inline u32 boot2_page_translate(u32 page) static int read_to(u32 bytes) { if(bytes > (valid_blocks * BLOCK_SIZE * PAGE_SIZE)) { - gecko_printf("tried to read %d boot2 bytes (%d pages), but only %d blocks (%d pages) are valid!\n", bytes, (bytes+(PAGE_SIZE-1)) / PAGE_SIZE, valid_blocks, valid_blocks * BLOCK_SIZE); + gecko_printf("tried to read %d boot2 bytes (%d pages), but only %d blocks (%d pages) are valid!\n", + bytes, (bytes+(PAGE_SIZE-1)) / PAGE_SIZE, valid_blocks, valid_blocks * BLOCK_SIZE); return -1; } while(bytes > ((u32)pages_read * PAGE_SIZE)) { @@ -186,7 +187,8 @@ int boot2_load(int copy) } mapno = find_valid_map(maps); if(mapno >= 0) { - gecko_printf("found valid boot2 blockmap at page 0x%x, submap %d, generation %d\n", page, mapno, maps[mapno].generation); + gecko_printf("found valid boot2 blockmap at page 0x%x, submap %d, generation %d\n", + page, mapno, maps[mapno].generation); if(maps[mapno].generation >= good_blockmap.generation) { memcpy(&good_blockmap, &maps[mapno], sizeof(boot2blockmap)); found = 1; @@ -270,7 +272,8 @@ int boot2_load(int copy) gecko_printf("boot2 title key: %08x%08x%08x%08x\n", kp[0], kp[1], kp[2], kp[3]); boot2_content_size = (boot2_tmd.boot_content.size + 15) & ~15; - gecko_printf("boot2 content size: 0x%x (padded: 0x%x)\n", (u32)boot2_tmd.boot_content.size, boot2_content_size); + gecko_printf("boot2 content size: 0x%x (padded: 0x%x)\n", + (u32)boot2_tmd.boot_content.size, boot2_content_size); // read content if(read_to(hdr->data_offset + boot2_content_size) < 0) { @@ -285,7 +288,7 @@ int boot2_load(int copy) return 0; } -void boot2_init() { +void boot2_init(void) { boot2_copy = -1; boot2_initialized = 0; if(boot2_load(0) < 0) { @@ -359,7 +362,6 @@ u32 boot2_ipc(volatile ipc_request *req) } else { ipc_post(req->code, req->tag, 1, -1); } - break; case IPC_BOOT2_TMD: diff --git a/bsdtypes.h b/bsdtypes.h index ec0b9f1..99f1bbe 100644 --- a/bsdtypes.h +++ b/bsdtypes.h @@ -7,6 +7,7 @@ Copyright (C) 2008, 2009 Sven Peter # This code is licensed to you under the terms of the GNU GPL, version 2; # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt */ + #ifndef __BSDTYPES_H__ #define __BSDTYPES_H__ diff --git a/crypto.c b/crypto.c index 7acf923..ffb517a 100644 --- a/crypto.c +++ b/crypto.c @@ -40,7 +40,7 @@ void crypto_read_seeprom(void) seeprom_read(&seeprom, 0, sizeof(seeprom) / 2); } -void crypto_initialize() +void crypto_initialize(void) { crypto_read_otp(); crypto_read_seeprom(); @@ -70,7 +70,7 @@ void crypto_ipc(volatile ipc_request *req) static int _aes_irq = 0; -void aes_irq() +void aes_irq(void) { _aes_irq = 1; } @@ -99,7 +99,7 @@ void aes_set_iv(u8 *iv) } } -void aes_empty_iv() +void aes_empty_iv(void) { int i; for(i = 0; i < 4; i++) diff --git a/diskio.c b/diskio.c index 87da0d3..0cde33e 100644 --- a/diskio.c +++ b/diskio.c @@ -20,7 +20,6 @@ Copyright (C) 2008, 2009 Haxx Enterprises static u8 buffer[512] MEM2_BSS ALIGNED(32); // Initialize a Drive - DSTATUS disk_initialize (BYTE drv) { if (sdmmc_check_card(SDMMC_DEFAULT_DEVICE) == SDMMC_NO_CARD) return STA_NOINIT; @@ -29,10 +28,7 @@ DSTATUS disk_initialize (BYTE drv) { return disk_status(drv); } - - // Return Disk Status - DSTATUS disk_status (BYTE drv) { (void)drv; if (sdmmc_check_card(SDMMC_DEFAULT_DEVICE) == SDMMC_INSERTED) @@ -41,10 +37,7 @@ DSTATUS disk_status (BYTE drv) { return STA_NODISK; } - - // Read Sector(s) - DRESULT disk_read (BYTE drv, BYTE *buff, DWORD sector, BYTE count) { int i; (void)drv; @@ -57,10 +50,7 @@ DRESULT disk_read (BYTE drv, BYTE *buff, DWORD sector, BYTE count) { return RES_OK; } - - // Write Sector(s) - #if _READONLY == 0 DRESULT disk_write (BYTE drv, const BYTE *buff, DWORD sector, BYTE count) { int i; @@ -84,4 +74,3 @@ DRESULT disk_ioctl (BYTE drv, BYTE ctrl, void *buff) { return RES_PARERR; } #endif /* _USE_IOCTL */ - diff --git a/exception.c b/exception.c index 1c8b67e..d99f757 100644 --- a/exception.c +++ b/exception.c @@ -18,7 +18,8 @@ Copyright (C) 2008, 2009 Haxx Enterprises #include "panic.h" const char *exceptions[] = { - "RESET", "UNDEFINED INSTR", "SWI", "INSTR ABORT", "DATA ABORT", "RESERVED", "IRQ", "FIQ", "(unknown exception type)" + "RESET", "UNDEFINED INSTR", "SWI", "INSTR ABORT", "DATA ABORT", + "RESERVED", "IRQ", "FIQ", "(unknown exception type)" }; const char *aborts[] = { diff --git a/gpio.h b/gpio.h index 433126d..ec80fc2 100644 --- a/gpio.h +++ b/gpio.h @@ -20,7 +20,7 @@ enum { GP_SLOTLED = 0x000020, GP_EJECTBTN = 0x000040, GP_SLOTIN = 0x000080, - GP_SENSORBAR = 0x000100, + GP_SENSORBAR = 0x000100, GP_DOEJECT = 0x000200, GP_EEP_CS = 0x000400, GP_EEP_CLK = 0x000800, diff --git a/hollywood.h b/hollywood.h index cc0db73..df7c0e0 100644 --- a/hollywood.h +++ b/hollywood.h @@ -17,7 +17,7 @@ Copyright (C) 2008, 2009 John Kelley /* Hollywood Registers */ #define HW_PPC_REG_BASE 0xd000000 -#define HW_REG_BASE 0xd800000 +#define HW_REG_BASE 0xd800000 // The PPC can only see the first three IPC registers #define HW_IPC_PPCMSG (HW_REG_BASE + 0x000) @@ -25,8 +25,8 @@ Copyright (C) 2008, 2009 John Kelley #define HW_IPC_ARMMSG (HW_REG_BASE + 0x008) #define HW_IPC_ARMCTRL (HW_REG_BASE + 0x00c) -#define HW_TIMER (HW_REG_BASE + 0x010) -#define HW_ALARM (HW_REG_BASE + 0x014) +#define HW_TIMER (HW_REG_BASE + 0x010) +#define HW_ALARM (HW_REG_BASE + 0x014) #define HW_PPCIRQFLAG (HW_REG_BASE + 0x030) #define HW_PPCIRQMASK (HW_REG_BASE + 0x034) @@ -34,12 +34,12 @@ Copyright (C) 2008, 2009 John Kelley #define HW_ARMIRQFLAG (HW_REG_BASE + 0x038) #define HW_ARMIRQMASK (HW_REG_BASE + 0x03c) -#define HW_MEMMIRR (HW_REG_BASE + 0x060) +#define HW_MEMMIRR (HW_REG_BASE + 0x060) // something to do with PPCBOOT // and legacy DI it seems ?!? -#define HW_EXICTRL (HW_REG_BASE + 0x070) -#define EXICTRL_ENABLE_EXI 1 +#define HW_EXICTRL (HW_REG_BASE + 0x070) +#define EXICTRL_ENABLE_EXI 1 // PPC side of GPIO1 (Starlet can access this too) // Output state @@ -47,7 +47,7 @@ Copyright (C) 2008, 2009 John Kelley // Direction (1=output) #define HW_GPIO1BDIR (HW_REG_BASE + 0x0c4) // Input state -#define HW_GPIO1BIN (HW_REG_BASE + 0x0c8) +#define HW_GPIO1BIN (HW_REG_BASE + 0x0c8) // Interrupt level #define HW_GPIO1BINTLVL (HW_REG_BASE + 0x0cc) // Interrupt flags (write 1 to clear) @@ -66,11 +66,11 @@ Copyright (C) 2008, 2009 John Kelley // Starlet side of GPIO1 // Output state -#define HW_GPIO1OUT (HW_REG_BASE + 0x0e0) +#define HW_GPIO1OUT (HW_REG_BASE + 0x0e0) // Direction (1=output) -#define HW_GPIO1DIR (HW_REG_BASE + 0x0e4) +#define HW_GPIO1DIR (HW_REG_BASE + 0x0e4) // Input state -#define HW_GPIO1IN (HW_REG_BASE + 0x0e8) +#define HW_GPIO1IN (HW_REG_BASE + 0x0e8) // Interrupt level #define HW_GPIO1INTLVL (HW_REG_BASE + 0x0ec) // Interrupt flags (write 1 to clear) @@ -83,106 +83,96 @@ Copyright (C) 2008, 2009 John Kelley #define HW_GPIO1OWNER (HW_REG_BASE + 0x0fc) // ???? -#define HW_DIFLAGS (HW_REG_BASE + 0x180) -#define DIFLAGS_BOOT_CODE 0x100000 +#define HW_DIFLAGS (HW_REG_BASE + 0x180) +#define DIFLAGS_BOOT_CODE 0x100000 // maybe a GPIO??? -#define HW_RESETS (HW_REG_BASE + 0x194) +#define HW_RESETS (HW_REG_BASE + 0x194) -#define HW_CLOCKS (HW_REG_BASE + 0x1b4) +#define HW_CLOCKS (HW_REG_BASE + 0x1b4) -#define HW_GPIO2OUT (HW_REG_BASE + 0x1c8) -#define HW_GPIO2DIR (HW_REG_BASE + 0x1cc) -#define HW_GPIO2IN (HW_REG_BASE + 0x1d0) - -#define HW_OTPCMD (HW_REG_BASE + 0x1ec) -#define HW_OTPDATA (HW_REG_BASE + 0x1f0) -#define HW_VERSION (HW_REG_BASE + 0x214) +#define HW_GPIO2OUT (HW_REG_BASE + 0x1c8) +#define HW_GPIO2DIR (HW_REG_BASE + 0x1cc) +#define HW_GPIO2IN (HW_REG_BASE + 0x1d0) +#define HW_OTPCMD (HW_REG_BASE + 0x1ec) +#define HW_OTPDATA (HW_REG_BASE + 0x1f0) +#define HW_VERSION (HW_REG_BASE + 0x214) /* NAND Registers */ -#define NAND_REG_BASE 0xd010000 - -#define NAND_CMD (NAND_REG_BASE + 0x000) -#define NAND_STATUS NAND_CMD -#define NAND_CONF (NAND_REG_BASE + 0x004) -#define NAND_ADDR0 (NAND_REG_BASE + 0x008) -#define NAND_ADDR1 (NAND_REG_BASE + 0x00c) -#define NAND_DATA (NAND_REG_BASE + 0x010) -#define NAND_ECC (NAND_REG_BASE + 0x014) -#define NAND_UNK1 (NAND_REG_BASE + 0x018) -#define NAND_UNK2 (NAND_REG_BASE + 0x01c) - +#define NAND_REG_BASE 0xd010000 +#define NAND_CMD (NAND_REG_BASE + 0x000) +#define NAND_STATUS NAND_CMD +#define NAND_CONF (NAND_REG_BASE + 0x004) +#define NAND_ADDR0 (NAND_REG_BASE + 0x008) +#define NAND_ADDR1 (NAND_REG_BASE + 0x00c) +#define NAND_DATA (NAND_REG_BASE + 0x010) +#define NAND_ECC (NAND_REG_BASE + 0x014) +#define NAND_UNK1 (NAND_REG_BASE + 0x018) +#define NAND_UNK2 (NAND_REG_BASE + 0x01c) /* AES Registers */ -#define AES_REG_BASE 0xd020000 - -#define AES_CMD (AES_REG_BASE + 0x000) -#define AES_SRC (AES_REG_BASE + 0x004) -#define AES_DEST (AES_REG_BASE + 0x008) -#define AES_KEY (AES_REG_BASE + 0x00c) -#define AES_IV (AES_REG_BASE + 0x010) - +#define AES_REG_BASE 0xd020000 +#define AES_CMD (AES_REG_BASE + 0x000) +#define AES_SRC (AES_REG_BASE + 0x004) +#define AES_DEST (AES_REG_BASE + 0x008) +#define AES_KEY (AES_REG_BASE + 0x00c) +#define AES_IV (AES_REG_BASE + 0x010) /* SHA-1 Registers */ -#define SHA_REG_BASE 0xd030000 - -#define SHA_CMD (SHA_REG_BASE + 0x000) -#define SHA_SRC (SHA_REG_BASE + 0x004) -#define SHA_H0 (SHA_REG_BASE + 0x008) -#define SHA_H1 (SHA_REG_BASE + 0x00c) -#define SHA_H2 (SHA_REG_BASE + 0x010) -#define SHA_H3 (SHA_REG_BASE + 0x014) -#define SHA_H4 (SHA_REG_BASE + 0x018) - +#define SHA_REG_BASE 0xd030000 +#define SHA_CMD (SHA_REG_BASE + 0x000) +#define SHA_SRC (SHA_REG_BASE + 0x004) +#define SHA_H0 (SHA_REG_BASE + 0x008) +#define SHA_H1 (SHA_REG_BASE + 0x00c) +#define SHA_H2 (SHA_REG_BASE + 0x010) +#define SHA_H3 (SHA_REG_BASE + 0x014) +#define SHA_H4 (SHA_REG_BASE + 0x018) /* SD Host Controller Registers */ -#define SDHC_REG_BASE 0xd070000 +#define SDHC_REG_BASE 0xd070000 /* EXI Registers */ -#define EXI_REG_BASE 0xd806800 -#define EXI0_REG_BASE (EXI_REG_BASE+0x000) -#define EXI1_REG_BASE (EXI_REG_BASE+0x014) -#define EXI2_REG_BASE (EXI_REG_BASE+0x028) +#define EXI_REG_BASE 0xd806800 +#define EXI0_REG_BASE (EXI_REG_BASE+0x000) +#define EXI1_REG_BASE (EXI_REG_BASE+0x014) +#define EXI2_REG_BASE (EXI_REG_BASE+0x028) -#define EXI0_CSR (EXI0_REG_BASE+0x000) -#define EXI0_MAR (EXI0_REG_BASE+0x004) -#define EXI0_LENGTH (EXI0_REG_BASE+0x008) -#define EXI0_CR (EXI0_REG_BASE+0x00c) -#define EXI0_DATA (EXI0_REG_BASE+0x010) +#define EXI0_CSR (EXI0_REG_BASE+0x000) +#define EXI0_MAR (EXI0_REG_BASE+0x004) +#define EXI0_LENGTH (EXI0_REG_BASE+0x008) +#define EXI0_CR (EXI0_REG_BASE+0x00c) +#define EXI0_DATA (EXI0_REG_BASE+0x010) -#define EXI1_CSR (EXI1_REG_BASE+0x000) -#define EXI1_MAR (EXI1_REG_BASE+0x004) -#define EXI1_LENGTH (EXI1_REG_BASE+0x008) -#define EXI1_CR (EXI1_REG_BASE+0x00c) -#define EXI1_DATA (EXI1_REG_BASE+0x010) - -#define EXI2_CSR (EXI2_REG_BASE+0x000) -#define EXI2_MAR (EXI2_REG_BASE+0x004) -#define EXI2_LENGTH (EXI2_REG_BASE+0x008) -#define EXI2_CR (EXI2_REG_BASE+0x00c) -#define EXI2_DATA (EXI2_REG_BASE+0x010) - -#define EXI_BOOT_BASE (EXI_REG_BASE+0x040) +#define EXI1_CSR (EXI1_REG_BASE+0x000) +#define EXI1_MAR (EXI1_REG_BASE+0x004) +#define EXI1_LENGTH (EXI1_REG_BASE+0x008) +#define EXI1_CR (EXI1_REG_BASE+0x00c) +#define EXI1_DATA (EXI1_REG_BASE+0x010) +#define EXI2_CSR (EXI2_REG_BASE+0x000) +#define EXI2_MAR (EXI2_REG_BASE+0x004) +#define EXI2_LENGTH (EXI2_REG_BASE+0x008) +#define EXI2_CR (EXI2_REG_BASE+0x00c) +#define EXI2_DATA (EXI2_REG_BASE+0x010) +#define EXI_BOOT_BASE (EXI_REG_BASE+0x040) /* MEMORY CONTROLLER Registers */ -#define MEM_REG_BASE 0xd8b4000 -#define MEM_PROT (MEM_REG_BASE+0x20a) -#define MEM_PROT_START (MEM_REG_BASE+0x20c) -#define MEM_PROT_END (MEM_REG_BASE+0x20e) -#define MEM_FLUSHREQ (MEM_REG_BASE+0x228) -#define MEM_FLUSHACK (MEM_REG_BASE+0x22a) +#define MEM_REG_BASE 0xd8b4000 +#define MEM_PROT (MEM_REG_BASE+0x20a) +#define MEM_PROT_START (MEM_REG_BASE+0x20c) +#define MEM_PROT_END (MEM_REG_BASE+0x20e) +#define MEM_FLUSHREQ (MEM_REG_BASE+0x228) +#define MEM_FLUSHACK (MEM_REG_BASE+0x22a) #endif - diff --git a/integer.h b/integer.h index 1d6bac3..cc55ee7 100644 --- a/integer.h +++ b/integer.h @@ -4,34 +4,28 @@ #ifndef _INTEGER -#if 0 -#include -#else - /* These types must be 16-bit, 32-bit or larger integer */ -typedef int INT; +typedef int INT; typedef unsigned int UINT; /* These types must be 8-bit integer */ -typedef signed char CHAR; +typedef signed char CHAR; typedef unsigned char UCHAR; typedef unsigned char BYTE; /* These types must be 16-bit integer */ -typedef short SHORT; +typedef short SHORT; typedef unsigned short USHORT; typedef unsigned short WORD; typedef unsigned short WCHAR; /* These types must be 32-bit integer */ -typedef long LONG; +typedef long LONG; typedef unsigned long ULONG; typedef unsigned long DWORD; /* Boolean type */ typedef enum { FALSE = 0, TRUE } BOOL; -#endif - #define _INTEGER #endif diff --git a/ipc.c b/ipc.c index ca77b1c..573af11 100644 --- a/ipc.c +++ b/ipc.c @@ -40,17 +40,17 @@ extern char __mem2_area_start[]; // These defines are for the ARMCTRL regs // See http://wiibrew.org/wiki/Hardware/IPC -#define IPC_CTRL_Y1 0x01 -#define IPC_CTRL_X2 0x02 -#define IPC_CTRL_X1 0x04 -#define IPC_CTRL_Y2 0x08 +#define IPC_CTRL_Y1 0x01 +#define IPC_CTRL_X2 0x02 +#define IPC_CTRL_X1 0x04 +#define IPC_CTRL_Y2 0x08 #define IPC_CTRL_IX1 0x10 #define IPC_CTRL_IX2 0x20 // Our definitions for this IPC interface #define IPC_CTRL_OUT IPC_CTRL_Y1 -#define IPC_CTRL_IN IPC_CTRL_X1 +#define IPC_CTRL_IN IPC_CTRL_X1 #define IPC_CTRL_IRQ_IN IPC_CTRL_IX1 // reset both flags (X* for ARM and Y* for PPC) diff --git a/memory.c b/memory.c index 9af19ed..5535da1 100644 --- a/memory.c +++ b/memory.c @@ -38,21 +38,21 @@ void _tlb_inval(void); #define CR_ICACHE (1 << 12) // TODO: move to hollywood.h once we figure out WTF -#define HW_100 (HW_REG_BASE + 0x100) -#define HW_104 (HW_REG_BASE + 0x104) -#define HW_108 (HW_REG_BASE + 0x108) -#define HW_10c (HW_REG_BASE + 0x10c) -#define HW_110 (HW_REG_BASE + 0x110) -#define HW_114 (HW_REG_BASE + 0x114) -#define HW_118 (HW_REG_BASE + 0x118) -#define HW_11c (HW_REG_BASE + 0x11c) -#define HW_120 (HW_REG_BASE + 0x120) -#define HW_124 (HW_REG_BASE + 0x124) -#define HW_130 (HW_REG_BASE + 0x130) -#define HW_134 (HW_REG_BASE + 0x134) -#define HW_138 (HW_REG_BASE + 0x138) -#define HW_188 (HW_REG_BASE + 0x188) -#define HW_18C (HW_REG_BASE + 0x18c) +#define HW_100 (HW_REG_BASE + 0x100) +#define HW_104 (HW_REG_BASE + 0x104) +#define HW_108 (HW_REG_BASE + 0x108) +#define HW_10c (HW_REG_BASE + 0x10c) +#define HW_110 (HW_REG_BASE + 0x110) +#define HW_114 (HW_REG_BASE + 0x114) +#define HW_118 (HW_REG_BASE + 0x118) +#define HW_11c (HW_REG_BASE + 0x11c) +#define HW_120 (HW_REG_BASE + 0x120) +#define HW_124 (HW_REG_BASE + 0x124) +#define HW_130 (HW_REG_BASE + 0x130) +#define HW_134 (HW_REG_BASE + 0x134) +#define HW_138 (HW_REG_BASE + 0x138) +#define HW_188 (HW_REG_BASE + 0x188) +#define HW_18C (HW_REG_BASE + 0x18c) #ifdef CAN_HAZ_IRQ #define IRQ_PREAMBLE u32 cookie = irq_kill(); diff --git a/memory.h b/memory.h index 5299e90..43a97e1 100644 --- a/memory.h +++ b/memory.h @@ -48,26 +48,31 @@ static inline u32 get_cr(void) __asm__ volatile ( "mrc\tp15, 0, %0, c1, c0, 0" : "=r" (data) ); return data; } + static inline u32 get_ttbr(void) { u32 data; __asm__ volatile ( "mrc\tp15, 0, %0, c2, c0, 0" : "=r" (data) ); return data; } + static inline u32 get_dacr(void) { u32 data; __asm__ volatile ( "mrc\tp15, 0, %0, c3, c0, 0" : "=r" (data) ); return data; } + static inline void set_cr(u32 data) { __asm__ volatile ( "mcr\tp15, 0, %0, c1, c0, 0" :: "r" (data) ); } + static inline void set_ttbr(u32 data) { __asm__ volatile ( "mcr\tp15, 0, %0, c2, c0, 0" :: "r" (data) ); } + static inline void set_dacr(u32 data) { __asm__ volatile ( "mcr\tp15, 0, %0, c3, c0, 0" :: "r" (data) ); @@ -79,12 +84,14 @@ static inline u32 get_dfsr(void) __asm__ volatile ( "mrc\tp15, 0, %0, c5, c0, 0" : "=r" (data) ); return data; } + static inline u32 get_ifsr(void) { u32 data; __asm__ volatile ( "mrc\tp15, 0, %0, c5, c0, 1" : "=r" (data) ); return data; } + static inline u32 get_far(void) { u32 data; diff --git a/nand.h b/nand.h index 4941cb2..205e73a 100644 --- a/nand.h +++ b/nand.h @@ -15,11 +15,11 @@ Copyright (C) 2008, 2009 Sven Peter #include "types.h" #include "ipc.h" -#define PAGE_SIZE 2048 +#define PAGE_SIZE 2048 #define PAGE_SPARE_SIZE 64 #define ECC_BUFFER_SIZE (PAGE_SPARE_SIZE+16) #define ECC_BUFFER_ALLOC (PAGE_SPARE_SIZE+32) -#define BLOCK_SIZE 64 +#define BLOCK_SIZE 64 #define NAND_MAX_PAGE 0x40000 void nand_irq(void); @@ -40,9 +40,7 @@ void nand_read_cluster(u32 clusterno, void *data); #define NAND_ECC_UNCORRECTABLE -1 int nand_correct(u32 pageno, void *data, void *ecc); - -void nand_initialize(); - +void nand_initialize(void); void nand_ipc(volatile ipc_request *req); #endif diff --git a/powerpc.c b/powerpc.c index 0bee6ca..fc15e85 100644 --- a/powerpc.c +++ b/powerpc.c @@ -46,7 +46,7 @@ void powerpc_upload_stub(u32 entry) clear32(HW_EXICTRL, EXICTRL_ENABLE_EXI); } -void powerpc_hang() +void powerpc_hang(void) { clear32(HW_RESETS, 0x30); udelay(100); @@ -54,7 +54,7 @@ void powerpc_hang() udelay(100); } -void powerpc_reset() +void powerpc_reset(void) { // enable the broadway IPC interrupt write32(HW_PPCIRQMASK, (1<<30)); diff --git a/powerpc.h b/powerpc.h index f8ffdce..ba5b45c 100644 --- a/powerpc.h +++ b/powerpc.h @@ -15,8 +15,8 @@ Copyright (C) 2009 Andre Heider "dhewg" #include "ipc.h" void powerpc_upload_stub(u32 entry); -void powerpc_hang(); -void powerpc_reset(); +void powerpc_hang(void); +void powerpc_reset(void); void powerpc_ipc(volatile ipc_request *req); #endif