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merge: sdhcreg.h

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bushing 2009-05-05 19:28:58 -07:00
parent 4e6b0d3a78
commit 9bc2a5023a
1 changed files with 100 additions and 117 deletions
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27
sdhcreg.h
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@ -19,15 +19,6 @@
#ifndef _SDHCREG_H_ #ifndef _SDHCREG_H_
#define _SDHCREG_H_ #define _SDHCREG_H_
/* PCI base address registers */
#define SDHC_PCI_BAR_START PCI_MAPREG_START
#define SDHC_PCI_BAR_END PCI_MAPREG_END
/* PCI interface classes */
#define SDHC_PCI_INTERFACE_NO_DMA 0x00
#define SDHC_PCI_INTERFACE_DMA 0x01
#define SDHC_PCI_INTERFACE_VENDOR 0x02
/* Host standard register set */ /* Host standard register set */
#define SDHC_DMA_ADDR 0x00 #define SDHC_DMA_ADDR 0x00
#define SDHC_BLOCK_SIZE 0x04 #define SDHC_BLOCK_SIZE 0x04
@ -118,22 +109,25 @@
#define SDHC_COMMAND_COMPLETE (1<<0) #define SDHC_COMMAND_COMPLETE (1<<0)
#define SDHC_NINTR_STATUS_MASK 0x81ff #define SDHC_NINTR_STATUS_MASK 0x81ff
#define SDHC_EINTR_STATUS 0x32 #define SDHC_EINTR_STATUS 0x32
#define SDHC_ADMA_ERROR (1<<9)
#define SDHC_AUTO_CMD12_ERROR (1<<8) #define SDHC_AUTO_CMD12_ERROR (1<<8)
#define SDHC_CURRENT_LIMIT_ERROR (1<<7) #define SDHC_CURRENT_LIMIT_ERROR (1<<7)
#define SDHC_DATA_END_BIT_ERROR (1<<6) #define SDHC_DATA_END_BIT_ERROR (1<<6)
#define SDHC_DATA_CRC_ERROR (1<<5) #define SDHC_DATA_CRC_ERROR (1<<5)
#define SDHC_DATA_TIMEOUT_ERROR (1<<4) #define SDHC_DATA_TIMEOUT_ERROR (1<<4)
#define SDHC_DATA_ERROR 0x70
#define SDHC_CMD_INDEX_ERROR (1<<3) #define SDHC_CMD_INDEX_ERROR (1<<3)
#define SDHC_CMD_END_BIT_ERROR (1<<2) #define SDHC_CMD_END_BIT_ERROR (1<<2)
#define SDHC_CMD_CRC_ERROR (1<<1) #define SDHC_CMD_CRC_ERROR (1<<1)
#define SDHC_CMD_TIMEOUT_ERROR (1<<0) #define SDHC_CMD_TIMEOUT_ERROR (1<<0)
#define SDHC_EINTR_STATUS_MASK 0x01ff /* excluding vendor signals */ #define SDHC_CMD_ERROR 0x0f
#define SDHC_EINTR_STATUS_MASK 0x03ff /* excluding vendor signals */
#define SDHC_NINTR_STATUS_EN 0x34 #define SDHC_NINTR_STATUS_EN 0x34
#define SDHC_EINTR_STATUS_EN 0x36 #define SDHC_EINTR_STATUS_EN 0x36
#define SDHC_NINTR_SIGNAL_EN 0x38 #define SDHC_NINTR_SIGNAL_EN 0x38
#define SDHC_NINTR_SIGNAL_MASK 0x01ff #define SDHC_NINTR_SIGNAL_MASK 0x01ff
#define SDHC_EINTR_SIGNAL_EN 0x3a #define SDHC_EINTR_SIGNAL_EN 0x3a
#define SDHC_EINTR_SIGNAL_MASK 0x01ff /* excluding vendor signals */ #define SDHC_EINTR_SIGNAL_MASK 0x03ff /* excluding vendor signals */
#define SDHC_CMD12_ERROR_STATUS 0x3c #define SDHC_CMD12_ERROR_STATUS 0x3c
#define SDHC_CAPABILITIES 0x40 #define SDHC_CAPABILITIES 0x40
#define SDHC_VOLTAGE_SUPP_1_8V (1<<26) #define SDHC_VOLTAGE_SUPP_1_8V (1<<26)
@ -175,15 +169,4 @@
#define SDHC_VENDOR_VERSION(hcv) \ #define SDHC_VENDOR_VERSION(hcv) \
(((hcv) >> SDHC_VENDOR_VERS_SHIFT) & SDHC_VENDOR_VERS_MASK) (((hcv) >> SDHC_VENDOR_VERS_SHIFT) & SDHC_VENDOR_VERS_MASK)
#define SDHC_PRESENT_STATE_BITS \
"\20\31CL\30D3L\27D2L\26D1L\25D0L\24WPS\23CD\22CSS\21CI" \
"\14BRE\13BWE\12RTA\11WTA\3DLA\2CID\1CIC"
#define SDHC_NINTR_STATUS_BITS \
"\20\20ERROR\11CARD\10REMOVAL\7INSERTION\6READ\5WRITE" \
"\4DMA\3GAP\2XFER\1CMD"
#define SDHC_EINTR_STATUS_BITS \
"\20\11ACMD12\10CL\7DEB\6DCRC\5DT\4CI\3CEB\2CCRC\1CT"
#define SDHC_CAPABILITIES_BITS \
"\20\33Vdd1.8V\32Vdd3.0V\31Vdd3.3V\30SUSPEND\27DMA\26HIGHSPEED"
#endif #endif