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https://github.com/fail0verflow/mini.git
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Fix horrible stack and CPSR problems
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parent
f0edf39096
commit
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13
irq_asm.S
13
irq_asm.S
@ -11,16 +11,13 @@
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irq_setup_stack:
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@ Switch to IRQ mode
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mrs r0, cpsr
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bic r1, r0, #0x1f
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orr r1, #0x12
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msr cpsr, r1
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msr cpsr_c, #0xd2
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@ Setup interrupt stack
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ldr sp, =__stack_addr
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add sp, r4
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ldr sp, =__irqstack_addr
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@ Restore mode
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msr cpsr, r0
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msr cpsr_c, r0
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bx lr
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v_irq:
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@ -35,12 +32,12 @@ irq_kill:
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mrs r1, cpsr
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and r0, r1, #(CPSR_IRQDIS|CPSR_FIQDIS)
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orr r1, r1, #(CPSR_IRQDIS|CPSR_FIQDIS)
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msr cpsr, r1
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msr cpsr_c, r1
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bx lr
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irq_restore:
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mrs r1, cpsr
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bic r1, r1, #(CPSR_IRQDIS|CPSR_FIQDIS)
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orr r1, r1, r0
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msr cpsr, r1
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msr cpsr_c, r1
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bx lr
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8
start.S
8
start.S
@ -29,6 +29,9 @@ _start:
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.pool
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v_reset:
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@ Switch to System mode
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msr cpsr_c, #0xdf
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@ Get loader base from ELF loader
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mov r4, r0
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@ -38,13 +41,10 @@ v_reset:
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@ Set up a stack
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ldr sp, =__stack_addr
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add sp, r4
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@ clear BSS
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ldr r1, =__bss_start
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add r1, r4
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ldr r2, =__bss_end
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add r2, r4
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mov r3, #0
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bss_loop:
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@ check for the end
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@ -58,9 +58,7 @@ bss_loop:
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done_bss:
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@ clear BSS2
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ldr r1, =__bss2_start
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add r1, r4
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ldr r2, =__bss2_end
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add r2, r4
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mov r3, #0
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bss2_loop:
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@ check for the end
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