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https://github.com/fail0verflow/mini.git
synced 2024-11-30 23:24:19 +01:00
removed some sd debug stuff
This commit is contained in:
Sven Peter
bushing
parent
3e758bdfcf
commit
a02074a8ae
81
sdhc.c
81
sdhc.c
@ -343,7 +343,6 @@ static void __sd_dumpregs(sdhci_t *sdhci)
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static int __sd_reset(sdhci_t *sdhci, int all)
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{
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u32 caps;
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int retval;
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u32 mask;
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@ -362,10 +361,7 @@ static int __sd_reset(sdhci_t *sdhci, int all)
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mask = SDHC_SOFTWARE_RESET_CMD | SDHC_SOFTWARE_RESET_DAT;
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sdhc_error(sdhci->reg_base, "resetting card (mask = %x)", mask);
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sdhc_debug(sdhci->reg_base, "software reset register: %02x", __sd_read8(sdhci->reg_base + SDHC_SOFTWARE_RESET));
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__sd_write8(sdhci->reg_base + SDHC_SOFTWARE_RESET, mask);
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sdhc_debug(sdhci->reg_base, "software reset register: %02x", __sd_read8(sdhci->reg_base + SDHC_SOFTWARE_RESET));
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sdhc_debug(sdhci->reg_base, "waiting for reset bit to be unset");
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retval = __sd_wait8_r(sdhci->reg_base + SDHC_SOFTWARE_RESET, mask);
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if(retval < 0)
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@ -380,9 +376,6 @@ static int __sd_reset(sdhci_t *sdhci, int all)
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__sd_dumpregs(sdhci);
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__sd_write8(sdhci->reg_base + SDHC_TIMEOUT_CONTROL, SDHC_TIMEOUT_MAX);
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caps = __sd_read32(sdhci->reg_base + SDHC_CAPABILITIES);
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sdhc_debug(sdhci->reg_base, "capabilites: %X", caps);
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return 0;
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}
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@ -408,16 +401,12 @@ static int __sd_clock(sdhci_t *sdhci, u8 enable, u32 freq)
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return 0;
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caps = read32(sdhci->reg_base + SDHC_CAPABILITIES);
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sdhc_debug(sdhci->reg_base, "capabilites: %X", caps);
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if(SDHC_BFREQ_KHZ(caps) != 0)
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d = __sd_clock_div(SDHC_BFREQ_KHZ(caps), freq);
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else
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d = 256 / 2;
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sdhc_debug(sdhci->reg_base, "using a clock divisor of %d to archieve a speed of %d kHz (base = %d)", 2*d, SDHC_BFREQ_KHZ(caps) / (2 * d), SDHC_BFREQ_KHZ(caps));
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sdhc_debug(sdhci->reg_base, " -> clock_control = %X", (d << 8) | SDHC_CLOCK_INTERNAL_ENABLE);
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__sd_write16(sdhci->reg_base + SDHC_CLOCK_CONTROL, (d << 8) | SDHC_CLOCK_INTERNAL_ENABLE);
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__sd_dumpregs(sdhci);
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@ -460,7 +449,7 @@ static int __sd_power(sdhci_t *sdhci, int vdd)
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if(!(caps & vdd))
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{
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sdhc_debug(sdhci->reg_base, "voltage %x not supported by the hc");
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sdhc_error(sdhci->reg_base, "voltage %x not supported by the hc");
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return SDHC_EINVAL;
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}
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@ -478,14 +467,12 @@ static int __sd_power(sdhci_t *sdhci, int vdd)
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pwr |= SDHC_PCTRL_VOLTAGE_18;
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break;
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default:
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sdhc_debug(sdhci->reg_base, "invalid vdd: %x", vdd);
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sdhc_error(sdhci->reg_base, "invalid vdd: %x", vdd);
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return SDHC_EINVAL;
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}
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sdhc_debug(sdhci->reg_base, "writing %02x to power control", pwr);
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__sd_write8(sdhci->reg_base + SDHC_POWER_CONTROL, pwr);
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pwr |= SDHC_PCTRL_ENABLE;
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sdhc_debug(sdhci->reg_base, "writing %02x to power control", pwr);
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__sd_write8(sdhci->reg_base + SDHC_POWER_CONTROL, pwr);
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__sd_dumpregs(sdhci);
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@ -510,16 +497,11 @@ static s32 __sd_cmd(sdhci_t *sdhci, u32 cmd, u32 type, u32 arg, u32 blk_cnt, voi
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int retval;
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int i, imax;
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u32 caps;
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#if 0 /* only needed for PIO which is currently broken */
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u8 *ptr;
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int len;
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#endif
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if(cmd & SD_CMD_ACMD)
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{
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sdhc_debug(sdhci->reg_base, " cmd %X is ACMD%d, sending CMD55 first", cmd, cmd - SD_CMD_ACMD);
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retval = __sd_cmd(sdhci, SD_CMD_APP, SD_R1, sdhci->rca << 16, 0, NULL, NULL, 0);
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sdhc_debug(sdhci->reg_base, " CMD55: retval = %d", retval);
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// TODO: also check the response here?
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if(retval < 0)
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return retval;
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@ -533,7 +515,7 @@ static s32 __sd_cmd(sdhci_t *sdhci, u32 cmd, u32 type, u32 arg, u32 blk_cnt, voi
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if(blk_cnt > SDHC_BLOCKS_MAX)
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{
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sdhc_debug(sdhci->reg_base, "%d blocks are too much...", blk_cnt);
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sdhc_error(sdhci->reg_base, "%d blocks are too much...", blk_cnt);
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return SDHC_EOVERFLOW;
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}
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@ -549,7 +531,6 @@ static s32 __sd_cmd(sdhci_t *sdhci, u32 cmd, u32 type, u32 arg, u32 blk_cnt, voi
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command = (cmd & SDHC_CMD_MASK) << SDHC_CMD_SHIFT;
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if(blk_cnt > 0)
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{
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sdhc_debug(sdhci->reg_base, "block count is > 0; setting up mode register");
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if(use_dma == 1)
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mode |= SDHC_CMDMODE_DMA_ENABLE;
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mode |= SDHC_CMDMODE_MULTIBLOCK;
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@ -557,13 +538,11 @@ static s32 __sd_cmd(sdhci_t *sdhci, u32 cmd, u32 type, u32 arg, u32 blk_cnt, voi
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mode |= SDHC_CMDMODE_BLOCKCNT_ENABLE;
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if(type & SD_READ)
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{
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sdhc_debug(sdhci->reg_base, "read operation");
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mask = SDHC_BFR_READ_ENABLE;
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mode |= SDHC_CMDMODE_READ;
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}
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else
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{
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sdhc_debug(sdhci->reg_base, "write operation");
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mask = SDHC_BFR_WRITE_ENABLE;
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mode |= SDHC_CMDMODE_WRITE;
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}
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@ -587,7 +566,6 @@ static s32 __sd_cmd(sdhci_t *sdhci, u32 cmd, u32 type, u32 arg, u32 blk_cnt, voi
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command |= SDHC_CMD_IDXCHECK;
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sdhc_debug(sdhci->reg_base, "command = %X, mode = %X", command, mode);
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sdhc_debug(sdhci->reg_base, "waiting for command inhibit bits to be cleared..");
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retval = __sd_wait32_r(sdhci->reg_base + SDHC_PRESENT_STATE, SDHC_PRESENT_CMD_INHIBIT_BOTH);
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@ -620,7 +598,6 @@ static s32 __sd_cmd(sdhci_t *sdhci, u32 cmd, u32 type, u32 arg, u32 blk_cnt, voi
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if(blk_cnt > 0)
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{
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sdhc_debug(sdhci->reg_base, "writing bsize = %x, bcount = %x", BLOCK_SIZE, blk_cnt);
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__sd_write16(sdhci->reg_base + SDHC_BLOCK_SIZE, (BLOCK_SIZE_512K << 12) | BLOCK_SIZE);
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__sd_write16(sdhci->reg_base + SDHC_BLOCK_COUNT, blk_cnt);
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}
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@ -628,12 +605,8 @@ static s32 __sd_cmd(sdhci_t *sdhci, u32 cmd, u32 type, u32 arg, u32 blk_cnt, voi
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sdhc_debug(sdhci->reg_base, "writing mode = %x, arg = %x, cmd = %x", mode, arg, command);
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__sd_write32(sdhci->reg_base + SDHC_CMD_ARG, arg);
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// just don't ask....
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__sd_write32(sdhci->reg_base + SDHC_CMD_TRANSFER_MODE, ((u32)command << 16) | mode);
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sdhc_debug(sdhci->reg_base, "writing %08x to %x", ((u32)command << 16) | mode, SDHC_CMD_TRANSFER_MODE);
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sdhc_debug(sdhci->reg_base, "mode = %x", __sd_read16(sdhci->reg_base + SDHC_CMD_TRANSFER_MODE));
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__sd_dumpregs(sdhci);
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sdhc_debug(sdhci->reg_base, "waiting until command phase is done");
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retval = __sd_wait32_r(sdhci->reg_base + SDHC_PRESENT_STATE, SDHC_PRESENT_CMD_INHIBIT_CMD);
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@ -673,7 +646,6 @@ static s32 __sd_cmd(sdhci_t *sdhci, u32 cmd, u32 type, u32 arg, u32 blk_cnt, voi
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response[0] = __sd_read32(sdhci->reg_base + SDHC_RESPONSE);
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sdhc_debug(sdhci->reg_base, "response = %08X", response[0]);
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}
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sdhc_debug(sdhci->reg_base, "copied response to buffer");
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}
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// FIXME: check response and abort on errors?
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@ -686,52 +658,12 @@ static s32 __sd_cmd(sdhci_t *sdhci, u32 cmd, u32 type, u32 arg, u32 blk_cnt, voi
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gecko_printf("sdhci: PIO mode is broken, align your buffer and use DMA.\n");
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__sd_reset(sdhci, 0);
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return SDHC_EIO;
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#if 0
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sdhc_debug(sdhci->reg_base, "using data port buffer to read/write data");
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len = blk_cnt * BLOCK_SIZE; // as long as BLOCK_SIZE % 4 == 0 len % 4 is (obviously) also 0; this will crash and burn otherwise!!
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ptr = (u8 *)buffer;
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while(len > 0)
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{
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if(len % BLOCK_SIZE == 0)
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{
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sdhc_debug(sdhci->reg_base, "starting to work on the next block; bytes left = %d", len);
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sdhc_debug(sdhci->reg_base, "waiting for data read/write enable bits to be set");
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retval = __sd_wait32(sdhci->reg_base + SDHC_PRESENT_STATE, mask);
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if(retval < 0)
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{
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// FIXME: error handling!!
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sdhc_debug(sdhci->reg_base, "timed out");
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sdhc_debug(sdhci->reg_base, "present state = %08x", __sd_read32(sdhci->reg_base + SDHC_PRESENT_STATE));
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__sd_dumpregs(sdhci);
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return retval;
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}
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sdhc_debug(sdhci->reg_base, "data read/write enable bits are set");
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}
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if(mask == SDHC_BFR_READ_ENABLE)
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*(u32 *)ptr = __sd_read32(sdhci->reg_base + SDHC_DATA);
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else
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__sd_write32(sdhci->reg_base + SDHC_DATA, *(u32 *)ptr);
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ptr += 4;
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len -= 4;
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}
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sdhc_debug(sdhci->reg_base, "all data transferred");
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sdhc_debug(sdhci->reg_base, "waiting.."); // FIXME: interrupts should be used here, don't even know if this works
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//if(mask == SDHC_BFR_READ_ENABLE)
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// while(__sd_read32(sdhci->reg_base + SDHC_PRESENT_STATE) & (1 << 9));
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//else
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// while(__sd_read32(sdhci->reg_base + SDHC_PRESENT_STATE) & (1 << 2));
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sdhc_debug(sdhci->reg_base, "done");
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#endif
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}
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else /* SDMA; transfer data in 512 KB blocks (i.e. 1024 512 byte blocks */
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{
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u8 *ptr = (u8 *)buffer;
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sdhc_debug(sdhci->reg_base, "using SDMA to transfer data");
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// poor man's interrupts
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while(1)
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{
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sdhc_debug(sdhci->reg_base, "waiting for interrupts...");
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@ -783,7 +715,6 @@ static s32 __sd_cmd(sdhci_t *sdhci, u32 cmd, u32 type, u32 arg, u32 blk_cnt, voi
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void __sd_print_status(sdhci_t *sdhci)
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{
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return;
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#ifdef SDHC_DEBUG
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u32 status;
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u32 state;
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@ -846,6 +777,7 @@ void __sd_print_status(sdhci_t *sdhci)
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}
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#endif
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return;
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}
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int sd_mount(sdhci_t *sdhci)
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@ -873,7 +805,6 @@ int sd_mount(sdhci_t *sdhci)
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if(retval < 0)
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return retval;
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sdhc_debug(sdhci->reg_base, "resetting card");
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retval = __sd_cmd(sdhci, SD_CMD_RESET_CARD, SD_R0, 0x0, 0, NULL, NULL, 0);
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if(retval < 0)
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return retval;
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@ -904,7 +835,7 @@ int sd_mount(sdhci_t *sdhci)
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else
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{
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// SDHC card deteced
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sdhc_debug(sdhci->reg_base, "SDv2 card detected.");
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sdhc_error(sdhci->reg_base, "SDv2 card detected.");
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sdhci->is_sdhc = 1;
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sdhci->ocr = OCR_HCS;
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}
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@ -922,9 +853,7 @@ int sd_mount(sdhci_t *sdhci)
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resp[0] = 0;
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while(tries++ <= SDHC_WAIT_TIMEOUT_OUTER_MULTIPLY)
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{
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sdhc_debug(sdhci->reg_base, "attemp %d", tries);
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retval = __sd_cmd(sdhci, SD_CMD_APP_SEND_OP_COND, SD_R3, sdhci->ocr, 0, NULL, resp, 6);
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sdhc_debug(sdhci->reg_base, " retval = %d, response = %08X", retval, resp[0]);
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if(resp[0] & OCR_POWERUP_STATUS)
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{
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sdhc_debug(sdhci->reg_base, "card power up is done.");
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