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sdhc seems to work now :>
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parent
5ba315148b
commit
b84f393c92
21
sdhc.c
21
sdhc.c
@ -675,7 +675,7 @@ sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
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* If the command has data to transfer in any direction,
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* execute the transfer now.
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*/
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if (cmd->c_error == 0 && cmd->c_data != NULL)
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if (cmd->c_error == 0 && cmd->c_datalen > 0)
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sdhc_transfer_data(hp, cmd);
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/* Turn off the LED. */
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@ -789,7 +789,7 @@ sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd)
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* Start a CPU data transfer. Writing to the high order byte
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* of the SDHC_COMMAND register triggers the SD command. (1.5)
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*/
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HWRITE2(hp, SDHC_BLOCK_SIZE, blksize);
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HWRITE2(hp, SDHC_BLOCK_SIZE, blksize | 7<<12);
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if (blkcount > 0)
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HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount);
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HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg);
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@ -804,8 +804,7 @@ sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd)
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void
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sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd)
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{
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u_char *datap = cmd->c_data;
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int i, datalen;
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int datalen;
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int mask;
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int error;
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int status;
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@ -815,7 +814,7 @@ sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd)
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SDHC_BUFFER_READ_ENABLE : SDHC_BUFFER_WRITE_ENABLE;
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error = 0;
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datalen = cmd->c_datalen;
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blkcnt = (cmd->c_datalen / 512);
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blkcnt = (datalen / 512);
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DPRINTF(1,("%s: resp=%#x datalen=%d\n", HDEVNAME(hp),
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MMC_R1(cmd->c_resp), datalen));
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@ -833,13 +832,13 @@ sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd)
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left = HREAD2(hp, SDHC_BLOCK_COUNT);
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DPRINTF(2,("%s: dma left:%#x\n", HDEVNAME(hp),
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left));
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cmd->c_buf = cmd->c_data + (blkcnt - left)*512;
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// FIXME: why do we need -0x200 here?
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cmd->c_buf = cmd->c_data + cmd->c_datalen - left*512 - 0x200;
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HWRITE4(hp, SDHC_DMA_ADDR,
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dma_addr(cmd->c_buf));
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continue;
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}
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if (ISSET(status, SDHC_TRANSFER_COMPLETE)) {
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gecko_printf("transfer complete!\n");
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break;
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}
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}
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@ -975,12 +974,12 @@ sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo)
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status = hp->intr_status & mask;
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for (timo = 1000; timo > 0; timo--) {
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for (timo = 500; timo > 0; timo--) {
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if (hp->intr_status != 0) {
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status = hp->intr_status & mask;
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break;
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}
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sdmmc_delay(10);
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sdmmc_delay(1000);
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}
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if (timo == 0) {
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status |= SDHC_ERROR_INTERRUPT;
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@ -1063,7 +1062,7 @@ sdhc_intr(void *arg)
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memset(&req, 0, sizeof(req));
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req.device = IPC_DEV_SDHC;
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req.req = IPC_SDHC_DISCOVER;
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req.args[0] = hp->sdmmc;
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req.args[0] = (u32)hp->sdmmc;
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ipc_add_slow(&req);
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}
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@ -1073,7 +1072,7 @@ sdhc_intr(void *arg)
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*/
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if (ISSET(status, SDHC_BUFFER_READ_READY|
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SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE|
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SDHC_TRANSFER_COMPLETE)) {
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SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) {
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hp->intr_status |= status;
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wakeup(&hp->intr_status);
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}
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14
sdmmc.c
14
sdmmc.c
@ -358,8 +358,6 @@ int sdmmc_read(struct device *dev, u32 blk_start, u32 blk_count, void *data)
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struct sdmmc_card *c = &cards[no];
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struct sdmmc_command cmd;
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gecko_printf("reading %d bytes to %p\n", blk_count*512,data);
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if (c->inserted == 0) {
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gecko_printf("sdmmc: READ: no card inserted.\n");
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return -1;
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@ -379,9 +377,6 @@ int sdmmc_read(struct device *dev, u32 blk_start, u32 blk_count, void *data)
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DPRINTF(2, ("sdmmc: MMC_READ_BLOCK_MULTIPLE\n"));
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memset(&cmd, 0, sizeof(cmd));
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if (blk_count == 1)
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cmd.c_opcode = MMC_READ_BLOCK_MULTIPLE;
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else
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cmd.c_opcode = MMC_READ_BLOCK_MULTIPLE;
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if (c->sdhc_blockmode)
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cmd.c_arg = blk_start;
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@ -393,8 +388,6 @@ int sdmmc_read(struct device *dev, u32 blk_start, u32 blk_count, void *data)
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cmd.c_flags = SCF_RSP_R1 | SCF_CMD_READ;
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sdmmc_host_exec_command(c, &cmd);
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gecko_printf("arg: %08x %08x\n", cmd.c_arg, blk_start);
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if (cmd.c_error) {
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gecko_printf("sdmmc: MMC_READ_BLOCK_MULTIPLE failed for "
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"card %d with %d", no, cmd.c_error);
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@ -430,9 +423,6 @@ int sdmmc_write(struct device *dev, u32 blk_start, u32 blk_count, void *data)
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DPRINTF(2, ("sdmmc: MMC_WRITE_BLOCK_MULTIPLE\n"));
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memset(&cmd, 0, sizeof(cmd));
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if (blk_count == 1)
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cmd.c_opcode = MMC_WRITE_BLOCK_SINGLE;
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else
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cmd.c_opcode = MMC_WRITE_BLOCK_MULTIPLE;
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if (c->sdhc_blockmode)
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cmd.c_arg = blk_start;
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@ -467,14 +457,14 @@ void sdmmc_ipc(volatile ipc_request *req)
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req->args[1], (void *)req->args[2]);
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dc_flushrange((void *)req->args[2],
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req->args[1]*SDMMC_DEFAULT_BLOCKLEN);
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ipc_post(req->code, req->tag, 1);
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ipc_post(req->code, req->tag, 1, ret);
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break;
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case IPC_SDMMC_WRITE:
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dc_invalidaterange((void *)req->args[2],
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req->args[1]*SDMMC_DEFAULT_BLOCKLEN);
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ret = sdmmc_write(SDMMC_DEFAULT_DEVICE, req->args[0],
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req->args[1], (void *)req->args[2]);
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ipc_post(req->code, req->tag, 1);
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ipc_post(req->code, req->tag, 1, ret);
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break;
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}
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}
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