merge sdmmc header files
This commit is contained in:
bushing
parent
e000264f3b
commit
f9e873115c
3
sdhc.c
3
sdhc.c
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@ -23,9 +23,6 @@
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#include "bsdtypes.h"
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#include "sdhcreg.h"
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#include "sdhcvar.h"
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#include "sdmmcchip.h"
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#include "sdmmcreg.h"
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#include "sdmmcvar.h"
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#include "sdmmc.h"
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#include "gecko.h"
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#include "string.h"
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3
sdmmc.c
3
sdmmc.c
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@ -11,9 +11,6 @@ Copyright (C) 2008, 2009 Sven Peter <svenpeter@gmail.com>
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#include "bsdtypes.h"
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#include "sdhcreg.h"
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#include "sdhcvar.h"
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#include "sdmmcchip.h"
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#include "sdmmcreg.h"
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#include "sdmmcvar.h"
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#include "sdmmc.h"
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#include "gecko.h"
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#include "string.h"
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437
sdmmc.h
437
sdmmc.h
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@ -12,8 +12,232 @@ Copyright (C) 2008, 2009 Sven Peter <svenpeter@gmail.com>
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#define __SDMMC_H__
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#include "bsdtypes.h"
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#include "sdmmcchip.h"
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#include "sdmmcvar.h"
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struct sdmmc_command;
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typedef struct sdmmc_chip_functions *sdmmc_chipset_tag_t;
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typedef void *sdmmc_chipset_handle_t;
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struct sdmmc_chip_functions {
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/* host controller reset */
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int (*host_reset)(sdmmc_chipset_handle_t);
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/* host capabilities */
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u_int32_t (*host_ocr)(sdmmc_chipset_handle_t);
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int (*host_maxblklen)(sdmmc_chipset_handle_t);
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/* card detection */
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int (*card_detect)(sdmmc_chipset_handle_t);
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/* bus power and clock frequency */
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int (*bus_power)(sdmmc_chipset_handle_t, u_int32_t);
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int (*bus_clock)(sdmmc_chipset_handle_t, int);
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/* command execution */
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void (*exec_command)(sdmmc_chipset_handle_t,
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struct sdmmc_command *);
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/* card interrupt */
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void (*card_intr_mask)(sdmmc_chipset_handle_t, int);
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void (*card_intr_ack)(sdmmc_chipset_handle_t);
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};
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/* host controller reset */
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#define sdmmc_chip_host_reset(tag, handle) \
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((tag)->host_reset((handle)))
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/* host capabilities */
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#define sdmmc_chip_host_ocr(tag, handle) \
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((tag)->host_ocr((handle)))
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#define sdmmc_chip_host_maxblklen(tag, handle) \
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((tag)->host_maxblklen((handle)))
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/* card detection */
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#define sdmmc_chip_card_detect(tag, handle) \
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((tag)->card_detect((handle)))
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/* bus power and clock frequency */
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#define sdmmc_chip_bus_power(tag, handle, ocr) \
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((tag)->bus_power((handle), (ocr)))
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#define sdmmc_chip_bus_clock(tag, handle, freq) \
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((tag)->bus_clock((handle), (freq)))
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/* command execution */
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#define sdmmc_chip_exec_command(tag, handle, cmdp) \
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((tag)->exec_command((handle), (cmdp)))
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/* card interrupt */
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#define sdmmc_chip_card_intr_mask(tag, handle, enable) \
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((tag)->card_intr_mask((handle), (enable)))
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#define sdmmc_chip_card_intr_ack(tag, handle) \
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((tag)->card_intr_ack((handle)))
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/* clock frequencies for sdmmc_chip_bus_clock() */
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#define SDMMC_SDCLK_OFF 0
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#define SDMMC_SDCLK_400KHZ 400
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#define SDMMC_SDCLK_25MHZ 25000
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struct sdmmcbus_attach_args {
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const char *saa_busname;
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sdmmc_chipset_tag_t sct;
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sdmmc_chipset_handle_t sch;
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int flags;
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long max_xfer;
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};
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void sdmmc_delay(u_int);
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struct sdmmc_csd {
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int csdver; /* CSD structure format */
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int mmcver; /* MMC version (for CID format) */
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int capacity; /* total number of sectors */
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int sector_size; /* sector size in bytes */
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int read_bl_len; /* block length for reads */
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/* ... */
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};
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struct sdmmc_cid {
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int mid; /* manufacturer identification number */
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int oid; /* OEM/product identification number */
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char pnm[8]; /* product name (MMC v1 has the longest) */
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int rev; /* product revision */
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int psn; /* product serial number */
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int mdt; /* manufacturing date */
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};
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typedef u_int32_t sdmmc_response[4];
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struct sdmmc_softc;
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struct sdmmc_task {
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void (*func)(void *arg);
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void *arg;
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int onqueue;
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struct sdmmc_softc *sc;
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};
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#define sdmmc_init_task(xtask, xfunc, xarg) do { \
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(xtask)->func = (xfunc); \
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(xtask)->arg = (xarg); \
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(xtask)->onqueue = 0; \
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(xtask)->sc = NULL; \
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} while (0)
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#define sdmmc_task_pending(xtask) ((xtask)->onqueue)
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struct sdmmc_command {
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// struct sdmmc_task c_task; /* task queue entry */
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u_int16_t c_opcode; /* SD or MMC command index */
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u_int32_t c_arg; /* SD/MMC command argument */
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sdmmc_response c_resp; /* response buffer */
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void *c_data; /* buffer to send or read into */
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int c_datalen; /* length of data buffer */
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int c_blklen; /* block length */
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int c_flags; /* see below */
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#define SCF_ITSDONE 0x0001 /* command is complete */
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#define SCF_CMD(flags) ((flags) & 0x00f0)
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#define SCF_CMD_AC 0x0000
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#define SCF_CMD_ADTC 0x0010
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#define SCF_CMD_BC 0x0020
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#define SCF_CMD_BCR 0x0030
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#define SCF_CMD_READ 0x0040 /* read command (data expected) */
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#define SCF_RSP_BSY 0x0100
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#define SCF_RSP_136 0x0200
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#define SCF_RSP_CRC 0x0400
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#define SCF_RSP_IDX 0x0800
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#define SCF_RSP_PRESENT 0x1000
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/* response types */
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#define SCF_RSP_R0 0 /* none */
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#define SCF_RSP_R1 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
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#define SCF_RSP_R1B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY)
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#define SCF_RSP_R2 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_136)
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#define SCF_RSP_R3 (SCF_RSP_PRESENT)
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#define SCF_RSP_R4 (SCF_RSP_PRESENT)
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#define SCF_RSP_R5 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
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#define SCF_RSP_R5B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY)
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#define SCF_RSP_R6 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
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#define SCF_RSP_R7 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
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int c_error; /* errno value on completion */
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int c_timeout;
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/* Host controller owned fields for data xfer in progress */
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int c_resid; /* remaining I/O */
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u_char *c_buf; /* remaining data */
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};
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/*
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* Decoded PC Card 16 based Card Information Structure (CIS),
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* per card (function 0) and per function (1 and greater).
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*/
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struct sdmmc_cis {
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u_int16_t manufacturer;
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#define SDMMC_VENDOR_INVALID 0xffff
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u_int16_t product;
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#define SDMMC_PRODUCT_INVALID 0xffff
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u_int8_t function;
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#define SDMMC_FUNCTION_INVALID 0xff
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u_char cis1_major;
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u_char cis1_minor;
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char cis1_info_buf[256];
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char *cis1_info[4];
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};
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/*
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* Structure describing either an SD card I/O function or a SD/MMC
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* memory card from a "stack of cards" that responded to CMD2. For a
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* combo card with one I/O function and one memory card, there will be
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* two of these structures allocated. Each card slot has such a list
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* of sdmmc_function structures.
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*/
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struct sdmmc_function {
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/* common members */
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struct sdmmc_softc *sc; /* card slot softc */
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u_int16_t rca; /* relative card address */
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int flags;
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#define SFF_ERROR 0x0001 /* function is poo; ignore it */
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#define SFF_SDHC 0x0002 /* SD High Capacity card */
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/* SD card I/O function members */
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int number; /* I/O function number or -1 */
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struct device *child; /* function driver */
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struct sdmmc_cis cis; /* decoded CIS */
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/* SD/MMC memory card members */
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struct sdmmc_csd csd; /* decoded CSD value */
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struct sdmmc_cid cid; /* decoded CID value */
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sdmmc_response raw_cid; /* temp. storage for decoding */
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};
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/*
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* Structure describing a single SD/MMC/SDIO card slot.
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*/
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struct sdmmc_softc {
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struct device sc_dev; /* base device */
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#define SDMMCDEVNAME(sc) ((sc)->sc_dev.dv_xname)
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sdmmc_chipset_tag_t sct; /* host controller chipset tag */
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sdmmc_chipset_handle_t sch; /* host controller chipset handle */
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int sc_flags;
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#define SMF_SD_MODE 0x0001 /* host in SD mode (MMC otherwise) */
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#define SMF_IO_MODE 0x0002 /* host in I/O mode (SD mode only) */
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#define SMF_MEM_MODE 0x0004 /* host in memory mode (SD or MMC) */
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#define SMF_CARD_PRESENT 0x0010 /* card presence noticed */
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#define SMF_CARD_ATTACHED 0x0020 /* card driver(s) attached */
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#define SMF_STOP_AFTER_MULTIPLE 0x0040 /* send a stop after a multiple cmd */
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int sc_function_count; /* number of I/O functions (SDIO) */
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struct sdmmc_function *sc_card; /* selected card */
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struct sdmmc_function *sc_fn0; /* function 0, the card itself */
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int sc_dying; /* bus driver is shutting down */
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struct proc *sc_task_thread; /* asynchronous tasks */
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struct sdmmc_task sc_discover_task; /* card attach/detach task */
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struct sdmmc_task sc_intr_task; /* card interrupt task */
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void *sc_scsibus; /* SCSI bus emulation softc */
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long sc_max_xfer; /* maximum transfer size */
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};
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/*
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* Attach devices at the sdmmc bus.
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*/
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struct sdmmc_attach_args {
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struct scsi_link *scsi_link; /* XXX */
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struct sdmmc_function *sf;
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};
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#define IPL_SDMMC IPL_BIO
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#define SDMMC_LOCK(sc) lockmgr(&(sc)->sc_lock, LK_EXCLUSIVE, NULL)
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#define SDMMC_UNLOCK(sc) lockmgr(&(sc)->sc_lock, LK_RELEASE, NULL)
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#define SDMMC_ASSERT_LOCKED(sc) \
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KASSERT(lockstatus(&((sc))->sc_lock) == LK_EXCLUSIVE)
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#ifdef CAN_HAZ_IPC
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#include "ipc.h"
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#endif
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@ -39,4 +263,213 @@ int sdmmc_read(struct device *dev, u32 blk_start, u32 blk_count, void *data);
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void sdmmc_ipc(volatile ipc_request *req);
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#endif
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/* MMC commands */ /* response type */
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#define MMC_GO_IDLE_STATE 0 /* R0 */
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#define MMC_SEND_OP_COND 1 /* R3 */
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#define MMC_ALL_SEND_CID 2 /* R2 */
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#define MMC_SET_RELATIVE_ADDR 3 /* R1 */
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#define MMC_SELECT_CARD 7 /* R1 */
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#define MMC_SEND_CSD 9 /* R2 */
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#define MMC_STOP_TRANSMISSION 12 /* R1B */
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#define MMC_SEND_STATUS 13 /* R1 */
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#define MMC_SET_BLOCKLEN 16 /* R1 */
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#define MMC_READ_BLOCK_SINGLE 17 /* R1 */
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#define MMC_READ_BLOCK_MULTIPLE 18 /* R1 */
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#define MMC_SET_BLOCK_COUNT 23 /* R1 */
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#define MMC_WRITE_BLOCK_SINGLE 24 /* R1 */
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#define MMC_WRITE_BLOCK_MULTIPLE 25 /* R1 */
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#define MMC_APP_CMD 55 /* R1 */
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/* SD commands */ /* response type */
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#define SD_SEND_RELATIVE_ADDR 3 /* R6 */
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#define SD_SEND_IF_COND 8 /* R7 */
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/* SD application commands */ /* response type */
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#define SD_APP_SET_BUS_WIDTH 6 /* R1 */
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#define SD_APP_OP_COND 41 /* R3 */
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/* OCR bits */
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#define MMC_OCR_MEM_READY (1<<31) /* memory power-up status bit */
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#define MMC_OCR_3_5V_3_6V (1<<23)
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#define MMC_OCR_3_4V_3_5V (1<<22)
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#define MMC_OCR_3_3V_3_4V (1<<21)
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#define MMC_OCR_3_2V_3_3V (1<<20)
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#define MMC_OCR_3_1V_3_2V (1<<19)
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#define MMC_OCR_3_0V_3_1V (1<<18)
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#define MMC_OCR_2_9V_3_0V (1<<17)
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#define MMC_OCR_2_8V_2_9V (1<<16)
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#define MMC_OCR_2_7V_2_8V (1<<15)
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#define MMC_OCR_2_6V_2_7V (1<<14)
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#define MMC_OCR_2_5V_2_6V (1<<13)
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#define MMC_OCR_2_4V_2_5V (1<<12)
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#define MMC_OCR_2_3V_2_4V (1<<11)
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#define MMC_OCR_2_2V_2_3V (1<<10)
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#define MMC_OCR_2_1V_2_2V (1<<9)
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#define MMC_OCR_2_0V_2_1V (1<<8)
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#define MMC_OCR_1_9V_2_0V (1<<7)
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#define MMC_OCR_1_8V_1_9V (1<<6)
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#define MMC_OCR_1_7V_1_8V (1<<5)
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#define MMC_OCR_1_6V_1_7V (1<<4)
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#define SD_OCR_SDHC_CAP (1<<30)
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#define SD_OCR_VOL_MASK 0xFF8000 /* bits 23:15 */
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/* R1 response type bits */
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#define MMC_R1_READY_FOR_DATA (1<<8) /* ready for next transfer */
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#define MMC_R1_APP_CMD (1<<5) /* app. commands supported */
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/* 48-bit response decoding (32 bits w/o CRC) */
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#define MMC_R1(resp) ((resp)[0])
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#define MMC_R3(resp) ((resp)[0])
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#define SD_R6(resp) ((resp)[0])
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/* RCA argument and response */
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#define MMC_ARG_RCA(rca) ((rca) << 16)
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#define SD_R6_RCA(resp) (SD_R6((resp)) >> 16)
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/* bus width argument */
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#define SD_ARG_BUS_WIDTH_1 0
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#define SD_ARG_BUS_WIDTH_4 2
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/* MMC R2 response (CSD) */
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#define MMC_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
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#define MMC_CSD_CSDVER_1_0 1
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#define MMC_CSD_CSDVER_2_0 2
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#define MMC_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4)
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#define MMC_CSD_MMCVER_1_0 0 /* MMC 1.0 - 1.2 */
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#define MMC_CSD_MMCVER_1_4 1 /* MMC 1.4 */
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#define MMC_CSD_MMCVER_2_0 2 /* MMC 2.0 - 2.2 */
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#define MMC_CSD_MMCVER_3_1 3 /* MMC 3.1 - 3.3 */
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#define MMC_CSD_MMCVER_4_0 4 /* MMC 4 */
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#define MMC_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
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#define MMC_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
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#define MMC_CSD_CAPACITY(resp) ((MMC_CSD_C_SIZE((resp))+1) << \
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(MMC_CSD_C_SIZE_MULT((resp))+2))
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#define MMC_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
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/* MMC v1 R2 response (CID) */
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#define MMC_CID_MID_V1(resp) MMC_RSP_BITS((resp), 104, 24)
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#define MMC_CID_PNM_V1_CPY(resp, pnm) \
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do { \
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(pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
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(pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
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(pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
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(pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
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(pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
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(pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
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(pnm)[6] = MMC_RSP_BITS((resp), 48, 8); \
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(pnm)[7] = '\0'; \
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} while (0)
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#define MMC_CID_REV_V1(resp) MMC_RSP_BITS((resp), 40, 8)
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#define MMC_CID_PSN_V1(resp) MMC_RSP_BITS((resp), 16, 24)
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#define MMC_CID_MDT_V1(resp) MMC_RSP_BITS((resp), 8, 8)
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/* MMC v2 R2 response (CID) */
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#define MMC_CID_MID_V2(resp) MMC_RSP_BITS((resp), 120, 8)
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#define MMC_CID_OID_V2(resp) MMC_RSP_BITS((resp), 104, 16)
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#define MMC_CID_PNM_V2_CPY(resp, pnm) \
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do { \
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(pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
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(pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
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(pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
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(pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
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(pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
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(pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
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(pnm)[6] = '\0'; \
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} while (0)
|
||||
#define MMC_CID_PSN_V2(resp) MMC_RSP_BITS((resp), 16, 32)
|
||||
|
||||
/* SD R2 response (CSD) */
|
||||
#define SD_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
|
||||
#define SD_CSD_CSDVER_1_0 0
|
||||
#define SD_CSD_CSDVER_2_0 1
|
||||
#define SD_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8)
|
||||
#define SD_CSD_TAAC_1_5_MSEC 0x26
|
||||
#define SD_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8)
|
||||
#define SD_CSD_SPEED(resp) MMC_RSP_BITS((resp), 96, 8)
|
||||
#define SD_CSD_SPEED_25_MHZ 0x32
|
||||
#define SD_CSD_SPEED_50_MHZ 0x5a
|
||||
#define SD_CSD_CCC(resp) MMC_RSP_BITS((resp), 84, 12)
|
||||
#define SD_CSD_CCC_ALL 0x5f5
|
||||
#define SD_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
|
||||
#define SD_CSD_READ_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 79, 1)
|
||||
#define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1)
|
||||
#define SD_CSD_READ_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 77, 1)
|
||||
#define SD_CSD_DSR_IMP(resp) MMC_RSP_BITS((resp), 76, 1)
|
||||
#define SD_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
|
||||
#define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \
|
||||
(SD_CSD_C_SIZE_MULT((resp))+2))
|
||||
#define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22)
|
||||
#define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10)
|
||||
#define SD_CSD_V2_BL_LEN 0x9 /* 512 */
|
||||
#define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3)
|
||||
#define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3)
|
||||
#define SD_CSD_VDD_W_CURR_MIN(resp) MMC_RSP_BITS((resp), 53, 3)
|
||||
#define SD_CSD_VDD_W_CURR_MAX(resp) MMC_RSP_BITS((resp), 50, 3)
|
||||
#define SD_CSD_VDD_RW_CURR_100mA 0x7
|
||||
#define SD_CSD_VDD_RW_CURR_80mA 0x6
|
||||
#define SD_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
|
||||
#define SD_CSD_ERASE_BLK_EN(resp) MMC_RSP_BITS((resp), 46, 1)
|
||||
#define SD_CSD_SECTOR_SIZE(resp) MMC_RSP_BITS((resp), 39, 7) /* +1 */
|
||||
#define SD_CSD_WP_GRP_SIZE(resp) MMC_RSP_BITS((resp), 32, 7) /* +1 */
|
||||
#define SD_CSD_WP_GRP_ENABLE(resp) MMC_RSP_BITS((resp), 31, 1)
|
||||
#define SD_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3)
|
||||
#define SD_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4)
|
||||
#define SD_CSD_RW_BL_LEN_2G 0xa
|
||||
#define SD_CSD_RW_BL_LEN_1G 0x9
|
||||
#define SD_CSD_WRITE_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 21, 1)
|
||||
#define SD_CSD_FILE_FORMAT_GRP(resp) MMC_RSP_BITS((resp), 15, 1)
|
||||
#define SD_CSD_COPY(resp) MMC_RSP_BITS((resp), 14, 1)
|
||||
#define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1)
|
||||
#define SD_CSD_TMP_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 12, 1)
|
||||
#define SD_CSD_FILE_FORMAT(resp) MMC_RSP_BITS((resp), 10, 2)
|
||||
|
||||
/* SD R2 response (CID) */
|
||||
#define SD_CID_MID(resp) MMC_RSP_BITS((resp), 120, 8)
|
||||
#define SD_CID_OID(resp) MMC_RSP_BITS((resp), 104, 16)
|
||||
#define SD_CID_PNM_CPY(resp, pnm) \
|
||||
do { \
|
||||
(pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
|
||||
(pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
|
||||
(pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
|
||||
(pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
|
||||
(pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
|
||||
(pnm)[5] = '\0'; \
|
||||
} while (0)
|
||||
#define SD_CID_REV(resp) MMC_RSP_BITS((resp), 56, 8)
|
||||
#define SD_CID_PSN(resp) MMC_RSP_BITS((resp), 24, 32)
|
||||
#define SD_CID_MDT(resp) MMC_RSP_BITS((resp), 8, 12)
|
||||
|
||||
/* Might be slow, but it should work on big and little endian systems. */
|
||||
#define MMC_RSP_BITS(resp, start, len) __bitfield((resp), (start)-8, (len))
|
||||
static __inline int
|
||||
__bitfield(u_int32_t *src, int start, int len)
|
||||
{
|
||||
u_int8_t *sp;
|
||||
u_int32_t dst, mask;
|
||||
int shift, bs, bc;
|
||||
|
||||
if (start < 0 || len < 0 || len > 32)
|
||||
return 0;
|
||||
|
||||
dst = 0;
|
||||
mask = len % 32 ? UINT_MAX >> (32 - (len % 32)) : UINT_MAX;
|
||||
shift = 0;
|
||||
|
||||
while (len > 0) {
|
||||
sp = (u_int8_t *)src + start / 8;
|
||||
bs = start % 8;
|
||||
bc = 8 - bs;
|
||||
if (bc > len)
|
||||
bc = len;
|
||||
dst |= (*sp++ >> bs) << shift;
|
||||
shift += bc;
|
||||
start += bc;
|
||||
len -= bc;
|
||||
}
|
||||
|
||||
dst &= mask;
|
||||
return (int)dst;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
90
sdmmcchip.h
90
sdmmcchip.h
|
|
@ -1,90 +0,0 @@
|
|||
/* $OpenBSD: sdmmcchip.h,v 1.4 2009/02/20 19:16:35 miod Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _SDMMC_CHIP_H_
|
||||
#define _SDMMC_CHIP_H_
|
||||
|
||||
struct sdmmc_command;
|
||||
|
||||
typedef struct sdmmc_chip_functions *sdmmc_chipset_tag_t;
|
||||
typedef void *sdmmc_chipset_handle_t;
|
||||
|
||||
struct sdmmc_chip_functions {
|
||||
/* host controller reset */
|
||||
int (*host_reset)(sdmmc_chipset_handle_t);
|
||||
/* host capabilities */
|
||||
u_int32_t (*host_ocr)(sdmmc_chipset_handle_t);
|
||||
int (*host_maxblklen)(sdmmc_chipset_handle_t);
|
||||
/* card detection */
|
||||
int (*card_detect)(sdmmc_chipset_handle_t);
|
||||
/* bus power and clock frequency */
|
||||
int (*bus_power)(sdmmc_chipset_handle_t, u_int32_t);
|
||||
int (*bus_clock)(sdmmc_chipset_handle_t, int);
|
||||
/* command execution */
|
||||
void (*exec_command)(sdmmc_chipset_handle_t,
|
||||
struct sdmmc_command *);
|
||||
/* card interrupt */
|
||||
void (*card_intr_mask)(sdmmc_chipset_handle_t, int);
|
||||
void (*card_intr_ack)(sdmmc_chipset_handle_t);
|
||||
};
|
||||
|
||||
/* host controller reset */
|
||||
#define sdmmc_chip_host_reset(tag, handle) \
|
||||
((tag)->host_reset((handle)))
|
||||
/* host capabilities */
|
||||
#define sdmmc_chip_host_ocr(tag, handle) \
|
||||
((tag)->host_ocr((handle)))
|
||||
#define sdmmc_chip_host_maxblklen(tag, handle) \
|
||||
((tag)->host_maxblklen((handle)))
|
||||
/* card detection */
|
||||
#define sdmmc_chip_card_detect(tag, handle) \
|
||||
((tag)->card_detect((handle)))
|
||||
/* bus power and clock frequency */
|
||||
#define sdmmc_chip_bus_power(tag, handle, ocr) \
|
||||
((tag)->bus_power((handle), (ocr)))
|
||||
#define sdmmc_chip_bus_clock(tag, handle, freq) \
|
||||
((tag)->bus_clock((handle), (freq)))
|
||||
/* command execution */
|
||||
#define sdmmc_chip_exec_command(tag, handle, cmdp) \
|
||||
((tag)->exec_command((handle), (cmdp)))
|
||||
/* card interrupt */
|
||||
#define sdmmc_chip_card_intr_mask(tag, handle, enable) \
|
||||
((tag)->card_intr_mask((handle), (enable)))
|
||||
#define sdmmc_chip_card_intr_ack(tag, handle) \
|
||||
((tag)->card_intr_ack((handle)))
|
||||
|
||||
/* clock frequencies for sdmmc_chip_bus_clock() */
|
||||
#define SDMMC_SDCLK_OFF 0
|
||||
#define SDMMC_SDCLK_400KHZ 400
|
||||
#define SDMMC_SDCLK_25MHZ 25000
|
||||
|
||||
struct sdmmcbus_attach_args {
|
||||
const char *saa_busname;
|
||||
sdmmc_chipset_tag_t sct;
|
||||
sdmmc_chipset_handle_t sch;
|
||||
int flags;
|
||||
long max_xfer;
|
||||
};
|
||||
|
||||
#if 0
|
||||
void sdmmc_needs_discover(struct device *);
|
||||
void sdmmc_card_intr(struct device *);
|
||||
#endif
|
||||
void sdmmc_delay(u_int);
|
||||
|
||||
#endif
|
||||
231
sdmmcreg.h
231
sdmmcreg.h
|
|
@ -1,231 +0,0 @@
|
|||
/* $OpenBSD: sdmmcreg.h,v 1.4 2009/01/09 10:55:22 jsg Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _SDMMCREG_H_
|
||||
#define _SDMMCREG_H_
|
||||
|
||||
/* MMC commands */ /* response type */
|
||||
#define MMC_GO_IDLE_STATE 0 /* R0 */
|
||||
#define MMC_SEND_OP_COND 1 /* R3 */
|
||||
#define MMC_ALL_SEND_CID 2 /* R2 */
|
||||
#define MMC_SET_RELATIVE_ADDR 3 /* R1 */
|
||||
#define MMC_SELECT_CARD 7 /* R1 */
|
||||
#define MMC_SEND_CSD 9 /* R2 */
|
||||
#define MMC_STOP_TRANSMISSION 12 /* R1B */
|
||||
#define MMC_SEND_STATUS 13 /* R1 */
|
||||
#define MMC_SET_BLOCKLEN 16 /* R1 */
|
||||
#define MMC_READ_BLOCK_SINGLE 17 /* R1 */
|
||||
#define MMC_READ_BLOCK_MULTIPLE 18 /* R1 */
|
||||
#define MMC_SET_BLOCK_COUNT 23 /* R1 */
|
||||
#define MMC_WRITE_BLOCK_SINGLE 24 /* R1 */
|
||||
#define MMC_WRITE_BLOCK_MULTIPLE 25 /* R1 */
|
||||
#define MMC_APP_CMD 55 /* R1 */
|
||||
|
||||
/* SD commands */ /* response type */
|
||||
#define SD_SEND_RELATIVE_ADDR 3 /* R6 */
|
||||
#define SD_SEND_IF_COND 8 /* R7 */
|
||||
|
||||
/* SD application commands */ /* response type */
|
||||
#define SD_APP_SET_BUS_WIDTH 6 /* R1 */
|
||||
#define SD_APP_OP_COND 41 /* R3 */
|
||||
|
||||
/* OCR bits */
|
||||
#define MMC_OCR_MEM_READY (1<<31) /* memory power-up status bit */
|
||||
#define MMC_OCR_3_5V_3_6V (1<<23)
|
||||
#define MMC_OCR_3_4V_3_5V (1<<22)
|
||||
#define MMC_OCR_3_3V_3_4V (1<<21)
|
||||
#define MMC_OCR_3_2V_3_3V (1<<20)
|
||||
#define MMC_OCR_3_1V_3_2V (1<<19)
|
||||
#define MMC_OCR_3_0V_3_1V (1<<18)
|
||||
#define MMC_OCR_2_9V_3_0V (1<<17)
|
||||
#define MMC_OCR_2_8V_2_9V (1<<16)
|
||||
#define MMC_OCR_2_7V_2_8V (1<<15)
|
||||
#define MMC_OCR_2_6V_2_7V (1<<14)
|
||||
#define MMC_OCR_2_5V_2_6V (1<<13)
|
||||
#define MMC_OCR_2_4V_2_5V (1<<12)
|
||||
#define MMC_OCR_2_3V_2_4V (1<<11)
|
||||
#define MMC_OCR_2_2V_2_3V (1<<10)
|
||||
#define MMC_OCR_2_1V_2_2V (1<<9)
|
||||
#define MMC_OCR_2_0V_2_1V (1<<8)
|
||||
#define MMC_OCR_1_9V_2_0V (1<<7)
|
||||
#define MMC_OCR_1_8V_1_9V (1<<6)
|
||||
#define MMC_OCR_1_7V_1_8V (1<<5)
|
||||
#define MMC_OCR_1_6V_1_7V (1<<4)
|
||||
|
||||
#define SD_OCR_SDHC_CAP (1<<30)
|
||||
#define SD_OCR_VOL_MASK 0xFF8000 /* bits 23:15 */
|
||||
|
||||
/* R1 response type bits */
|
||||
#define MMC_R1_READY_FOR_DATA (1<<8) /* ready for next transfer */
|
||||
#define MMC_R1_APP_CMD (1<<5) /* app. commands supported */
|
||||
|
||||
/* 48-bit response decoding (32 bits w/o CRC) */
|
||||
#define MMC_R1(resp) ((resp)[0])
|
||||
#define MMC_R3(resp) ((resp)[0])
|
||||
#define SD_R6(resp) ((resp)[0])
|
||||
|
||||
/* RCA argument and response */
|
||||
#define MMC_ARG_RCA(rca) ((rca) << 16)
|
||||
#define SD_R6_RCA(resp) (SD_R6((resp)) >> 16)
|
||||
|
||||
/* bus width argument */
|
||||
#define SD_ARG_BUS_WIDTH_1 0
|
||||
#define SD_ARG_BUS_WIDTH_4 2
|
||||
|
||||
/* MMC R2 response (CSD) */
|
||||
#define MMC_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
|
||||
#define MMC_CSD_CSDVER_1_0 1
|
||||
#define MMC_CSD_CSDVER_2_0 2
|
||||
#define MMC_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4)
|
||||
#define MMC_CSD_MMCVER_1_0 0 /* MMC 1.0 - 1.2 */
|
||||
#define MMC_CSD_MMCVER_1_4 1 /* MMC 1.4 */
|
||||
#define MMC_CSD_MMCVER_2_0 2 /* MMC 2.0 - 2.2 */
|
||||
#define MMC_CSD_MMCVER_3_1 3 /* MMC 3.1 - 3.3 */
|
||||
#define MMC_CSD_MMCVER_4_0 4 /* MMC 4 */
|
||||
#define MMC_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
|
||||
#define MMC_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
|
||||
#define MMC_CSD_CAPACITY(resp) ((MMC_CSD_C_SIZE((resp))+1) << \
|
||||
(MMC_CSD_C_SIZE_MULT((resp))+2))
|
||||
#define MMC_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
|
||||
|
||||
/* MMC v1 R2 response (CID) */
|
||||
#define MMC_CID_MID_V1(resp) MMC_RSP_BITS((resp), 104, 24)
|
||||
#define MMC_CID_PNM_V1_CPY(resp, pnm) \
|
||||
do { \
|
||||
(pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
|
||||
(pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
|
||||
(pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
|
||||
(pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
|
||||
(pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
|
||||
(pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
|
||||
(pnm)[6] = MMC_RSP_BITS((resp), 48, 8); \
|
||||
(pnm)[7] = '\0'; \
|
||||
} while (0)
|
||||
#define MMC_CID_REV_V1(resp) MMC_RSP_BITS((resp), 40, 8)
|
||||
#define MMC_CID_PSN_V1(resp) MMC_RSP_BITS((resp), 16, 24)
|
||||
#define MMC_CID_MDT_V1(resp) MMC_RSP_BITS((resp), 8, 8)
|
||||
|
||||
/* MMC v2 R2 response (CID) */
|
||||
#define MMC_CID_MID_V2(resp) MMC_RSP_BITS((resp), 120, 8)
|
||||
#define MMC_CID_OID_V2(resp) MMC_RSP_BITS((resp), 104, 16)
|
||||
#define MMC_CID_PNM_V2_CPY(resp, pnm) \
|
||||
do { \
|
||||
(pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
|
||||
(pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
|
||||
(pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
|
||||
(pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
|
||||
(pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
|
||||
(pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
|
||||
(pnm)[6] = '\0'; \
|
||||
} while (0)
|
||||
#define MMC_CID_PSN_V2(resp) MMC_RSP_BITS((resp), 16, 32)
|
||||
|
||||
/* SD R2 response (CSD) */
|
||||
#define SD_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
|
||||
#define SD_CSD_CSDVER_1_0 0
|
||||
#define SD_CSD_CSDVER_2_0 1
|
||||
#define SD_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8)
|
||||
#define SD_CSD_TAAC_1_5_MSEC 0x26
|
||||
#define SD_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8)
|
||||
#define SD_CSD_SPEED(resp) MMC_RSP_BITS((resp), 96, 8)
|
||||
#define SD_CSD_SPEED_25_MHZ 0x32
|
||||
#define SD_CSD_SPEED_50_MHZ 0x5a
|
||||
#define SD_CSD_CCC(resp) MMC_RSP_BITS((resp), 84, 12)
|
||||
#define SD_CSD_CCC_ALL 0x5f5
|
||||
#define SD_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
|
||||
#define SD_CSD_READ_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 79, 1)
|
||||
#define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1)
|
||||
#define SD_CSD_READ_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 77, 1)
|
||||
#define SD_CSD_DSR_IMP(resp) MMC_RSP_BITS((resp), 76, 1)
|
||||
#define SD_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
|
||||
#define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \
|
||||
(SD_CSD_C_SIZE_MULT((resp))+2))
|
||||
#define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22)
|
||||
#define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10)
|
||||
#define SD_CSD_V2_BL_LEN 0x9 /* 512 */
|
||||
#define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3)
|
||||
#define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3)
|
||||
#define SD_CSD_VDD_W_CURR_MIN(resp) MMC_RSP_BITS((resp), 53, 3)
|
||||
#define SD_CSD_VDD_W_CURR_MAX(resp) MMC_RSP_BITS((resp), 50, 3)
|
||||
#define SD_CSD_VDD_RW_CURR_100mA 0x7
|
||||
#define SD_CSD_VDD_RW_CURR_80mA 0x6
|
||||
#define SD_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
|
||||
#define SD_CSD_ERASE_BLK_EN(resp) MMC_RSP_BITS((resp), 46, 1)
|
||||
#define SD_CSD_SECTOR_SIZE(resp) MMC_RSP_BITS((resp), 39, 7) /* +1 */
|
||||
#define SD_CSD_WP_GRP_SIZE(resp) MMC_RSP_BITS((resp), 32, 7) /* +1 */
|
||||
#define SD_CSD_WP_GRP_ENABLE(resp) MMC_RSP_BITS((resp), 31, 1)
|
||||
#define SD_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3)
|
||||
#define SD_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4)
|
||||
#define SD_CSD_RW_BL_LEN_2G 0xa
|
||||
#define SD_CSD_RW_BL_LEN_1G 0x9
|
||||
#define SD_CSD_WRITE_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 21, 1)
|
||||
#define SD_CSD_FILE_FORMAT_GRP(resp) MMC_RSP_BITS((resp), 15, 1)
|
||||
#define SD_CSD_COPY(resp) MMC_RSP_BITS((resp), 14, 1)
|
||||
#define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1)
|
||||
#define SD_CSD_TMP_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 12, 1)
|
||||
#define SD_CSD_FILE_FORMAT(resp) MMC_RSP_BITS((resp), 10, 2)
|
||||
|
||||
/* SD R2 response (CID) */
|
||||
#define SD_CID_MID(resp) MMC_RSP_BITS((resp), 120, 8)
|
||||
#define SD_CID_OID(resp) MMC_RSP_BITS((resp), 104, 16)
|
||||
#define SD_CID_PNM_CPY(resp, pnm) \
|
||||
do { \
|
||||
(pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
|
||||
(pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
|
||||
(pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
|
||||
(pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
|
||||
(pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
|
||||
(pnm)[5] = '\0'; \
|
||||
} while (0)
|
||||
#define SD_CID_REV(resp) MMC_RSP_BITS((resp), 56, 8)
|
||||
#define SD_CID_PSN(resp) MMC_RSP_BITS((resp), 24, 32)
|
||||
#define SD_CID_MDT(resp) MMC_RSP_BITS((resp), 8, 12)
|
||||
|
||||
/* Might be slow, but it should work on big and little endian systems. */
|
||||
#define MMC_RSP_BITS(resp, start, len) __bitfield((resp), (start)-8, (len))
|
||||
static __inline int
|
||||
__bitfield(u_int32_t *src, int start, int len)
|
||||
{
|
||||
u_int8_t *sp;
|
||||
u_int32_t dst, mask;
|
||||
int shift, bs, bc;
|
||||
|
||||
if (start < 0 || len < 0 || len > 32)
|
||||
return 0;
|
||||
|
||||
dst = 0;
|
||||
mask = len % 32 ? UINT_MAX >> (32 - (len % 32)) : UINT_MAX;
|
||||
shift = 0;
|
||||
|
||||
while (len > 0) {
|
||||
sp = (u_int8_t *)src + start / 8;
|
||||
bs = start % 8;
|
||||
bc = 8 - bs;
|
||||
if (bc > len)
|
||||
bc = len;
|
||||
dst |= (*sp++ >> bs) << shift;
|
||||
shift += bc;
|
||||
start += bc;
|
||||
len -= bc;
|
||||
}
|
||||
|
||||
dst &= mask;
|
||||
return (int)dst;
|
||||
}
|
||||
|
||||
#endif
|
||||
184
sdmmcvar.h
184
sdmmcvar.h
|
|
@ -1,184 +0,0 @@
|
|||
/* $OpenBSD: sdmmcvar.h,v 1.16 2009/04/07 16:35:52 blambert Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
|
||||
* Copyright (c) 2009 Sven Peter <svenpeter@gmail.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _SDMMCVAR_H_
|
||||
#define _SDMMCVAR_H_
|
||||
|
||||
struct sdmmc_csd {
|
||||
int csdver; /* CSD structure format */
|
||||
int mmcver; /* MMC version (for CID format) */
|
||||
int capacity; /* total number of sectors */
|
||||
int sector_size; /* sector size in bytes */
|
||||
int read_bl_len; /* block length for reads */
|
||||
/* ... */
|
||||
};
|
||||
|
||||
struct sdmmc_cid {
|
||||
int mid; /* manufacturer identification number */
|
||||
int oid; /* OEM/product identification number */
|
||||
char pnm[8]; /* product name (MMC v1 has the longest) */
|
||||
int rev; /* product revision */
|
||||
int psn; /* product serial number */
|
||||
int mdt; /* manufacturing date */
|
||||
};
|
||||
|
||||
typedef u_int32_t sdmmc_response[4];
|
||||
|
||||
struct sdmmc_softc;
|
||||
|
||||
struct sdmmc_task {
|
||||
void (*func)(void *arg);
|
||||
void *arg;
|
||||
int onqueue;
|
||||
struct sdmmc_softc *sc;
|
||||
};
|
||||
|
||||
#define sdmmc_init_task(xtask, xfunc, xarg) do { \
|
||||
(xtask)->func = (xfunc); \
|
||||
(xtask)->arg = (xarg); \
|
||||
(xtask)->onqueue = 0; \
|
||||
(xtask)->sc = NULL; \
|
||||
} while (0)
|
||||
|
||||
#define sdmmc_task_pending(xtask) ((xtask)->onqueue)
|
||||
|
||||
struct sdmmc_command {
|
||||
// struct sdmmc_task c_task; /* task queue entry */
|
||||
u_int16_t c_opcode; /* SD or MMC command index */
|
||||
u_int32_t c_arg; /* SD/MMC command argument */
|
||||
sdmmc_response c_resp; /* response buffer */
|
||||
void *c_data; /* buffer to send or read into */
|
||||
int c_datalen; /* length of data buffer */
|
||||
int c_blklen; /* block length */
|
||||
int c_flags; /* see below */
|
||||
#define SCF_ITSDONE 0x0001 /* command is complete */
|
||||
#define SCF_CMD(flags) ((flags) & 0x00f0)
|
||||
#define SCF_CMD_AC 0x0000
|
||||
#define SCF_CMD_ADTC 0x0010
|
||||
#define SCF_CMD_BC 0x0020
|
||||
#define SCF_CMD_BCR 0x0030
|
||||
#define SCF_CMD_READ 0x0040 /* read command (data expected) */
|
||||
#define SCF_RSP_BSY 0x0100
|
||||
#define SCF_RSP_136 0x0200
|
||||
#define SCF_RSP_CRC 0x0400
|
||||
#define SCF_RSP_IDX 0x0800
|
||||
#define SCF_RSP_PRESENT 0x1000
|
||||
/* response types */
|
||||
#define SCF_RSP_R0 0 /* none */
|
||||
#define SCF_RSP_R1 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
|
||||
#define SCF_RSP_R1B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY)
|
||||
#define SCF_RSP_R2 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_136)
|
||||
#define SCF_RSP_R3 (SCF_RSP_PRESENT)
|
||||
#define SCF_RSP_R4 (SCF_RSP_PRESENT)
|
||||
#define SCF_RSP_R5 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
|
||||
#define SCF_RSP_R5B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY)
|
||||
#define SCF_RSP_R6 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
|
||||
#define SCF_RSP_R7 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
|
||||
int c_error; /* errno value on completion */
|
||||
|
||||
int c_timeout;
|
||||
|
||||
/* Host controller owned fields for data xfer in progress */
|
||||
int c_resid; /* remaining I/O */
|
||||
u_char *c_buf; /* remaining data */
|
||||
};
|
||||
|
||||
/*
|
||||
* Decoded PC Card 16 based Card Information Structure (CIS),
|
||||
* per card (function 0) and per function (1 and greater).
|
||||
*/
|
||||
struct sdmmc_cis {
|
||||
u_int16_t manufacturer;
|
||||
#define SDMMC_VENDOR_INVALID 0xffff
|
||||
u_int16_t product;
|
||||
#define SDMMC_PRODUCT_INVALID 0xffff
|
||||
u_int8_t function;
|
||||
#define SDMMC_FUNCTION_INVALID 0xff
|
||||
u_char cis1_major;
|
||||
u_char cis1_minor;
|
||||
char cis1_info_buf[256];
|
||||
char *cis1_info[4];
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure describing either an SD card I/O function or a SD/MMC
|
||||
* memory card from a "stack of cards" that responded to CMD2. For a
|
||||
* combo card with one I/O function and one memory card, there will be
|
||||
* two of these structures allocated. Each card slot has such a list
|
||||
* of sdmmc_function structures.
|
||||
*/
|
||||
struct sdmmc_function {
|
||||
/* common members */
|
||||
struct sdmmc_softc *sc; /* card slot softc */
|
||||
u_int16_t rca; /* relative card address */
|
||||
int flags;
|
||||
#define SFF_ERROR 0x0001 /* function is poo; ignore it */
|
||||
#define SFF_SDHC 0x0002 /* SD High Capacity card */
|
||||
/* SD card I/O function members */
|
||||
int number; /* I/O function number or -1 */
|
||||
struct device *child; /* function driver */
|
||||
struct sdmmc_cis cis; /* decoded CIS */
|
||||
/* SD/MMC memory card members */
|
||||
struct sdmmc_csd csd; /* decoded CSD value */
|
||||
struct sdmmc_cid cid; /* decoded CID value */
|
||||
sdmmc_response raw_cid; /* temp. storage for decoding */
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure describing a single SD/MMC/SDIO card slot.
|
||||
*/
|
||||
struct sdmmc_softc {
|
||||
struct device sc_dev; /* base device */
|
||||
#define SDMMCDEVNAME(sc) ((sc)->sc_dev.dv_xname)
|
||||
sdmmc_chipset_tag_t sct; /* host controller chipset tag */
|
||||
sdmmc_chipset_handle_t sch; /* host controller chipset handle */
|
||||
int sc_flags;
|
||||
#define SMF_SD_MODE 0x0001 /* host in SD mode (MMC otherwise) */
|
||||
#define SMF_IO_MODE 0x0002 /* host in I/O mode (SD mode only) */
|
||||
#define SMF_MEM_MODE 0x0004 /* host in memory mode (SD or MMC) */
|
||||
#define SMF_CARD_PRESENT 0x0010 /* card presence noticed */
|
||||
#define SMF_CARD_ATTACHED 0x0020 /* card driver(s) attached */
|
||||
#define SMF_STOP_AFTER_MULTIPLE 0x0040 /* send a stop after a multiple cmd */
|
||||
int sc_function_count; /* number of I/O functions (SDIO) */
|
||||
struct sdmmc_function *sc_card; /* selected card */
|
||||
struct sdmmc_function *sc_fn0; /* function 0, the card itself */
|
||||
int sc_dying; /* bus driver is shutting down */
|
||||
struct proc *sc_task_thread; /* asynchronous tasks */
|
||||
struct sdmmc_task sc_discover_task; /* card attach/detach task */
|
||||
struct sdmmc_task sc_intr_task; /* card interrupt task */
|
||||
void *sc_scsibus; /* SCSI bus emulation softc */
|
||||
long sc_max_xfer; /* maximum transfer size */
|
||||
};
|
||||
|
||||
/*
|
||||
* Attach devices at the sdmmc bus.
|
||||
*/
|
||||
struct sdmmc_attach_args {
|
||||
struct scsi_link *scsi_link; /* XXX */
|
||||
struct sdmmc_function *sf;
|
||||
};
|
||||
|
||||
#define IPL_SDMMC IPL_BIO
|
||||
|
||||
#define SDMMC_LOCK(sc) lockmgr(&(sc)->sc_lock, LK_EXCLUSIVE, NULL)
|
||||
#define SDMMC_UNLOCK(sc) lockmgr(&(sc)->sc_lock, LK_RELEASE, NULL)
|
||||
#define SDMMC_ASSERT_LOCKED(sc) \
|
||||
KASSERT(lockstatus(&((sc))->sc_lock) == LK_EXCLUSIVE)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue