mirror of
https://github.com/fail0verflow/mini.git
synced 2024-11-16 08:29:25 +01:00
345 lines
7.4 KiB
C
345 lines
7.4 KiB
C
#include "types.h"
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#include "start.h"
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#include "memory.h"
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#include "utils.h"
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#include "gecko.h"
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#include "hollywood.h"
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#include "irq.h"
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void _dc_inval_entries(void *start, int count);
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void _dc_flush_entries(const void *start, int count);
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void _dc_flush(void);
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void _dc_inval(void);
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void _ic_inval(void);
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void _drain_write_buffer(void);
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void _tlb_inval(void);
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extern u32 __page_table[4096];
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#define LINESIZE 0x20
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#define CACHESIZE 0x4000
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// TODO: move to hollywood.h once we figure out WTF
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#define HW_100 (HW_REG_BASE + 0x100)
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#define HW_104 (HW_REG_BASE + 0x104)
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#define HW_108 (HW_REG_BASE + 0x108)
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#define HW_10c (HW_REG_BASE + 0x10c)
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#define HW_110 (HW_REG_BASE + 0x110)
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#define HW_114 (HW_REG_BASE + 0x114)
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#define HW_118 (HW_REG_BASE + 0x118)
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#define HW_11c (HW_REG_BASE + 0x11c)
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#define HW_120 (HW_REG_BASE + 0x120)
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#define HW_124 (HW_REG_BASE + 0x124)
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#define HW_130 (HW_REG_BASE + 0x130)
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#define HW_134 (HW_REG_BASE + 0x134)
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#define HW_138 (HW_REG_BASE + 0x138)
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#define HW_188 (HW_REG_BASE + 0x188)
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#define HW_18C (HW_REG_BASE + 0x18c)
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// what is this thing doing anyway?
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// and why only on reads?
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u32 _mc_read32(u32 addr)
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{
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u32 data;
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u32 tmp130 = 0;
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// this seems to be a bug workaround
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if(!(read32(HW_VERSION) & 0xF0))
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{
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tmp130 = read32(HW_130);
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write32(HW_130, tmp130 | 0x400);
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// Dummy reads?
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read32(HW_138);
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read32(HW_138);
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read32(HW_138);
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read32(HW_138);
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}
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data = read32(addr);
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read32(HW_VERSION); //???
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if(!(read32(HW_VERSION) & 0xF0))
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write32(HW_130, tmp130);
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return data;
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}
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void _magic_bullshit(int type) {
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u32 mask = 10;
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switch(type) {
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case 0: mask = 0x8000; break;
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case 1: mask = 0x4000; break;
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case 2: mask = 0x0001; break;
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case 3: mask = 0x0002; break;
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case 4: mask = 0x0004; break;
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case 5: mask = 0x0008; break;
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case 6: mask = 0x0010; break;
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case 7: mask = 0x0020; break;
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case 8: mask = 0x0040; break;
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case 9: mask = 0x0080; break;
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case 10: mask = 0x0100; break;
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case 11: mask = 0x1000; break;
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case 12: mask = 0x0000; break;
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}
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//NOTE: 0xd8b000x, not 0xd8b400x!
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u32 val = _mc_read32(0xd8b0008);
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if(val & mask) {
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if((type >= 2) && (type <= 10)) {
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while((read32(HW_18C) & 0xF) == 9)
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set32(HW_188, 0x10000);
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clear32(HW_188, 0x10000);
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set32(HW_188, 0x2000000);
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mask32(HW_124, 0x7c0, 0x280);
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set32(HW_134, 0x400);
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while((read32(HW_18C) & 0xF) != 9);
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set32(HW_100, 0x400);
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set32(HW_104, 0x400);
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set32(HW_108, 0x400);
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set32(HW_10c, 0x400);
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set32(HW_110, 0x400);
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set32(HW_114, 0x400);
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set32(HW_118, 0x400);
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set32(HW_11c, 0x400);
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set32(HW_120, 0x400);
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write32(0xd8b0008, _mc_read32(0xd8b0008) & (~mask));
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write32(0xd8b0008, _mc_read32(0xd8b0008) | mask);
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clear32(HW_134, 0x400);
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clear32(HW_100, 0x400);
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clear32(HW_104, 0x400);
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clear32(HW_108, 0x400);
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clear32(HW_10c, 0x400);
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clear32(HW_110, 0x400);
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clear32(HW_114, 0x400);
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clear32(HW_118, 0x400);
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clear32(HW_11c, 0x400);
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clear32(HW_120, 0x400);
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clear32(HW_188, 0x2000000);
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mask32(HW_124, 0x7c0, 0xc0);
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} else {
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if((type == 11) || (type == 0) || (type == 1)) {
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write32(0xd8b0008, val & (~mask));
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// wtfux
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write32(0xd8b0008, val | mask);
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write32(0xd8b0008, val | mask);
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write32(0xd8b0008, val | mask);
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}
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}
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}
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}
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void magic_bullshit(int type)
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{
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u32 cookie = irq_kill();
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_magic_bullshit(type);
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if(type != 0)
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_magic_bullshit(0);
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irq_restore(cookie);
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}
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void ahb_memflush(enum AHBDEV dev)
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{
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u32 cookie = irq_kill();
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u16 req = 0;
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u16 ack;
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int i;
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switch(dev)
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{
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case MEMORY:
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req = 1;
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break;
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case NAND:
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req = 8;
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break;
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default:
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if((dev >= RAW0) && (dev <= RAWF))
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{
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req = dev - RAW0;
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} else {
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gecko_printf("ahb_memflush(0x%x): Invalid device\n", dev);
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return;
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}
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break;
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}
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write16(MEM_FLUSHREQ, req);
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for(i=0;i<1000000;i++) {
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ack = read16(MEM_FLUSHACK);
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_magic_bullshit(0);
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if(ack == req)
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break;
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}
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write16(MEM_FLUSHREQ, 0);
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if(i>=1000000) {
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gecko_printf("ahb_memflush(%d): Flush (0x%x) did not ack!\n", dev, req);
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}
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irq_restore(cookie);
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}
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void dc_flushrange(const void *start, u32 size)
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{
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u32 cookie = irq_kill();
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if(size > 0x4000) {
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_dc_flush();
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} else {
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void *end = ALIGN_FORWARD(((u8*)start) + size, LINESIZE);
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start = ALIGN_BACKWARD(start, LINESIZE);
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_dc_flush_entries(start, (end - start) / LINESIZE);
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}
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_drain_write_buffer();
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ahb_memflush(MEMORY);
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irq_restore(cookie);
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}
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void dc_invalidaterange(void *start, u32 size)
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{
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u32 cookie = irq_kill();
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void *end = ALIGN_FORWARD(((u8*)start) + size, LINESIZE);
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start = ALIGN_BACKWARD(start, LINESIZE);
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_dc_inval_entries(start, (end - start) / LINESIZE);
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_magic_bullshit(0);
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irq_restore(cookie);
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}
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void dc_flushall(void)
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{
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u32 cookie = irq_kill();
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_dc_flush();
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_drain_write_buffer();
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ahb_memflush(MEMORY);
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irq_restore(cookie);
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}
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void ic_invalidateall(void)
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{
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u32 cookie = irq_kill();
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_ic_inval();
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_magic_bullshit(0);
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irq_restore(cookie);
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}
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void mem_protect(int enable, void *start, void *end)
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{
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write16(MEM_PROT, enable?1:0);
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write16(MEM_PROT_START, (((u32)start) & 0xFFFFFFF) >> 12);
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write16(MEM_PROT_END, (((u32)end) & 0xFFFFFFF) >> 12);
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udelay(10);
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}
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void mem_setswap(int enable)
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{
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u32 d = read32(HW_MEMMIRR);
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if((d & 0x20) && !enable)
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write32(HW_MEMMIRR, d & ~0x20);
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if((!(d & 0x20)) && enable)
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write32(HW_MEMMIRR, d | 0x20);
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}
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u32 dma_addr(void *p)
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{
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u32 addr = (u32)p;
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switch(addr>>20) {
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case 0xfff:
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case 0x0d4:
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case 0x0dc:
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if(read32(HW_MEMMIRR) & 0x20) {
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addr ^= 0x10000;
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}
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addr &= 0x0001FFFF;
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addr |= 0x0d400000;
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break;
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}
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//gecko_printf("DMA to %p: address %08x\n", p, addr);
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return addr;
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}
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#define SECTION 0x012
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#define NONBUFFERABLE 0x000
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#define BUFFERABLE 0x004
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#define WRITETHROUGH_CACHE 0x008
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#define WRITEBACK_CACHE 0x00C
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#define DOMAIN(x) ((x)<<5)
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#define AP_ROM 0x000
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#define AP_NOUSER 0x400
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#define AP_ROUSER 0x800
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#define AP_RWUSER 0xC00
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// from, to, size: units of 1MB
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void map_section(u32 from, u32 to, u32 size, u32 attributes)
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{
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attributes |= SECTION;
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while(size--) {
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__page_table[from++] = (to++<<20) | attributes;
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}
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}
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//#define NO_CACHES
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void mem_initialize(void)
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{
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u32 cr;
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u32 cookie = irq_kill();
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gecko_printf("MEM: cleaning up\n");
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_ic_inval();
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_dc_inval();
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_tlb_inval();
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gecko_printf("MEM: unprotecting memory\n");
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mem_protect(0,NULL,NULL);
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gecko_printf("MEM: mapping sections\n");
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memset32(__page_table, 0, 16384);
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map_section(0x000, 0x000, 0x018, WRITEBACK_CACHE | DOMAIN(0) | AP_RWUSER);
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map_section(0x100, 0x100, 0x040, WRITEBACK_CACHE | DOMAIN(0) | AP_RWUSER);
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map_section(0x0d0, 0x0d0, 0x001, NONBUFFERABLE | DOMAIN(0) | AP_RWUSER);
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map_section(0x0d8, 0x0d8, 0x001, NONBUFFERABLE | DOMAIN(0) | AP_RWUSER);
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map_section(0xfff, 0xfff, 0x001, WRITEBACK_CACHE | DOMAIN(0) | AP_RWUSER);
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set_dacr(0xFFFFFFFF); //manager access for all domains, ignore AP
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set_ttbr((u32)__page_table); //configure translation table
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_drain_write_buffer();
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cr = get_cr();
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#ifndef NO_CACHES
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gecko_printf("MEM: enabling caches\n");
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cr |= 0x1004; //ICACHE/DCACHE and MMU enable
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set_cr(cr);
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gecko_printf("MEM: enabling MMU\n");
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cr |= 0x0001; //ICACHE/DCACHE and MMU enable
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set_cr(cr);
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#endif
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gecko_printf("MEM: init done\n");
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irq_restore(cookie);
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}
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void mem_shutdown(void)
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{
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u32 cookie = irq_kill();
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_dc_flush();
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_drain_write_buffer();
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u32 cr = get_cr();
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cr &= ~0x1005; //disable ICACHE, DCACHE, MMU
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set_cr(cr);
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_ic_inval();
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_dc_inval();
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_tlb_inval();
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irq_restore(cookie);
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}
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