11 Commits

Author	SHA1	Message	Date
ikari	899c8139fc	FPGA: free some block RAM when using ChipScope	2019-07-05 13:40:22 +02:00
ikari	a01fb3d6a1	Revise project structure ... Makefile based build for FPGA configurations, firmware, SuperCIC, release packaging. Probably needs more polishing.	2019-05-20 00:33:28 +02:00
ikari	e07b6e2508	MSU1: avoid unaligned SD reads (FPGA side)	2017-04-30 23:29:23 +02:00
ikari	5f72758c7b	Fix DAC timing for Rev.E,F,H ... Previous fix for Rev.G broke timing for all other revisions resulting in nasty distortion. Hopefully still works with all Rev.Gs ;)	2017-03-10 00:30:21 +01:00
Maximilian Rehkopf	2a1a539f77	Revert to previous I2S timing for DAC (hopefully helps with Rev.G issues)	2016-09-27 17:46:06 +02:00
ikari	b136c13a02	Discard superfluous registers in DAC interpolation filter	2016-04-24 01:49:05 +02:00
ikari	4ee41ec20c	rework external DAC control (play+reset)	2016-04-24 01:48:26 +02:00
ikari	829953b034	DAC: improve audio quality (nearest neighbor -> CIC filter), fix playback rate	2016-04-01 02:00:29 +02:00
ikari_01	dedcb9ff5e	DAC: volume boost setting for MSU1	2015-10-21 00:12:30 +02:00
Maximilian Rehkopf	1a52da6272	FPGA: Adjust DAC I²S signal timing	2012-07-09 01:41:47 +02:00
ikari	e57c4aa450	FPGA/cx4: initial commit	2011-10-23 04:10:55 +02:00