ikari
e35792e068
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
ikari
ab41f61374
FPGA: misc cleanup
2019-07-05 14:03:05 +02:00
ikari
a01fb3d6a1
Revise project structure
...
Makefile based build for FPGA configurations, firmware, SuperCIC,
release packaging. Probably needs more polishing.
2019-05-20 00:33:28 +02:00
ikari
9d4d669689
Avoid memory corruption on MCU writes
...
(address invalid before end of write strobe)
2019-03-26 10:29:39 +01:00
ikari
6cccbe9ac7
Update plethora of generated Xilinx files...
2019-02-28 18:52:22 +01:00
ikari
7d5dd9d2b4
Feature: Brightness limit
...
This intercepts and overrides writes to $2100, limiting the brightness
written to a configurable value (8..15).
The FPGA feature bitfield is extended to 16 bits to accomodate the 4
additional bits for the brightness limit.
The menu itself does not apply the brightness limit on FPGA level but
"fakes" it by setting the brightness manually. The newly added menu
change hooks are used to reflect the brightness setting as soon as it is
changed during selection.
2018-07-15 00:50:11 +02:00
Maximilian Rehkopf
81efb6f631
Merge branch 'develop' of ssh://github.com/mrehkopf/sd2snes into develop
2017-05-01 09:28:13 +02:00
ikari
7de6107b51
Update ISE project files
2017-04-30 23:38:44 +02:00
Maximilian Rehkopf
21e6bd9f8a
Properly name ROMSEL signal, filter like other control signals
2016-09-28 17:46:09 +02:00
ikari
43d53557af
Another in-game hook overhaul
...
- Offload any flow control to FPGA to shave off some more CPU cycles
- Blank screen on reset to menu to avoid graphical artifacts
2016-09-14 01:39:59 +02:00
ikari
6b06fce13f
FPGA: update project settings
2016-08-16 04:01:57 +02:00
ikari
4ee41ec20c
rework external DAC control (play+reset)
2016-04-24 01:48:26 +02:00
ikari
829953b034
DAC: improve audio quality (nearest neighbor -> CIC filter), fix playback rate
2016-04-01 02:00:29 +02:00
ikari_01
dedcb9ff5e
DAC: volume boost setting for MSU1
2015-10-21 00:12:30 +02:00
ikari_01
22e07425e6
Cx4: Remove all core related multi-cycle constraints; timing closure
2015-08-29 14:52:01 +02:00
ikari_01
16c870a55d
FPGA/cx4: Project file updates, remove some harmful multi-cycle constraints
2015-02-01 09:42:48 +01:00
ikari_01
4bdcffdfa6
FPGA: reconstitute more aggressive SNES control signal filtering; unify edge detection and data buffering
2014-10-08 00:00:43 +02:00
ikari_01
278eedca6b
Snoop $4200 register write (sense auto joypad read); double BRAM buffer size
...
Rearrange memory map of BRAM hook
2014-09-30 17:46:42 +02:00
ikari_01
470b286572
FPGA: new memory sharing for all sub configurations; Cx4 speed switch
2014-09-18 17:32:56 +02:00
Maximilian Rehkopf
7ba9196e6a
FPGA: update ISE project files
2014-05-10 16:53:09 +02:00
Maximilian Rehkopf
2a1ef40796
FPGA/cx4: adjust Cx4 CPU timing
2012-05-19 18:07:13 +02:00
Maximilian Rehkopf
f5caf21fac
FPGA: slightly tighten timing constraints
2012-05-02 10:41:07 +02:00
ikari
e2f33c28c9
FPGA: pull-up SD clock
2012-02-27 22:12:35 +01:00
ikari
f0a2e85c65
FPGA: updated project files
2012-01-14 23:16:57 +01:00
ikari
3dd64cb98f
FPGA/cx4: timing closure
2011-11-01 20:56:30 +01:00
ikari
7643790fed
FPGA/Cx4: fully operational except reset vector area
2011-10-30 01:54:39 +02:00
ikari
8c76dfbeb6
FPGA/Cx4: WIP
2011-10-27 15:42:13 +02:00
ikari
e57c4aa450
FPGA/cx4: initial commit
2011-10-23 04:10:55 +02:00
