This allows for savestate handler execution directly from the menu ROM
bank without having to copy it to block RAM or similar.
(this seems to be causing unresolvable issues with HDMA interrupting
NMI/IRQ so it will be due for an overhaul)
Databus direction was reversed according to the ROMSEL signal, not
taking into account SRAM that is mapped outside of active ROMSEL areas.
Instead take into account anything where data is sourced from the
cartridge (ROM_HIT).
Only snoop registers 2100-2183 and ignore the ones we supply ourselves.
e.g. Trying to snoop BS-X registers would result in the SNES not being
able to read them at all, freezing the
BS-X BIOS at the startup screen.
On some occasions data output can be enabled before data is valid.
This results in needless data line toggling which in turn can cause
coupling into other signals, thereby potentially altering the ROM address
and putting wrong data on the bus, etc.
Use a narrowed output enable signal for SNES read cases to prevent this
effect.
CPU_CLK is substantially shorter than RD# during DMA transfers.
Access cycle end was previously based on falling edge of CPU_CLK.
This resulted in premature yielding of RAM access to the bus and in
consequence incorrect values leaking onto the bus.
