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4 Commits

Author SHA1 Message Date
Maximilian Rehkopf
5b0f22d411 Ensure MSU-1 data address increment at end of DMA (#208) 
* Ensure MSU-1 data address increment at end of DMA

* fix MSU1 address increment for rest of the FPGA cores

* update generated files
 2023-03-30 11:09:25 +02:00
ikari
e9a11762d9 FPGA: General update of generated files 2023-02-03 01:37:32 +01:00
ikari
e35792e068 FPGA: Bump Quartus version, update generated files 2021-07-29 23:06:25 +02:00
ikari
5b3f38ee80 FPGA: Move DSPx to separate core 2020-09-24 00:52:50 +02:00