6 Commits

Author	SHA1	Message	Date
ikari	858d660569	Update a slew of Xilinx autogenerated files	2025-06-24 10:58:46 +02:00
Maximilian Rehkopf	5b0f22d411	Ensure MSU-1 data address increment at end of DMA (#208) ... * Ensure MSU-1 data address increment at end of DMA * fix MSU1 address increment for rest of the FPGA cores * update generated files	2023-03-30 11:09:25 +02:00
ikari	e9a11762d9	FPGA: General update of generated files	2023-02-03 01:37:32 +01:00
ikari	e35792e068	FPGA: Bump Quartus version, update generated files	2021-07-29 23:06:25 +02:00
ikari	ab41f61374	FPGA: misc cleanup	2019-07-05 14:03:05 +02:00
ikari	a01fb3d6a1	Revise project structure ... Makefile based build for FPGA configurations, firmware, SuperCIC, release packaging. Probably needs more polishing.	2019-05-20 00:33:28 +02:00