ikari 858d660569 Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

..

ipcore_dir

Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

address.v

FPGA: fix ROM address detection to exclude WRAM

2021-07-28 11:09:49 +02:00

cheat.v

comments, wording, cleanup, cosmetics

2021-07-28 02:19:06 +02:00

clk_test.v

Cx4: run at actual 80MHz (20MHz effective) instead of 86MHz

2016-08-16 04:00:26 +02:00

config.vh

Revise project structure

2019-05-20 00:33:28 +02:00

cx4_datram.qip

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

cx4_datram.v

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

cx4_datrom.mif

Revise project structure

2019-05-20 00:33:28 +02:00

cx4_datrom.qip

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

cx4_datrom.v

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

cx4_mul.qip

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

cx4_mul.v

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

cx4_pgmrom.qip

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

cx4_pgmrom.v

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

cx4.v

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

dac_buf.qip

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

dac_buf.v

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

dac.v

FPGA: free some block RAM when using ChipScope

2019-07-05 13:40:22 +02:00

dcm.v

Cx4: run at actual 80MHz (20MHz effective) instead of 86MHz

2016-08-16 04:00:26 +02:00

main_assignment_defaults.qdf

Revise project structure

2019-05-20 00:33:28 +02:00

main.qsf

FPGA: General update of generated files

2023-02-03 01:37:32 +01:00

main.sdc

FPGA: Change MK3 FPGA clock input from 24MHz to 8MHz

2023-02-03 01:37:31 +01:00

main.ucf

Properly name ROMSEL signal, filter like other control signals

2016-09-28 17:46:09 +02:00

main.v

FPGA: fix ROM address detection to exclude WRAM

2021-07-28 11:09:49 +02:00

Makefile

FPGA build: add header files to prerequisites

2021-07-28 01:26:42 +02:00

mcu_cmd.v

Feature: Brightness limit

2018-07-15 00:50:11 +02:00

msu_databuf.qip

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

msu_databuf.v

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

msu.v

Ensure MSU-1 data address increment at end of DMA (#208)

2023-03-30 11:09:25 +02:00

pll.ppf

Revise project structure

2019-05-20 00:33:28 +02:00

pll.qip

FPGA: General update of generated files

2023-02-03 01:37:32 +01:00

pll.v

FPGA: Change MK3 FPGA clock input from 24MHz to 8MHz

2023-02-03 01:37:31 +01:00

sd2snes_cx4.qpf

Revise project structure

2019-05-20 00:33:28 +02:00

sd2snes_cx4.xise

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

sd_dma.v

Fix SD clock glitch on FPGA->MCU handoff after partial DMA

2017-04-30 23:30:26 +02:00

snescmd_buf.qip

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

snescmd_buf.v

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

spi.v

FPGA: misc cleanup

2019-07-05 14:03:05 +02:00