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Implement Maxwell3D Shader Program Registers
This commit added basic shader program registers, they simply track the address a shader is pointed to at the moment. No parsing of the shader program is done within them.
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@ -326,5 +326,41 @@ namespace skyline::gpu::interconnect {
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scissor.offset.y = bounds.minimum;
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scissor.extent.height = bounds.maximum - bounds.minimum;
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}
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/* Shader Program */
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private:
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struct Shader {
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bool enabled{false};
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u32 offset{}; //!< Offset of the shader from the base IOVA
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span<u8> data; //!< The shader bytecode in the CPU AS
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};
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u64 shaderBaseIova{}; //!< The base IOVA that shaders are located at an offset from
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std::array<Shader, maxwell3d::StageCount> boundShaders{};
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public:
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void SetShaderBaseIovaHigh(u32 high) {
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shaderBaseIova = (shaderBaseIova & std::numeric_limits<u32>::max()) | (static_cast<u64>(high) << 32);
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for (auto &shader : boundShaders)
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shader.data = span<u8>{};
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}
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void SetShaderBaseIovaLow(u32 low) {
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shaderBaseIova = (shaderBaseIova & (static_cast<u64>(std::numeric_limits<u32>::max()) << 32)) | low;
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for (auto &shader : boundShaders)
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shader.data = span<u8>{};
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}
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void SetShaderEnabled(maxwell3d::StageId stage, bool enabled) {
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auto &shader{boundShaders[static_cast<size_t>(stage)]};
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shader.enabled = enabled;
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shader.data = span<u8>{};
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}
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void SetShaderOffset(maxwell3d::StageId stage, u32 offset) {
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auto &shader{boundShaders[static_cast<size_t>(stage)]};
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shader.offset = offset;
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shader.data = span<u8>{};
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}
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};
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}
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@ -525,5 +525,37 @@ namespace skyline::soc::gm20b::engine::maxwell3d::type {
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};
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static_assert(sizeof(SemaphoreInfo) == sizeof(u32));
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constexpr static size_t StageCount{6}; //!< Amount of pipeline stages on Maxwell 3D
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/**
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* @brief All the pipeline stages that Maxwell3D supports for draws
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*/
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enum class StageId {
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VertexA = 0,
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VertexB = 1,
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TessellationControl = 2,
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TessellationEvaluation = 3,
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Geometry = 4,
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Fragment = 5,
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};
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static_assert(static_cast<size_t>(StageId::Fragment) + 1 == StageCount);
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/**
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* @brief The arguments to set a shader program for a pipeline stage
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*/
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struct SetProgramInfo {
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struct {
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bool enable : 1;
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u8 _pad0_ : 3;
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StageId stage : 4;
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u32 _pad1_ : 24;
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} info;
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u32 offset; //!< Offset from the base shader memory IOVA
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u32 _pad2_;
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u32 gprCount; //!< Amount of GPRs used by the shader program
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u32 _pad3_[12];
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};
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static_assert(sizeof(SetProgramInfo) == (sizeof(u32) * 0x10));
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#pragma pack(pop)
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}
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@ -226,6 +226,14 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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MAXWELL3D_CASE(renderTargetControl, {
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context.UpdateRenderTargetControl(renderTargetControl);
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})
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#define SET_SHADER_ENABLE_CALLBACK(z, index, data) \
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MAXWELL3D_ARRAY_STRUCT_CASE(setProgram, index, info, { \
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context.SetShaderEnabled(info.stage, info.enable); \
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})
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BOOST_PP_REPEAT(6, SET_SHADER_ENABLE_CALLBACK, 0)
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static_assert(type::StageCount == 6 && type::StageCount < BOOST_PP_LIMIT_REPEAT);
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#undef SET_SHADER_ENABLE_CALLBACK
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}
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}
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@ -282,6 +290,14 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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}
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})
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#define SET_SHADER_OFFSET_CALLBACK(z, index, data) \
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MAXWELL3D_ARRAY_STRUCT_CASE(setProgram, index, offset, { \
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context.SetShaderOffset(registers.setProgram[index].info.stage, offset); \
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})
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BOOST_PP_REPEAT(6, SET_SHADER_OFFSET_CALLBACK, 0)
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static_assert(type::StageCount == 6 && type::StageCount < BOOST_PP_LIMIT_REPEAT);
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MAXWELL3D_ARRAY_CASE(firmwareCall, 4, {
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registers.raw[0xD00] = 1;
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})
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@ -200,6 +200,9 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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Register<0x6C0, Semaphore> semaphore;
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Register<0x780, std::array<type::Blend, type::RenderTargetCount>> independentBlend;
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Register<0x800, std::array<type::SetProgramInfo, type::StageCount>> setProgram;
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Register<0x8C0, u32[0x20]> firmwareCall;
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};
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static_assert(sizeof(Registers) == (RegisterCount * sizeof(u32)));
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