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Fix Depth RT layer stride
The layer stride provided by the depth register in Maxwell3D needs to be shifted by 2, this caused the stride to be 1/4th of what it needed to be resulting in OOB access.
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@ -87,7 +87,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
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/* Depth Render Target */
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void DepthRenderTargetState::EngineRegisters::DirtyBind(DirtyManager &manager, dirty::Handle handle) const {
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manager.Bind(handle, ztSize, ztOffset, ztFormat, ztBlockSize, ztArrayPitch, ztSelect, ztLayer, surfaceClip);
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manager.Bind(handle, ztSize, ztOffset, ztFormat, ztBlockSize, ztArrayPitchLsr2, ztSelect, ztLayer, surfaceClip);
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}
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DepthRenderTargetState::DepthRenderTargetState(dirty::Handle dirtyHandle, DirtyManager &manager, const EngineRegisters &engine) : engine{manager, dirtyHandle, engine} {}
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@ -121,7 +121,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
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.blockDepth = engine->ztBlockSize.BlockDepth(),
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};
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guest.layerStride = (guest.baseArrayLayer > 1 || guest.layerCount > 1) ? engine->ztArrayPitch : 0;
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guest.layerStride = (guest.baseArrayLayer > 1 || guest.layerCount > 1) ? engine->ZtArrayPitch() : 0;
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auto mappings{ctx.channelCtx.asCtx->gmmu.TranslateRange(engine->ztOffset, guest.GetSize())};
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guest.mappings.assign(mappings.begin(), mappings.end());
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@ -40,12 +40,16 @@ namespace skyline::gpu::interconnect::maxwell3d {
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const soc::gm20b::engine::Address &ztOffset;
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const engine::ZtFormat &ztFormat;
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const engine::ZtBlockSize &ztBlockSize;
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const u32 &ztArrayPitch;
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const u32 &ztArrayPitchLsr2;
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const engine::ZtSelect &ztSelect;
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const engine::ZtLayer &ztLayer;
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const engine::SurfaceClip &surfaceClip;
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void DirtyBind(DirtyManager &manager, dirty::Handle handle) const;
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u32 ZtArrayPitch() const {
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return ztArrayPitchLsr2 << 2;
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}
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};
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private:
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