From 476c070c7ab58cf67317435259c7ff97bd630633 Mon Sep 17 00:00:00 2001
From: PixelyIon <pixelyion@protonmail.com>
Date: Tue, 16 Nov 2021 15:13:15 +0530
Subject: [PATCH] Fix Minor Maxwell3D Register Ordering Issues

We order all registers in ascending order, a few registers namely `colorLogicOp`, `colorWriteMask`, `clearBuffers` and `depthBiasClamp` were erroneously not following this order which has now been fixed.
---
 .../skyline/soc/gm20b/engines/maxwell_3d.h    | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/app/src/main/cpp/skyline/soc/gm20b/engines/maxwell_3d.h b/app/src/main/cpp/skyline/soc/gm20b/engines/maxwell_3d.h
index 5816ef36..95337903 100644
--- a/app/src/main/cpp/skyline/soc/gm20b/engines/maxwell_3d.h
+++ b/app/src/main/cpp/skyline/soc/gm20b/engines/maxwell_3d.h
@@ -204,18 +204,25 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
 
             Register<0x5A1, u32> provokingVertexIsLast;
 
+            Register<0x61F, float> depthBiasClamp;
+
             Register<0x646, u32> cullFaceEnable;
             Register<0x647, type::FrontFace> frontFace;
             Register<0x648, type::CullFace> cullFace;
 
             Register<0x649, u32> pixelCentreImage;
             Register<0x64B, u32> viewportTransformEnable;
+            Register<0x64F, type::ViewVolumeClipControl> viewVolumeClipControl;
+
+            struct ColorLogicOp {
+                u32 enable;
+                type::ColorLogicOp type;
+            };
+            Register<0x671, ColorLogicOp> colorLogicOp;
+
             Register<0x674, type::ClearBuffers> clearBuffers;
             Register<0x680, std::array<type::ColorWriteMask, type::RenderTargetCount>> colorWriteMask;
 
-            Register<0x61F, float> depthBiasClamp;
-            Register<0x64F, type::ViewVolumeClipControl> viewVolumeClipControl;
-
             struct Semaphore {
                 type::Address address; // 0x6C0
                 u32 payload; // 0x6C2
@@ -223,12 +230,6 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
             };
             Register<0x6C0, Semaphore> semaphore;
 
-            struct ColorLogicOp {
-                u32 enable;
-                type::ColorLogicOp type;
-            };
-            Register<0x671, ColorLogicOp> colorLogicOp;
-
             struct VertexBuffer {
                 union {
                     u32 raw;